321 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 42; RUN: llc -mtriple=aarch64 -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD3; RUN: llc -mtriple=aarch64 -global-isel -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-GI4 5define i8 @scmp.8.8(i8 %x, i8 %y) nounwind {6; CHECK-SD-LABEL: scmp.8.8:7; CHECK-SD: // %bb.0:8; CHECK-SD-NEXT: sxtb w8, w09; CHECK-SD-NEXT: cmp w8, w1, sxtb10; CHECK-SD-NEXT: cset w8, gt11; CHECK-SD-NEXT: csinv w0, w8, wzr, ge12; CHECK-SD-NEXT: ret13;14; CHECK-GI-LABEL: scmp.8.8:15; CHECK-GI: // %bb.0:16; CHECK-GI-NEXT: sxtb w8, w017; CHECK-GI-NEXT: sxtb w9, w118; CHECK-GI-NEXT: cmp w8, w919; CHECK-GI-NEXT: cset w8, gt20; CHECK-GI-NEXT: csinv w0, w8, wzr, ge21; CHECK-GI-NEXT: ret22 %1 = call i8 @llvm.scmp(i8 %x, i8 %y)23 ret i8 %124}25 26define i8 @scmp.8.16(i16 %x, i16 %y) nounwind {27; CHECK-SD-LABEL: scmp.8.16:28; CHECK-SD: // %bb.0:29; CHECK-SD-NEXT: sxth w8, w030; CHECK-SD-NEXT: cmp w8, w1, sxth31; CHECK-SD-NEXT: cset w8, gt32; CHECK-SD-NEXT: csinv w0, w8, wzr, ge33; CHECK-SD-NEXT: ret34;35; CHECK-GI-LABEL: scmp.8.16:36; CHECK-GI: // %bb.0:37; CHECK-GI-NEXT: sxth w8, w038; CHECK-GI-NEXT: sxth w9, w139; CHECK-GI-NEXT: cmp w8, w940; CHECK-GI-NEXT: cset w8, gt41; CHECK-GI-NEXT: csinv w0, w8, wzr, ge42; CHECK-GI-NEXT: ret43 %1 = call i8 @llvm.scmp(i16 %x, i16 %y)44 ret i8 %145}46 47define i8 @scmp.8.32(i32 %x, i32 %y) nounwind {48; CHECK-LABEL: scmp.8.32:49; CHECK: // %bb.0:50; CHECK-NEXT: cmp w0, w151; CHECK-NEXT: cset w8, gt52; CHECK-NEXT: csinv w0, w8, wzr, ge53; CHECK-NEXT: ret54 %1 = call i8 @llvm.scmp(i32 %x, i32 %y)55 ret i8 %156}57 58define i8 @scmp.8.64(i64 %x, i64 %y) nounwind {59; CHECK-LABEL: scmp.8.64:60; CHECK: // %bb.0:61; CHECK-NEXT: cmp x0, x162; CHECK-NEXT: cset w8, gt63; CHECK-NEXT: csinv w0, w8, wzr, ge64; CHECK-NEXT: ret65 %1 = call i8 @llvm.scmp(i64 %x, i64 %y)66 ret i8 %167}68 69define i8 @scmp.8.128(i128 %x, i128 %y) nounwind {70; CHECK-SD-LABEL: scmp.8.128:71; CHECK-SD: // %bb.0:72; CHECK-SD-NEXT: cmp x2, x073; CHECK-SD-NEXT: sbcs xzr, x3, x174; CHECK-SD-NEXT: cset w8, lt75; CHECK-SD-NEXT: cmp x0, x276; CHECK-SD-NEXT: sbcs xzr, x1, x377; CHECK-SD-NEXT: csinv w0, w8, wzr, ge78; CHECK-SD-NEXT: ret79;80; CHECK-GI-LABEL: scmp.8.128:81; CHECK-GI: // %bb.0:82; CHECK-GI-NEXT: cmp x0, x283; CHECK-GI-NEXT: cset w8, hi84; CHECK-GI-NEXT: cmp x1, x385; CHECK-GI-NEXT: cset w9, gt86; CHECK-GI-NEXT: csel w8, w8, w9, eq87; CHECK-GI-NEXT: cmp x0, x288; CHECK-GI-NEXT: cset w9, lo89; CHECK-GI-NEXT: cmp x1, x390; CHECK-GI-NEXT: cset w10, lt91; CHECK-GI-NEXT: csel w9, w9, w10, eq92; CHECK-GI-NEXT: tst w8, #0x193; CHECK-GI-NEXT: cset w8, ne94; CHECK-GI-NEXT: tst w9, #0x195; CHECK-GI-NEXT: csinv w0, w8, wzr, eq96; CHECK-GI-NEXT: ret97 %1 = call i8 @llvm.scmp(i128 %x, i128 %y)98 ret i8 %199}100 101define i32 @scmp.32.32(i32 %x, i32 %y) nounwind {102; CHECK-LABEL: scmp.32.32:103; CHECK: // %bb.0:104; CHECK-NEXT: cmp w0, w1105; CHECK-NEXT: cset w8, gt106; CHECK-NEXT: csinv w0, w8, wzr, ge107; CHECK-NEXT: ret108 %1 = call i32 @llvm.scmp(i32 %x, i32 %y)109 ret i32 %1110}111 112define i32 @scmp.32.64(i64 %x, i64 %y) nounwind {113; CHECK-LABEL: scmp.32.64:114; CHECK: // %bb.0:115; CHECK-NEXT: cmp x0, x1116; CHECK-NEXT: cset w8, gt117; CHECK-NEXT: csinv w0, w8, wzr, ge118; CHECK-NEXT: ret119 %1 = call i32 @llvm.scmp(i64 %x, i64 %y)120 ret i32 %1121}122 123define i64 @scmp.64.64(i64 %x, i64 %y) nounwind {124; CHECK-LABEL: scmp.64.64:125; CHECK: // %bb.0:126; CHECK-NEXT: cmp x0, x1127; CHECK-NEXT: cset x8, gt128; CHECK-NEXT: csinv x0, x8, xzr, ge129; CHECK-NEXT: ret130 %1 = call i64 @llvm.scmp(i64 %x, i64 %y)131 ret i64 %1132}133 134define <8 x i8> @s_v8i8(<8 x i8> %a, <8 x i8> %b) {135; CHECK-LABEL: s_v8i8:136; CHECK: // %bb.0: // %entry137; CHECK-NEXT: cmgt v2.8b, v0.8b, v1.8b138; CHECK-NEXT: cmgt v0.8b, v1.8b, v0.8b139; CHECK-NEXT: sub v0.8b, v0.8b, v2.8b140; CHECK-NEXT: ret141entry:142 %c = call <8 x i8> @llvm.scmp(<8 x i8> %a, <8 x i8> %b)143 ret <8 x i8> %c144}145 146define <16 x i8> @s_v16i8(<16 x i8> %a, <16 x i8> %b) {147; CHECK-LABEL: s_v16i8:148; CHECK: // %bb.0: // %entry149; CHECK-NEXT: cmgt v2.16b, v0.16b, v1.16b150; CHECK-NEXT: cmgt v0.16b, v1.16b, v0.16b151; CHECK-NEXT: sub v0.16b, v0.16b, v2.16b152; CHECK-NEXT: ret153entry:154 %c = call <16 x i8> @llvm.scmp(<16 x i8> %a, <16 x i8> %b)155 ret <16 x i8> %c156}157 158define <4 x i16> @s_v4i16(<4 x i16> %a, <4 x i16> %b) {159; CHECK-LABEL: s_v4i16:160; CHECK: // %bb.0: // %entry161; CHECK-NEXT: cmgt v2.4h, v0.4h, v1.4h162; CHECK-NEXT: cmgt v0.4h, v1.4h, v0.4h163; CHECK-NEXT: sub v0.4h, v0.4h, v2.4h164; CHECK-NEXT: ret165entry:166 %c = call <4 x i16> @llvm.scmp(<4 x i16> %a, <4 x i16> %b)167 ret <4 x i16> %c168}169 170define <8 x i16> @s_v8i16(<8 x i16> %a, <8 x i16> %b) {171; CHECK-LABEL: s_v8i16:172; CHECK: // %bb.0: // %entry173; CHECK-NEXT: cmgt v2.8h, v0.8h, v1.8h174; CHECK-NEXT: cmgt v0.8h, v1.8h, v0.8h175; CHECK-NEXT: sub v0.8h, v0.8h, v2.8h176; CHECK-NEXT: ret177entry:178 %c = call <8 x i16> @llvm.scmp(<8 x i16> %a, <8 x i16> %b)179 ret <8 x i16> %c180}181 182define <16 x i16> @s_v16i16(<16 x i16> %a, <16 x i16> %b) {183; CHECK-SD-LABEL: s_v16i16:184; CHECK-SD: // %bb.0: // %entry185; CHECK-SD-NEXT: cmgt v4.8h, v1.8h, v3.8h186; CHECK-SD-NEXT: cmgt v5.8h, v0.8h, v2.8h187; CHECK-SD-NEXT: cmgt v0.8h, v2.8h, v0.8h188; CHECK-SD-NEXT: cmgt v1.8h, v3.8h, v1.8h189; CHECK-SD-NEXT: sub v0.8h, v0.8h, v5.8h190; CHECK-SD-NEXT: sub v1.8h, v1.8h, v4.8h191; CHECK-SD-NEXT: ret192;193; CHECK-GI-LABEL: s_v16i16:194; CHECK-GI: // %bb.0: // %entry195; CHECK-GI-NEXT: cmgt v4.8h, v0.8h, v2.8h196; CHECK-GI-NEXT: cmgt v5.8h, v1.8h, v3.8h197; CHECK-GI-NEXT: cmgt v0.8h, v2.8h, v0.8h198; CHECK-GI-NEXT: cmgt v1.8h, v3.8h, v1.8h199; CHECK-GI-NEXT: sub v0.8h, v0.8h, v4.8h200; CHECK-GI-NEXT: sub v1.8h, v1.8h, v5.8h201; CHECK-GI-NEXT: ret202entry:203 %c = call <16 x i16> @llvm.scmp(<16 x i16> %a, <16 x i16> %b)204 ret <16 x i16> %c205}206 207define <2 x i32> @s_v2i32(<2 x i32> %a, <2 x i32> %b) {208; CHECK-LABEL: s_v2i32:209; CHECK: // %bb.0: // %entry210; CHECK-NEXT: cmgt v2.2s, v0.2s, v1.2s211; CHECK-NEXT: cmgt v0.2s, v1.2s, v0.2s212; CHECK-NEXT: sub v0.2s, v0.2s, v2.2s213; CHECK-NEXT: ret214entry:215 %c = call <2 x i32> @llvm.scmp(<2 x i32> %a, <2 x i32> %b)216 ret <2 x i32> %c217}218 219define <4 x i32> @s_v4i32(<4 x i32> %a, <4 x i32> %b) {220; CHECK-LABEL: s_v4i32:221; CHECK: // %bb.0: // %entry222; CHECK-NEXT: cmgt v2.4s, v0.4s, v1.4s223; CHECK-NEXT: cmgt v0.4s, v1.4s, v0.4s224; CHECK-NEXT: sub v0.4s, v0.4s, v2.4s225; CHECK-NEXT: ret226entry:227 %c = call <4 x i32> @llvm.scmp(<4 x i32> %a, <4 x i32> %b)228 ret <4 x i32> %c229}230 231define <8 x i32> @s_v8i32(<8 x i32> %a, <8 x i32> %b) {232; CHECK-SD-LABEL: s_v8i32:233; CHECK-SD: // %bb.0: // %entry234; CHECK-SD-NEXT: cmgt v4.4s, v1.4s, v3.4s235; CHECK-SD-NEXT: cmgt v5.4s, v0.4s, v2.4s236; CHECK-SD-NEXT: cmgt v0.4s, v2.4s, v0.4s237; CHECK-SD-NEXT: cmgt v1.4s, v3.4s, v1.4s238; CHECK-SD-NEXT: sub v0.4s, v0.4s, v5.4s239; CHECK-SD-NEXT: sub v1.4s, v1.4s, v4.4s240; CHECK-SD-NEXT: ret241;242; CHECK-GI-LABEL: s_v8i32:243; CHECK-GI: // %bb.0: // %entry244; CHECK-GI-NEXT: cmgt v4.4s, v0.4s, v2.4s245; CHECK-GI-NEXT: cmgt v5.4s, v1.4s, v3.4s246; CHECK-GI-NEXT: cmgt v0.4s, v2.4s, v0.4s247; CHECK-GI-NEXT: cmgt v1.4s, v3.4s, v1.4s248; CHECK-GI-NEXT: sub v0.4s, v0.4s, v4.4s249; CHECK-GI-NEXT: sub v1.4s, v1.4s, v5.4s250; CHECK-GI-NEXT: ret251entry:252 %c = call <8 x i32> @llvm.scmp(<8 x i32> %a, <8 x i32> %b)253 ret <8 x i32> %c254}255 256define <2 x i64> @s_v2i64(<2 x i64> %a, <2 x i64> %b) {257; CHECK-LABEL: s_v2i64:258; CHECK: // %bb.0: // %entry259; CHECK-NEXT: cmgt v2.2d, v0.2d, v1.2d260; CHECK-NEXT: cmgt v0.2d, v1.2d, v0.2d261; CHECK-NEXT: sub v0.2d, v0.2d, v2.2d262; CHECK-NEXT: ret263entry:264 %c = call <2 x i64> @llvm.scmp(<2 x i64> %a, <2 x i64> %b)265 ret <2 x i64> %c266}267 268define <4 x i64> @s_v4i64(<4 x i64> %a, <4 x i64> %b) {269; CHECK-SD-LABEL: s_v4i64:270; CHECK-SD: // %bb.0: // %entry271; CHECK-SD-NEXT: cmgt v4.2d, v1.2d, v3.2d272; CHECK-SD-NEXT: cmgt v5.2d, v0.2d, v2.2d273; CHECK-SD-NEXT: cmgt v0.2d, v2.2d, v0.2d274; CHECK-SD-NEXT: cmgt v1.2d, v3.2d, v1.2d275; CHECK-SD-NEXT: sub v0.2d, v0.2d, v5.2d276; CHECK-SD-NEXT: sub v1.2d, v1.2d, v4.2d277; CHECK-SD-NEXT: ret278;279; CHECK-GI-LABEL: s_v4i64:280; CHECK-GI: // %bb.0: // %entry281; CHECK-GI-NEXT: cmgt v4.2d, v0.2d, v2.2d282; CHECK-GI-NEXT: cmgt v5.2d, v1.2d, v3.2d283; CHECK-GI-NEXT: cmgt v0.2d, v2.2d, v0.2d284; CHECK-GI-NEXT: cmgt v1.2d, v3.2d, v1.2d285; CHECK-GI-NEXT: sub v0.2d, v0.2d, v4.2d286; CHECK-GI-NEXT: sub v1.2d, v1.2d, v5.2d287; CHECK-GI-NEXT: ret288entry:289 %c = call <4 x i64> @llvm.scmp(<4 x i64> %a, <4 x i64> %b)290 ret <4 x i64> %c291}292 293define <16 x i8> @signOf_neon_scmp(<8 x i16> %s0_lo, <8 x i16> %s0_hi, <8 x i16> %s1_lo, <8 x i16> %s1_hi) {294; CHECK-SD-LABEL: signOf_neon_scmp:295; CHECK-SD: // %bb.0: // %entry296; CHECK-SD-NEXT: cmgt v4.8h, v1.8h, v3.8h297; CHECK-SD-NEXT: cmgt v1.8h, v3.8h, v1.8h298; CHECK-SD-NEXT: cmgt v3.8h, v0.8h, v2.8h299; CHECK-SD-NEXT: cmgt v0.8h, v2.8h, v0.8h300; CHECK-SD-NEXT: sub v1.8h, v1.8h, v4.8h301; CHECK-SD-NEXT: sub v0.8h, v0.8h, v3.8h302; CHECK-SD-NEXT: uzp1 v0.16b, v0.16b, v1.16b303; CHECK-SD-NEXT: ret304;305; CHECK-GI-LABEL: signOf_neon_scmp:306; CHECK-GI: // %bb.0: // %entry307; CHECK-GI-NEXT: cmgt v4.8h, v0.8h, v2.8h308; CHECK-GI-NEXT: cmgt v5.8h, v1.8h, v3.8h309; CHECK-GI-NEXT: cmgt v0.8h, v2.8h, v0.8h310; CHECK-GI-NEXT: cmgt v1.8h, v3.8h, v1.8h311; CHECK-GI-NEXT: uzp1 v0.16b, v0.16b, v1.16b312; CHECK-GI-NEXT: uzp1 v1.16b, v4.16b, v5.16b313; CHECK-GI-NEXT: sub v0.16b, v0.16b, v1.16b314; CHECK-GI-NEXT: ret315entry:316 %0 = shufflevector <8 x i16> %s0_lo, <8 x i16> %s0_hi, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>317 %1 = shufflevector <8 x i16> %s1_lo, <8 x i16> %s1_hi, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>318 %or.i = tail call <16 x i8> @llvm.scmp.v16i8.v16i16(<16 x i16> %0, <16 x i16> %1)319 ret <16 x i8> %or.i320}321