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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-none-elf %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD3; RUN: llc -mtriple=aarch64-none-elf -global-isel %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-GI4 5define i32 @xori64i32(i64 %a) {6; CHECK-LABEL: xori64i32:7; CHECK: // %bb.0:8; CHECK-NEXT: asr x8, x0, #639; CHECK-NEXT: eor w0, w8, #0x7fffffff10; CHECK-NEXT: ret11 %shr4 = ashr i64 %a, 6312 %conv5 = trunc i64 %shr4 to i3213 %xor = xor i32 %conv5, 214748364714 ret i32 %xor15}16 17define i64 @selecti64i64(i64 %a) {18; CHECK-SD-LABEL: selecti64i64:19; CHECK-SD: // %bb.0:20; CHECK-SD-NEXT: asr x8, x0, #6321; CHECK-SD-NEXT: eor x0, x8, #0x7fffffff22; CHECK-SD-NEXT: ret23;24; CHECK-GI-LABEL: selecti64i64:25; CHECK-GI: // %bb.0:26; CHECK-GI-NEXT: mov x8, #-2147483648 // =0xffffffff8000000027; CHECK-GI-NEXT: mov w9, #2147483647 // =0x7fffffff28; CHECK-GI-NEXT: cmp x0, #029; CHECK-GI-NEXT: csel x0, x9, x8, pl30; CHECK-GI-NEXT: ret31 %c = icmp sgt i64 %a, -132 %s = select i1 %c, i64 2147483647, i64 -214748364833 ret i64 %s34}35 36define i32 @selecti64i32(i64 %a) {37; CHECK-SD-LABEL: selecti64i32:38; CHECK-SD: // %bb.0:39; CHECK-SD-NEXT: asr x8, x0, #6340; CHECK-SD-NEXT: eor w0, w8, #0x7fffffff41; CHECK-SD-NEXT: ret42;43; CHECK-GI-LABEL: selecti64i32:44; CHECK-GI: // %bb.0:45; CHECK-GI-NEXT: cmp x0, #046; CHECK-GI-NEXT: mov w9, #-2147483648 // =0x8000000047; CHECK-GI-NEXT: cset w8, pl48; CHECK-GI-NEXT: sbfx w8, w8, #0, #149; CHECK-GI-NEXT: add w0, w8, w950; CHECK-GI-NEXT: ret51 %c = icmp sgt i64 %a, -152 %s = select i1 %c, i32 2147483647, i32 -214748364853 ret i32 %s54}55 56define i64 @selecti32i64(i32 %a) {57; CHECK-SD-LABEL: selecti32i64:58; CHECK-SD: // %bb.0:59; CHECK-SD-NEXT: // kill: def $w0 killed $w0 def $x060; CHECK-SD-NEXT: sbfx x8, x0, #31, #161; CHECK-SD-NEXT: eor x0, x8, #0x7fffffff62; CHECK-SD-NEXT: ret63;64; CHECK-GI-LABEL: selecti32i64:65; CHECK-GI: // %bb.0:66; CHECK-GI-NEXT: mov x8, #-2147483648 // =0xffffffff8000000067; CHECK-GI-NEXT: mov w9, #2147483647 // =0x7fffffff68; CHECK-GI-NEXT: cmp w0, #069; CHECK-GI-NEXT: csel x0, x9, x8, pl70; CHECK-GI-NEXT: ret71 %c = icmp sgt i32 %a, -172 %s = select i1 %c, i64 2147483647, i64 -214748364873 ret i64 %s74}75 76 77 78define i8 @xori32i8(i32 %a) {79; CHECK-LABEL: xori32i8:80; CHECK: // %bb.0:81; CHECK-NEXT: mov w8, #84 // =0x5482; CHECK-NEXT: eor w0, w8, w0, asr #3183; CHECK-NEXT: ret84 %shr4 = ashr i32 %a, 3185 %conv5 = trunc i32 %shr4 to i886 %xor = xor i8 %conv5, 8487 ret i8 %xor88}89 90define i32 @selecti32i32(i32 %a) {91; CHECK-SD-LABEL: selecti32i32:92; CHECK-SD: // %bb.0:93; CHECK-SD-NEXT: mov w8, #84 // =0x5494; CHECK-SD-NEXT: eor w0, w8, w0, asr #3195; CHECK-SD-NEXT: ret96;97; CHECK-GI-LABEL: selecti32i32:98; CHECK-GI: // %bb.0:99; CHECK-GI-NEXT: mov w8, #-85 // =0xffffffab100; CHECK-GI-NEXT: mov w9, #84 // =0x54101; CHECK-GI-NEXT: cmp w0, #0102; CHECK-GI-NEXT: csel w0, w9, w8, pl103; CHECK-GI-NEXT: ret104 %c = icmp sgt i32 %a, -1105 %s = select i1 %c, i32 84, i32 -85106 ret i32 %s107}108 109define i8 @selecti32i8(i32 %a) {110; CHECK-SD-LABEL: selecti32i8:111; CHECK-SD: // %bb.0:112; CHECK-SD-NEXT: mov w8, #84 // =0x54113; CHECK-SD-NEXT: eor w0, w8, w0, asr #31114; CHECK-SD-NEXT: ret115;116; CHECK-GI-LABEL: selecti32i8:117; CHECK-GI: // %bb.0:118; CHECK-GI-NEXT: mov w8, #84 // =0x54119; CHECK-GI-NEXT: mov w9, #-85 // =0xffffffab120; CHECK-GI-NEXT: cmp w0, #0121; CHECK-GI-NEXT: csel w0, w8, w9, pl122; CHECK-GI-NEXT: ret123 %c = icmp sgt i32 %a, -1124 %s = select i1 %c, i8 84, i8 -85125 ret i8 %s126}127 128define i32 @selecti8i32(i8 %a) {129; CHECK-SD-LABEL: selecti8i32:130; CHECK-SD: // %bb.0:131; CHECK-SD-NEXT: sxtb w8, w0132; CHECK-SD-NEXT: mov w9, #84 // =0x54133; CHECK-SD-NEXT: eor w0, w9, w8, asr #7134; CHECK-SD-NEXT: ret135;136; CHECK-GI-LABEL: selecti8i32:137; CHECK-GI: // %bb.0:138; CHECK-GI-NEXT: sxtb w8, w0139; CHECK-GI-NEXT: mov w9, #-85 // =0xffffffab140; CHECK-GI-NEXT: mov w10, #84 // =0x54141; CHECK-GI-NEXT: cmp w8, #0142; CHECK-GI-NEXT: csel w0, w10, w9, pl143; CHECK-GI-NEXT: ret144 %c = icmp sgt i8 %a, -1145 %s = select i1 %c, i32 84, i32 -85146 ret i32 %s147}148 149define i32 @icmpasreq(i32 %input, i32 %a, i32 %b) {150; CHECK-SD-LABEL: icmpasreq:151; CHECK-SD: // %bb.0:152; CHECK-SD-NEXT: cmp w0, #0153; CHECK-SD-NEXT: csel w0, w1, w2, mi154; CHECK-SD-NEXT: ret155;156; CHECK-GI-LABEL: icmpasreq:157; CHECK-GI: // %bb.0:158; CHECK-GI-NEXT: mov w8, #-1 // =0xffffffff159; CHECK-GI-NEXT: cmp w8, w0, asr #31160; CHECK-GI-NEXT: csel w0, w1, w2, eq161; CHECK-GI-NEXT: ret162 %sh = ashr i32 %input, 31163 %c = icmp eq i32 %sh, -1164 %s = select i1 %c, i32 %a, i32 %b165 ret i32 %s166}167 168define i32 @icmpasrne(i32 %input, i32 %a, i32 %b) {169; CHECK-SD-LABEL: icmpasrne:170; CHECK-SD: // %bb.0:171; CHECK-SD-NEXT: cmn w0, #1172; CHECK-SD-NEXT: csel w0, w1, w2, gt173; CHECK-SD-NEXT: ret174;175; CHECK-GI-LABEL: icmpasrne:176; CHECK-GI: // %bb.0:177; CHECK-GI-NEXT: mov w8, #-1 // =0xffffffff178; CHECK-GI-NEXT: cmp w8, w0, asr #31179; CHECK-GI-NEXT: csel w0, w1, w2, ne180; CHECK-GI-NEXT: ret181 %sh = ashr i32 %input, 31182 %c = icmp ne i32 %sh, -1183 %s = select i1 %c, i32 %a, i32 %b184 ret i32 %s185}186 187define i32 @selecti32i32_0(i32 %a) {188; CHECK-SD-LABEL: selecti32i32_0:189; CHECK-SD: // %bb.0:190; CHECK-SD-NEXT: asr w0, w0, #31191; CHECK-SD-NEXT: ret192;193; CHECK-GI-LABEL: selecti32i32_0:194; CHECK-GI: // %bb.0:195; CHECK-GI-NEXT: cmp w0, #0196; CHECK-GI-NEXT: cset w8, mi197; CHECK-GI-NEXT: sbfx w0, w8, #0, #1198; CHECK-GI-NEXT: ret199 %c = icmp sgt i32 %a, -1200 %s = select i1 %c, i32 0, i32 -1201 ret i32 %s202}203 204define i32 @selecti32i32_m1(i32 %a) {205; CHECK-SD-LABEL: selecti32i32_m1:206; CHECK-SD: // %bb.0:207; CHECK-SD-NEXT: mvn w8, w0208; CHECK-SD-NEXT: asr w0, w8, #31209; CHECK-SD-NEXT: ret210;211; CHECK-GI-LABEL: selecti32i32_m1:212; CHECK-GI: // %bb.0:213; CHECK-GI-NEXT: cmp w0, #0214; CHECK-GI-NEXT: cset w8, pl215; CHECK-GI-NEXT: sbfx w0, w8, #0, #1216; CHECK-GI-NEXT: ret217 %c = icmp sgt i32 %a, -1218 %s = select i1 %c, i32 -1, i32 0219 ret i32 %s220}221 222define i32 @selecti32i32_1(i32 %a) {223; CHECK-SD-LABEL: selecti32i32_1:224; CHECK-SD: // %bb.0:225; CHECK-SD-NEXT: asr w8, w0, #31226; CHECK-SD-NEXT: eor w0, w8, #0x1227; CHECK-SD-NEXT: ret228;229; CHECK-GI-LABEL: selecti32i32_1:230; CHECK-GI: // %bb.0:231; CHECK-GI-NEXT: mov w8, #-2 // =0xfffffffe232; CHECK-GI-NEXT: cmp w0, #0233; CHECK-GI-NEXT: csinc w0, w8, wzr, mi234; CHECK-GI-NEXT: ret235 %c = icmp sgt i32 %a, -1236 %s = select i1 %c, i32 1, i32 -2237 ret i32 %s238}239 240define i32 @selecti32i32_sge(i32 %a) {241; CHECK-SD-LABEL: selecti32i32_sge:242; CHECK-SD: // %bb.0:243; CHECK-SD-NEXT: asr w8, w0, #31244; CHECK-SD-NEXT: eor w0, w8, #0xc245; CHECK-SD-NEXT: ret246;247; CHECK-GI-LABEL: selecti32i32_sge:248; CHECK-GI: // %bb.0:249; CHECK-GI-NEXT: mov w8, #-13 // =0xfffffff3250; CHECK-GI-NEXT: mov w9, #12 // =0xc251; CHECK-GI-NEXT: cmp w0, #0252; CHECK-GI-NEXT: csel w0, w9, w8, pl253; CHECK-GI-NEXT: ret254 %c = icmp sge i32 %a, 0255 %s = select i1 %c, i32 12, i32 -13256 ret i32 %s257}258 259define i32 @selecti32i32_slt(i32 %a) {260; CHECK-SD-LABEL: selecti32i32_slt:261; CHECK-SD: // %bb.0:262; CHECK-SD-NEXT: asr w8, w0, #31263; CHECK-SD-NEXT: eor w0, w8, #0xc264; CHECK-SD-NEXT: ret265;266; CHECK-GI-LABEL: selecti32i32_slt:267; CHECK-GI: // %bb.0:268; CHECK-GI-NEXT: mov w8, #12 // =0xc269; CHECK-GI-NEXT: mov w9, #-13 // =0xfffffff3270; CHECK-GI-NEXT: cmp w0, #0271; CHECK-GI-NEXT: csel w0, w9, w8, mi272; CHECK-GI-NEXT: ret273 %c = icmp slt i32 %a, 0274 %s = select i1 %c, i32 -13, i32 12275 ret i32 %s276}277 278define i32 @selecti32i32_sle(i32 %a) {279; CHECK-SD-LABEL: selecti32i32_sle:280; CHECK-SD: // %bb.0:281; CHECK-SD-NEXT: asr w8, w0, #31282; CHECK-SD-NEXT: eor w0, w8, #0xc283; CHECK-SD-NEXT: ret284;285; CHECK-GI-LABEL: selecti32i32_sle:286; CHECK-GI: // %bb.0:287; CHECK-GI-NEXT: mov w8, #12 // =0xc288; CHECK-GI-NEXT: mov w9, #-13 // =0xfffffff3289; CHECK-GI-NEXT: cmp w0, #0290; CHECK-GI-NEXT: csel w0, w9, w8, mi291; CHECK-GI-NEXT: ret292 %c = icmp sle i32 %a, -1293 %s = select i1 %c, i32 -13, i32 12294 ret i32 %s295}296 297define i32 @selecti32i32_sgt(i32 %a) {298; CHECK-SD-LABEL: selecti32i32_sgt:299; CHECK-SD: // %bb.0:300; CHECK-SD-NEXT: asr w8, w0, #31301; CHECK-SD-NEXT: eor w0, w8, #0xc302; CHECK-SD-NEXT: ret303;304; CHECK-GI-LABEL: selecti32i32_sgt:305; CHECK-GI: // %bb.0:306; CHECK-GI-NEXT: mov w8, #12 // =0xc307; CHECK-GI-NEXT: mov w9, #-13 // =0xfffffff3308; CHECK-GI-NEXT: cmp w0, #0309; CHECK-GI-NEXT: csel w0, w9, w8, mi310; CHECK-GI-NEXT: ret311 %c = icmp sle i32 %a, -1312 %s = select i1 %c, i32 -13, i32 12313 ret i32 %s314}315 316define i32 @oneusecmp(i32 %a, i32 %b, i32 %d) {317; CHECK-SD-LABEL: oneusecmp:318; CHECK-SD: // %bb.0:319; CHECK-SD-NEXT: asr w8, w0, #31320; CHECK-SD-NEXT: cmp w0, #0321; CHECK-SD-NEXT: csel w9, w2, w1, mi322; CHECK-SD-NEXT: eor w8, w8, #0x7f323; CHECK-SD-NEXT: add w0, w8, w9324; CHECK-SD-NEXT: ret325;326; CHECK-GI-LABEL: oneusecmp:327; CHECK-GI: // %bb.0:328; CHECK-GI-NEXT: mov w8, #127 // =0x7f329; CHECK-GI-NEXT: mov w9, #-128 // =0xffffff80330; CHECK-GI-NEXT: cmp w0, #0331; CHECK-GI-NEXT: csel w8, w9, w8, mi332; CHECK-GI-NEXT: csel w9, w2, w1, mi333; CHECK-GI-NEXT: add w0, w8, w9334; CHECK-GI-NEXT: ret335 %c = icmp sle i32 %a, -1336 %s = select i1 %c, i32 -128, i32 127337 %s2 = select i1 %c, i32 %d, i32 %b338 %x = add i32 %s, %s2339 ret i32 %x340}341