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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=aarch64 | FileCheck %s --check-prefixes=CHECK,CHECK-SD3; RUN: llc < %s -mtriple=aarch64 -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI4 5define i1 @and(i32 %x, i32 %y, i32 %z, i32 %w) {6; CHECK-SD-LABEL: and:7; CHECK-SD: // %bb.0:8; CHECK-SD-NEXT: cmp w0, w19; CHECK-SD-NEXT: ccmp w2, w3, #4, eq10; CHECK-SD-NEXT: cset w0, gt11; CHECK-SD-NEXT: ret12;13; CHECK-GI-LABEL: and:14; CHECK-GI: // %bb.0:15; CHECK-GI-NEXT: cmp w0, w116; CHECK-GI-NEXT: cset w8, eq17; CHECK-GI-NEXT: cmp w2, w318; CHECK-GI-NEXT: cset w9, gt19; CHECK-GI-NEXT: and w0, w8, w920; CHECK-GI-NEXT: ret21 %a = icmp eq i32 %x, %y22 %b = icmp sgt i32 %z, %w23 %s = select i1 %a, i1 %b, i1 false24 ret i1 %s25}26 27define i1 @or(i32 %x, i32 %y, i32 %z, i32 %w) {28; CHECK-SD-LABEL: or:29; CHECK-SD: // %bb.0:30; CHECK-SD-NEXT: cmp w0, w131; CHECK-SD-NEXT: ccmp w2, w3, #0, ne32; CHECK-SD-NEXT: cset w0, gt33; CHECK-SD-NEXT: ret34;35; CHECK-GI-LABEL: or:36; CHECK-GI: // %bb.0:37; CHECK-GI-NEXT: cmp w0, w138; CHECK-GI-NEXT: cset w8, eq39; CHECK-GI-NEXT: cmp w2, w340; CHECK-GI-NEXT: cset w9, gt41; CHECK-GI-NEXT: orr w8, w8, w942; CHECK-GI-NEXT: and w0, w8, #0x143; CHECK-GI-NEXT: ret44 %a = icmp eq i32 %x, %y45 %b = icmp sgt i32 %z, %w46 %s = select i1 %a, i1 true, i1 %b47 ret i1 %s48}49 50define i1 @and_not(i32 %x, i32 %y, i32 %z, i32 %w) {51; CHECK-SD-LABEL: and_not:52; CHECK-SD: // %bb.0:53; CHECK-SD-NEXT: cmp w0, w154; CHECK-SD-NEXT: ccmp w2, w3, #4, ne55; CHECK-SD-NEXT: cset w0, gt56; CHECK-SD-NEXT: ret57;58; CHECK-GI-LABEL: and_not:59; CHECK-GI: // %bb.0:60; CHECK-GI-NEXT: cmp w0, w161; CHECK-GI-NEXT: cset w8, ne62; CHECK-GI-NEXT: cmp w2, w363; CHECK-GI-NEXT: cset w9, gt64; CHECK-GI-NEXT: and w0, w8, w965; CHECK-GI-NEXT: ret66 %a = icmp eq i32 %x, %y67 %b = icmp sgt i32 %z, %w68 %s = select i1 %a, i1 false, i1 %b69 ret i1 %s70}71 72define i1 @or_not(i32 %x, i32 %y, i32 %z, i32 %w) {73; CHECK-SD-LABEL: or_not:74; CHECK-SD: // %bb.0:75; CHECK-SD-NEXT: cmp w0, w176; CHECK-SD-NEXT: ccmp w2, w3, #0, eq77; CHECK-SD-NEXT: cset w0, gt78; CHECK-SD-NEXT: ret79;80; CHECK-GI-LABEL: or_not:81; CHECK-GI: // %bb.0:82; CHECK-GI-NEXT: cmp w0, w183; CHECK-GI-NEXT: cset w8, ne84; CHECK-GI-NEXT: cmp w2, w385; CHECK-GI-NEXT: cset w9, gt86; CHECK-GI-NEXT: orr w8, w8, w987; CHECK-GI-NEXT: and w0, w8, #0x188; CHECK-GI-NEXT: ret89 %a = icmp eq i32 %x, %y90 %b = icmp sgt i32 %z, %w91 %s = select i1 %a, i1 %b, i1 true92 ret i1 %s93}94 95define <4 x i1> @and_vec(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z, <4 x i32> %w) {96; CHECK-SD-LABEL: and_vec:97; CHECK-SD: // %bb.0:98; CHECK-SD-NEXT: cmgt v2.4s, v2.4s, v3.4s99; CHECK-SD-NEXT: cmeq v0.4s, v0.4s, v1.4s100; CHECK-SD-NEXT: and v0.16b, v0.16b, v2.16b101; CHECK-SD-NEXT: xtn v0.4h, v0.4s102; CHECK-SD-NEXT: ret103;104; CHECK-GI-LABEL: and_vec:105; CHECK-GI: // %bb.0:106; CHECK-GI-NEXT: cmeq v0.4s, v0.4s, v1.4s107; CHECK-GI-NEXT: cmgt v1.4s, v2.4s, v3.4s108; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b109; CHECK-GI-NEXT: xtn v0.4h, v0.4s110; CHECK-GI-NEXT: ret111 %a = icmp eq <4 x i32> %x, %y112 %b = icmp sgt <4 x i32> %z, %w113 %s = select <4 x i1> %a, <4 x i1> %b, <4 x i1> zeroinitializer114 ret <4 x i1> %s115}116 117define <4 x i1> @or_vec(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z, <4 x i32> %w) {118; CHECK-SD-LABEL: or_vec:119; CHECK-SD: // %bb.0:120; CHECK-SD-NEXT: cmgt v2.4s, v2.4s, v3.4s121; CHECK-SD-NEXT: cmeq v0.4s, v0.4s, v1.4s122; CHECK-SD-NEXT: orr v0.16b, v0.16b, v2.16b123; CHECK-SD-NEXT: xtn v0.4h, v0.4s124; CHECK-SD-NEXT: ret125;126; CHECK-GI-LABEL: or_vec:127; CHECK-GI: // %bb.0:128; CHECK-GI-NEXT: cmeq v0.4s, v0.4s, v1.4s129; CHECK-GI-NEXT: cmgt v1.4s, v2.4s, v3.4s130; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b131; CHECK-GI-NEXT: xtn v0.4h, v0.4s132; CHECK-GI-NEXT: ret133 %a = icmp eq <4 x i32> %x, %y134 %b = icmp sgt <4 x i32> %z, %w135 %s = select <4 x i1> %a, <4 x i1> <i1 1, i1 1, i1 1, i1 1>, <4 x i1> %b136 ret <4 x i1> %s137}138 139define <4 x i1> @and_not_vec(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z, <4 x i32> %w) {140; CHECK-SD-LABEL: and_not_vec:141; CHECK-SD: // %bb.0:142; CHECK-SD-NEXT: cmgt v2.4s, v2.4s, v3.4s143; CHECK-SD-NEXT: cmeq v0.4s, v0.4s, v1.4s144; CHECK-SD-NEXT: bic v0.16b, v2.16b, v0.16b145; CHECK-SD-NEXT: xtn v0.4h, v0.4s146; CHECK-SD-NEXT: ret147;148; CHECK-GI-LABEL: and_not_vec:149; CHECK-GI: // %bb.0:150; CHECK-GI-NEXT: cmeq v0.4s, v0.4s, v1.4s151; CHECK-GI-NEXT: cmgt v1.4s, v2.4s, v3.4s152; CHECK-GI-NEXT: bic v0.16b, v1.16b, v0.16b153; CHECK-GI-NEXT: xtn v0.4h, v0.4s154; CHECK-GI-NEXT: ret155 %a = icmp eq <4 x i32> %x, %y156 %b = icmp sgt <4 x i32> %z, %w157 %s = select <4 x i1> %a, <4 x i1> zeroinitializer, <4 x i1> %b158 ret <4 x i1> %s159}160 161define <4 x i1> @or_not_vec(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z, <4 x i32> %w) {162; CHECK-SD-LABEL: or_not_vec:163; CHECK-SD: // %bb.0:164; CHECK-SD-NEXT: cmgt v2.4s, v2.4s, v3.4s165; CHECK-SD-NEXT: cmeq v0.4s, v0.4s, v1.4s166; CHECK-SD-NEXT: orn v0.16b, v2.16b, v0.16b167; CHECK-SD-NEXT: xtn v0.4h, v0.4s168; CHECK-SD-NEXT: ret169;170; CHECK-GI-LABEL: or_not_vec:171; CHECK-GI: // %bb.0:172; CHECK-GI-NEXT: cmeq v0.4s, v0.4s, v1.4s173; CHECK-GI-NEXT: cmgt v1.4s, v2.4s, v3.4s174; CHECK-GI-NEXT: orn v0.16b, v1.16b, v0.16b175; CHECK-GI-NEXT: xtn v0.4h, v0.4s176; CHECK-GI-NEXT: ret177 %a = icmp eq <4 x i32> %x, %y178 %b = icmp sgt <4 x i32> %z, %w179 %s = select <4 x i1> %a, <4 x i1> %b, <4 x i1> <i1 1, i1 1, i1 1, i1 1>180 ret <4 x i1> %s181}182 183define <4 x i1> @and_vec_undef(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z, <4 x i32> %w) {184; CHECK-SD-LABEL: and_vec_undef:185; CHECK-SD: // %bb.0:186; CHECK-SD-NEXT: cmgt v2.4s, v2.4s, v3.4s187; CHECK-SD-NEXT: cmeq v0.4s, v0.4s, v1.4s188; CHECK-SD-NEXT: and v0.16b, v0.16b, v2.16b189; CHECK-SD-NEXT: xtn v0.4h, v0.4s190; CHECK-SD-NEXT: ret191;192; CHECK-GI-LABEL: and_vec_undef:193; CHECK-GI: // %bb.0:194; CHECK-GI-NEXT: cmeq v0.4s, v0.4s, v1.4s195; CHECK-GI-NEXT: cmgt v1.4s, v2.4s, v3.4s196; CHECK-GI-NEXT: and v0.16b, v0.16b, v1.16b197; CHECK-GI-NEXT: xtn v0.4h, v0.4s198; CHECK-GI-NEXT: ret199 %a = icmp eq <4 x i32> %x, %y200 %b = icmp sgt <4 x i32> %z, %w201 %s = select <4 x i1> %a, <4 x i1> %b, <4 x i1> <i1 0, i1 undef, i1 0, i1 undef>202 ret <4 x i1> %s203}204 205define <4 x i1> @or_vec_undef(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z, <4 x i32> %w) {206; CHECK-SD-LABEL: or_vec_undef:207; CHECK-SD: // %bb.0:208; CHECK-SD-NEXT: cmgt v2.4s, v2.4s, v3.4s209; CHECK-SD-NEXT: cmeq v0.4s, v0.4s, v1.4s210; CHECK-SD-NEXT: orr v0.16b, v0.16b, v2.16b211; CHECK-SD-NEXT: xtn v0.4h, v0.4s212; CHECK-SD-NEXT: ret213;214; CHECK-GI-LABEL: or_vec_undef:215; CHECK-GI: // %bb.0:216; CHECK-GI-NEXT: cmeq v0.4s, v0.4s, v1.4s217; CHECK-GI-NEXT: cmgt v1.4s, v2.4s, v3.4s218; CHECK-GI-NEXT: orr v0.16b, v0.16b, v1.16b219; CHECK-GI-NEXT: xtn v0.4h, v0.4s220; CHECK-GI-NEXT: ret221 %a = icmp eq <4 x i32> %x, %y222 %b = icmp sgt <4 x i32> %z, %w223 %s = select <4 x i1> %a, <4 x i1> <i1 undef, i1 1, i1 1, i1 undef>, <4 x i1> %b224 ret <4 x i1> %s225}226 227define <4 x i1> @and_not_vec_undef(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z, <4 x i32> %w) {228; CHECK-SD-LABEL: and_not_vec_undef:229; CHECK-SD: // %bb.0:230; CHECK-SD-NEXT: cmgt v2.4s, v2.4s, v3.4s231; CHECK-SD-NEXT: cmeq v0.4s, v0.4s, v1.4s232; CHECK-SD-NEXT: bic v0.16b, v2.16b, v0.16b233; CHECK-SD-NEXT: xtn v0.4h, v0.4s234; CHECK-SD-NEXT: ret235;236; CHECK-GI-LABEL: and_not_vec_undef:237; CHECK-GI: // %bb.0:238; CHECK-GI-NEXT: cmeq v0.4s, v0.4s, v1.4s239; CHECK-GI-NEXT: cmgt v1.4s, v2.4s, v3.4s240; CHECK-GI-NEXT: bic v0.16b, v1.16b, v0.16b241; CHECK-GI-NEXT: xtn v0.4h, v0.4s242; CHECK-GI-NEXT: ret243 %a = icmp eq <4 x i32> %x, %y244 %b = icmp sgt <4 x i32> %z, %w245 %s = select <4 x i1> %a, <4 x i1> <i1 0, i1 0, i1 undef, i1 0>, <4 x i1> %b246 ret <4 x i1> %s247}248 249define <4 x i1> @or_not_vec_undef(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z, <4 x i32> %w) {250; CHECK-SD-LABEL: or_not_vec_undef:251; CHECK-SD: // %bb.0:252; CHECK-SD-NEXT: cmgt v2.4s, v2.4s, v3.4s253; CHECK-SD-NEXT: cmeq v0.4s, v0.4s, v1.4s254; CHECK-SD-NEXT: orn v0.16b, v2.16b, v0.16b255; CHECK-SD-NEXT: xtn v0.4h, v0.4s256; CHECK-SD-NEXT: ret257;258; CHECK-GI-LABEL: or_not_vec_undef:259; CHECK-GI: // %bb.0:260; CHECK-GI-NEXT: cmeq v0.4s, v0.4s, v1.4s261; CHECK-GI-NEXT: cmgt v1.4s, v2.4s, v3.4s262; CHECK-GI-NEXT: orn v0.16b, v1.16b, v0.16b263; CHECK-GI-NEXT: xtn v0.4h, v0.4s264; CHECK-GI-NEXT: ret265 %a = icmp eq <4 x i32> %x, %y266 %b = icmp sgt <4 x i32> %z, %w267 %s = select <4 x i1> %a, <4 x i1> %b, <4 x i1> <i1 1, i1 undef, i1 1, i1 1>268 ret <4 x i1> %s269}270;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:271; CHECK: {{.*}}272