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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=aarch64 | FileCheck %s --check-prefixes=CHECK,CHECK-SD3; RUN: llc < %s -mtriple=aarch64 -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI4 5define i64 @select_ogt_float(float %a, float %b) {6; CHECK-SD-LABEL: select_ogt_float:7; CHECK-SD: // %bb.0: // %entry8; CHECK-SD-NEXT: fcmp s0, s19; CHECK-SD-NEXT: mov w8, #4 // =0x410; CHECK-SD-NEXT: csel x0, x8, xzr, gt11; CHECK-SD-NEXT: ret12;13; CHECK-GI-LABEL: select_ogt_float:14; CHECK-GI: // %bb.0: // %entry15; CHECK-GI-NEXT: fcmp s0, s116; CHECK-GI-NEXT: cset w8, gt17; CHECK-GI-NEXT: lsl x0, x8, #218; CHECK-GI-NEXT: ret19entry:20 %cc = fcmp ogt float %a, %b21 %sel = select i1 %cc, i64 4, i64 022 ret i64 %sel23}24 25define i64 @select_ule_float_inverse(float %a, float %b) {26; CHECK-SD-LABEL: select_ule_float_inverse:27; CHECK-SD: // %bb.0: // %entry28; CHECK-SD-NEXT: fcmp s0, s129; CHECK-SD-NEXT: mov w8, #4 // =0x430; CHECK-SD-NEXT: csel x0, xzr, x8, le31; CHECK-SD-NEXT: ret32;33; CHECK-GI-LABEL: select_ule_float_inverse:34; CHECK-GI: // %bb.0: // %entry35; CHECK-GI-NEXT: fcmp s0, s136; CHECK-GI-NEXT: cset w8, gt37; CHECK-GI-NEXT: lsl x0, x8, #238; CHECK-GI-NEXT: ret39entry:40 %cc = fcmp ule float %a, %b41 %sel = select i1 %cc, i64 0, i64 442 ret i64 %sel43}44 45define i64 @select_eq_i32(i32 %a, i32 %b) {46; CHECK-SD-LABEL: select_eq_i32:47; CHECK-SD: // %bb.0: // %entry48; CHECK-SD-NEXT: mov w8, #4 // =0x449; CHECK-SD-NEXT: cmp w0, w150; CHECK-SD-NEXT: csel x0, x8, xzr, eq51; CHECK-SD-NEXT: ret52;53; CHECK-GI-LABEL: select_eq_i32:54; CHECK-GI: // %bb.0: // %entry55; CHECK-GI-NEXT: cmp w0, w156; CHECK-GI-NEXT: cset w8, eq57; CHECK-GI-NEXT: lsl x0, x8, #258; CHECK-GI-NEXT: ret59entry:60 %cc = icmp eq i32 %a, %b61 %sel = select i1 %cc, i64 4, i64 062 ret i64 %sel63}64 65define i64 @select_ne_i32_inverse(i32 %a, i32 %b) {66; CHECK-SD-LABEL: select_ne_i32_inverse:67; CHECK-SD: // %bb.0: // %entry68; CHECK-SD-NEXT: mov w8, #4 // =0x469; CHECK-SD-NEXT: cmp w0, w170; CHECK-SD-NEXT: csel x0, xzr, x8, ne71; CHECK-SD-NEXT: ret72;73; CHECK-GI-LABEL: select_ne_i32_inverse:74; CHECK-GI: // %bb.0: // %entry75; CHECK-GI-NEXT: cmp w0, w176; CHECK-GI-NEXT: cset w8, eq77; CHECK-GI-NEXT: lsl x0, x8, #278; CHECK-GI-NEXT: ret79entry:80 %cc = icmp ne i32 %a, %b81 %sel = select i1 %cc, i64 0, i64 482 ret i64 %sel83}84 85define <2 x double> @select_olt_load_cmp(<2 x double> %a, ptr %src) {86; CHECK-SD-LABEL: select_olt_load_cmp:87; CHECK-SD: // %bb.0: // %entry88; CHECK-SD-NEXT: ldr d1, [x0]89; CHECK-SD-NEXT: fcmgt v1.2s, v1.2s, #0.090; CHECK-SD-NEXT: sshll v1.2d, v1.2s, #091; CHECK-SD-NEXT: and v0.16b, v1.16b, v0.16b92; CHECK-SD-NEXT: ret93;94; CHECK-GI-LABEL: select_olt_load_cmp:95; CHECK-GI: // %bb.0: // %entry96; CHECK-GI-NEXT: ldr d1, [x0]97; CHECK-GI-NEXT: movi v2.2d, #000000000000000098; CHECK-GI-NEXT: fcmgt v1.2s, v1.2s, #0.099; CHECK-GI-NEXT: ushll v1.2d, v1.2s, #0100; CHECK-GI-NEXT: shl v1.2d, v1.2d, #63101; CHECK-GI-NEXT: cmlt v1.2d, v1.2d, #0102; CHECK-GI-NEXT: bif v0.16b, v2.16b, v1.16b103; CHECK-GI-NEXT: ret104entry:105 %l = load <2 x float>, ptr %src, align 4106 %cmp = fcmp olt <2 x float> zeroinitializer, %l107 %sel = select <2 x i1> %cmp, <2 x double> %a, <2 x double> zeroinitializer108 ret <2 x double> %sel109}110 111define <4 x i32> @select_icmp_sgt(<4 x i32> %a, <4 x i8> %b) {112; CHECK-SD-LABEL: select_icmp_sgt:113; CHECK-SD: // %bb.0: // %entry114; CHECK-SD-NEXT: shl v1.4h, v1.4h, #8115; CHECK-SD-NEXT: sshr v1.4h, v1.4h, #8116; CHECK-SD-NEXT: cmgt v1.4h, v1.4h, #0117; CHECK-SD-NEXT: sshll v1.4s, v1.4h, #0118; CHECK-SD-NEXT: bic v0.16b, v0.16b, v1.16b119; CHECK-SD-NEXT: ret120;121; CHECK-GI-LABEL: select_icmp_sgt:122; CHECK-GI: // %bb.0: // %entry123; CHECK-GI-NEXT: mov w8, #0 // =0x0124; CHECK-GI-NEXT: uzp1 v1.8b, v1.8b, v0.8b125; CHECK-GI-NEXT: fmov s2, w8126; CHECK-GI-NEXT: mov v2.b[1], w8127; CHECK-GI-NEXT: mov v2.b[2], w8128; CHECK-GI-NEXT: mov v2.b[3], w8129; CHECK-GI-NEXT: cmgt v1.8b, v1.8b, v2.8b130; CHECK-GI-NEXT: umov w8, v1.b[0]131; CHECK-GI-NEXT: umov w9, v1.b[1]132; CHECK-GI-NEXT: fmov s2, w8133; CHECK-GI-NEXT: umov w8, v1.b[2]134; CHECK-GI-NEXT: mov v2.s[1], w9135; CHECK-GI-NEXT: umov w9, v1.b[3]136; CHECK-GI-NEXT: mov v2.s[2], w8137; CHECK-GI-NEXT: mov v2.s[3], w9138; CHECK-GI-NEXT: shl v1.4s, v2.4s, #31139; CHECK-GI-NEXT: cmlt v1.4s, v1.4s, #0140; CHECK-GI-NEXT: bic v0.16b, v0.16b, v1.16b141; CHECK-GI-NEXT: ret142entry:143 %cmp = icmp sgt <4 x i8> %b, zeroinitializer144 %sel = select <4 x i1> %cmp, <4 x i32> zeroinitializer, <4 x i32> %a145 ret <4 x i32> %sel146}147;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:148; CHECK: {{.*}}149