975 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=aarch64 | FileCheck %s --check-prefixes=CHECK,CHECK-SD3; RUN: llc < %s -mtriple=aarch64 -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI4 5; Select of constants: control flow / conditional moves can always be replaced by logic+math (but may not be worth it?).6; Test the zeroext/signext variants of each pattern to see if that makes a difference.7 8; select Cond, 0, 1 --> zext (!Cond)9 10define i32 @select_0_or_1(i1 %cond) {11; CHECK-SD-LABEL: select_0_or_1:12; CHECK-SD: // %bb.0:13; CHECK-SD-NEXT: mov w8, #1 // =0x114; CHECK-SD-NEXT: bic w0, w8, w015; CHECK-SD-NEXT: ret16;17; CHECK-GI-LABEL: select_0_or_1:18; CHECK-GI: // %bb.0:19; CHECK-GI-NEXT: eor w8, w0, #0x120; CHECK-GI-NEXT: and w0, w8, #0x121; CHECK-GI-NEXT: ret22 %sel = select i1 %cond, i32 0, i32 123 ret i32 %sel24}25 26define i32 @select_0_or_1_zeroext(i1 zeroext %cond) {27; CHECK-LABEL: select_0_or_1_zeroext:28; CHECK: // %bb.0:29; CHECK-NEXT: eor w0, w0, #0x130; CHECK-NEXT: ret31 %sel = select i1 %cond, i32 0, i32 132 ret i32 %sel33}34 35define i32 @select_0_or_1_signext(i1 signext %cond) {36; CHECK-SD-LABEL: select_0_or_1_signext:37; CHECK-SD: // %bb.0:38; CHECK-SD-NEXT: mov w8, #1 // =0x139; CHECK-SD-NEXT: bic w0, w8, w040; CHECK-SD-NEXT: ret41;42; CHECK-GI-LABEL: select_0_or_1_signext:43; CHECK-GI: // %bb.0:44; CHECK-GI-NEXT: eor w8, w0, #0x145; CHECK-GI-NEXT: and w0, w8, #0x146; CHECK-GI-NEXT: ret47 %sel = select i1 %cond, i32 0, i32 148 ret i32 %sel49}50 51; select Cond, 1, 0 --> zext (Cond)52 53define i32 @select_1_or_0(i1 %cond) {54; CHECK-LABEL: select_1_or_0:55; CHECK: // %bb.0:56; CHECK-NEXT: and w0, w0, #0x157; CHECK-NEXT: ret58 %sel = select i1 %cond, i32 1, i32 059 ret i32 %sel60}61 62define i32 @select_1_or_0_zeroext(i1 zeroext %cond) {63; CHECK-LABEL: select_1_or_0_zeroext:64; CHECK: // %bb.0:65; CHECK-NEXT: ret66 %sel = select i1 %cond, i32 1, i32 067 ret i32 %sel68}69 70define i32 @select_1_or_0_signext(i1 signext %cond) {71; CHECK-LABEL: select_1_or_0_signext:72; CHECK: // %bb.0:73; CHECK-NEXT: and w0, w0, #0x174; CHECK-NEXT: ret75 %sel = select i1 %cond, i32 1, i32 076 ret i32 %sel77}78 79; select Cond, 0, -1 --> sext (!Cond)80 81define i32 @select_0_or_neg1(i1 %cond) {82; CHECK-SD-LABEL: select_0_or_neg1:83; CHECK-SD: // %bb.0:84; CHECK-SD-NEXT: and w8, w0, #0x185; CHECK-SD-NEXT: sub w0, w8, #186; CHECK-SD-NEXT: ret87;88; CHECK-GI-LABEL: select_0_or_neg1:89; CHECK-GI: // %bb.0:90; CHECK-GI-NEXT: eor w8, w0, #0x191; CHECK-GI-NEXT: sbfx w0, w8, #0, #192; CHECK-GI-NEXT: ret93 %sel = select i1 %cond, i32 0, i32 -194 ret i32 %sel95}96 97define i32 @select_0_or_neg1_zeroext(i1 zeroext %cond) {98; CHECK-SD-LABEL: select_0_or_neg1_zeroext:99; CHECK-SD: // %bb.0:100; CHECK-SD-NEXT: sub w0, w0, #1101; CHECK-SD-NEXT: ret102;103; CHECK-GI-LABEL: select_0_or_neg1_zeroext:104; CHECK-GI: // %bb.0:105; CHECK-GI-NEXT: eor w8, w0, #0x1106; CHECK-GI-NEXT: sbfx w0, w8, #0, #1107; CHECK-GI-NEXT: ret108 %sel = select i1 %cond, i32 0, i32 -1109 ret i32 %sel110}111 112define i32 @select_0_or_neg1_signext(i1 signext %cond) {113; CHECK-SD-LABEL: select_0_or_neg1_signext:114; CHECK-SD: // %bb.0:115; CHECK-SD-NEXT: mvn w0, w0116; CHECK-SD-NEXT: ret117;118; CHECK-GI-LABEL: select_0_or_neg1_signext:119; CHECK-GI: // %bb.0:120; CHECK-GI-NEXT: eor w8, w0, #0x1121; CHECK-GI-NEXT: sbfx w0, w8, #0, #1122; CHECK-GI-NEXT: ret123 %sel = select i1 %cond, i32 0, i32 -1124 ret i32 %sel125}126 127; select Cond, -1, 0 --> sext (Cond)128 129define i32 @select_neg1_or_0(i1 %cond) {130; CHECK-LABEL: select_neg1_or_0:131; CHECK: // %bb.0:132; CHECK-NEXT: sbfx w0, w0, #0, #1133; CHECK-NEXT: ret134 %sel = select i1 %cond, i32 -1, i32 0135 ret i32 %sel136}137 138define i32 @select_neg1_or_0_zeroext(i1 zeroext %cond) {139; CHECK-LABEL: select_neg1_or_0_zeroext:140; CHECK: // %bb.0:141; CHECK-NEXT: sbfx w0, w0, #0, #1142; CHECK-NEXT: ret143 %sel = select i1 %cond, i32 -1, i32 0144 ret i32 %sel145}146 147define i32 @select_neg1_or_0_signext(i1 signext %cond) {148; CHECK-LABEL: select_neg1_or_0_signext:149; CHECK: // %bb.0:150; CHECK-NEXT: ret151 %sel = select i1 %cond, i32 -1, i32 0152 ret i32 %sel153}154 155; select Cond, C+1, C --> add (zext Cond), C156 157define i32 @select_Cplus1_C(i1 %cond) {158; CHECK-SD-LABEL: select_Cplus1_C:159; CHECK-SD: // %bb.0:160; CHECK-SD-NEXT: mov w8, #41 // =0x29161; CHECK-SD-NEXT: tst w0, #0x1162; CHECK-SD-NEXT: cinc w0, w8, ne163; CHECK-SD-NEXT: ret164;165; CHECK-GI-LABEL: select_Cplus1_C:166; CHECK-GI: // %bb.0:167; CHECK-GI-NEXT: and w8, w0, #0x1168; CHECK-GI-NEXT: add w0, w8, #41169; CHECK-GI-NEXT: ret170 %sel = select i1 %cond, i32 42, i32 41171 ret i32 %sel172}173 174define i32 @select_Cplus1_C_zeroext(i1 zeroext %cond) {175; CHECK-SD-LABEL: select_Cplus1_C_zeroext:176; CHECK-SD: // %bb.0:177; CHECK-SD-NEXT: mov w8, #41 // =0x29178; CHECK-SD-NEXT: cmp w0, #0179; CHECK-SD-NEXT: cinc w0, w8, ne180; CHECK-SD-NEXT: ret181;182; CHECK-GI-LABEL: select_Cplus1_C_zeroext:183; CHECK-GI: // %bb.0:184; CHECK-GI-NEXT: add w0, w0, #41185; CHECK-GI-NEXT: ret186 %sel = select i1 %cond, i32 42, i32 41187 ret i32 %sel188}189 190define i32 @select_Cplus1_C_signext(i1 signext %cond) {191; CHECK-SD-LABEL: select_Cplus1_C_signext:192; CHECK-SD: // %bb.0:193; CHECK-SD-NEXT: mov w8, #41 // =0x29194; CHECK-SD-NEXT: tst w0, #0x1195; CHECK-SD-NEXT: cinc w0, w8, ne196; CHECK-SD-NEXT: ret197;198; CHECK-GI-LABEL: select_Cplus1_C_signext:199; CHECK-GI: // %bb.0:200; CHECK-GI-NEXT: and w8, w0, #0x1201; CHECK-GI-NEXT: add w0, w8, #41202; CHECK-GI-NEXT: ret203 %sel = select i1 %cond, i32 42, i32 41204 ret i32 %sel205}206 207; select Cond, C, C+1 --> add (sext Cond), C208 209define i32 @select_C_Cplus1(i1 %cond) {210; CHECK-SD-LABEL: select_C_Cplus1:211; CHECK-SD: // %bb.0:212; CHECK-SD-NEXT: mov w8, #41 // =0x29213; CHECK-SD-NEXT: tst w0, #0x1214; CHECK-SD-NEXT: cinc w0, w8, eq215; CHECK-SD-NEXT: ret216;217; CHECK-GI-LABEL: select_C_Cplus1:218; CHECK-GI: // %bb.0:219; CHECK-GI-NEXT: sbfx w8, w0, #0, #1220; CHECK-GI-NEXT: add w0, w8, #42221; CHECK-GI-NEXT: ret222 %sel = select i1 %cond, i32 41, i32 42223 ret i32 %sel224}225 226define i32 @select_C_Cplus1_zeroext(i1 zeroext %cond) {227; CHECK-SD-LABEL: select_C_Cplus1_zeroext:228; CHECK-SD: // %bb.0:229; CHECK-SD-NEXT: mov w8, #41 // =0x29230; CHECK-SD-NEXT: cmp w0, #0231; CHECK-SD-NEXT: cinc w0, w8, eq232; CHECK-SD-NEXT: ret233;234; CHECK-GI-LABEL: select_C_Cplus1_zeroext:235; CHECK-GI: // %bb.0:236; CHECK-GI-NEXT: sbfx w8, w0, #0, #1237; CHECK-GI-NEXT: add w0, w8, #42238; CHECK-GI-NEXT: ret239 %sel = select i1 %cond, i32 41, i32 42240 ret i32 %sel241}242 243define i32 @select_C_Cplus1_signext(i1 signext %cond) {244; CHECK-SD-LABEL: select_C_Cplus1_signext:245; CHECK-SD: // %bb.0:246; CHECK-SD-NEXT: mov w8, #41 // =0x29247; CHECK-SD-NEXT: tst w0, #0x1248; CHECK-SD-NEXT: cinc w0, w8, eq249; CHECK-SD-NEXT: ret250;251; CHECK-GI-LABEL: select_C_Cplus1_signext:252; CHECK-GI: // %bb.0:253; CHECK-GI-NEXT: add w0, w0, #42254; CHECK-GI-NEXT: ret255 %sel = select i1 %cond, i32 41, i32 42256 ret i32 %sel257}258 259; In general, select of 2 constants could be:260; select Cond, C1, C2 --> add (mul (zext Cond), C1-C2), C2 --> add (and (sext Cond), C1-C2), C2261 262define i32 @select_C1_C2(i1 %cond) {263; CHECK-SD-LABEL: select_C1_C2:264; CHECK-SD: // %bb.0:265; CHECK-SD-NEXT: mov w8, #42 // =0x2a266; CHECK-SD-NEXT: tst w0, #0x1267; CHECK-SD-NEXT: mov w9, #421 // =0x1a5268; CHECK-SD-NEXT: csel w0, w9, w8, ne269; CHECK-SD-NEXT: ret270;271; CHECK-GI-LABEL: select_C1_C2:272; CHECK-GI: // %bb.0:273; CHECK-GI-NEXT: and w8, w0, #0x1274; CHECK-GI-NEXT: mov w9, #42 // =0x2a275; CHECK-GI-NEXT: mov w10, #421 // =0x1a5276; CHECK-GI-NEXT: tst w8, #0x1277; CHECK-GI-NEXT: csel w0, w10, w9, ne278; CHECK-GI-NEXT: ret279 %sel = select i1 %cond, i32 421, i32 42280 ret i32 %sel281}282 283define i32 @select_C1_C2_zeroext(i1 zeroext %cond) {284; CHECK-SD-LABEL: select_C1_C2_zeroext:285; CHECK-SD: // %bb.0:286; CHECK-SD-NEXT: mov w8, #42 // =0x2a287; CHECK-SD-NEXT: cmp w0, #0288; CHECK-SD-NEXT: mov w9, #421 // =0x1a5289; CHECK-SD-NEXT: csel w0, w9, w8, ne290; CHECK-SD-NEXT: ret291;292; CHECK-GI-LABEL: select_C1_C2_zeroext:293; CHECK-GI: // %bb.0:294; CHECK-GI-NEXT: mov w8, #42 // =0x2a295; CHECK-GI-NEXT: mov w9, #421 // =0x1a5296; CHECK-GI-NEXT: tst w0, #0x1297; CHECK-GI-NEXT: csel w0, w9, w8, ne298; CHECK-GI-NEXT: ret299 %sel = select i1 %cond, i32 421, i32 42300 ret i32 %sel301}302 303define i32 @select_C1_C2_signext(i1 signext %cond) {304; CHECK-SD-LABEL: select_C1_C2_signext:305; CHECK-SD: // %bb.0:306; CHECK-SD-NEXT: mov w8, #42 // =0x2a307; CHECK-SD-NEXT: tst w0, #0x1308; CHECK-SD-NEXT: mov w9, #421 // =0x1a5309; CHECK-SD-NEXT: csel w0, w9, w8, ne310; CHECK-SD-NEXT: ret311;312; CHECK-GI-LABEL: select_C1_C2_signext:313; CHECK-GI: // %bb.0:314; CHECK-GI-NEXT: and w8, w0, #0x1315; CHECK-GI-NEXT: mov w9, #42 // =0x2a316; CHECK-GI-NEXT: mov w10, #421 // =0x1a5317; CHECK-GI-NEXT: tst w8, #0x1318; CHECK-GI-NEXT: csel w0, w10, w9, ne319; CHECK-GI-NEXT: ret320 %sel = select i1 %cond, i32 421, i32 42321 ret i32 %sel322}323 324; A binary operator with constant after the select should always get folded into the select.325 326define i8 @sel_constants_add_constant(i1 %cond) {327; CHECK-SD-LABEL: sel_constants_add_constant:328; CHECK-SD: // %bb.0:329; CHECK-SD-NEXT: mov w8, #28 // =0x1c330; CHECK-SD-NEXT: tst w0, #0x1331; CHECK-SD-NEXT: csinc w0, w8, wzr, eq332; CHECK-SD-NEXT: ret333;334; CHECK-GI-LABEL: sel_constants_add_constant:335; CHECK-GI: // %bb.0:336; CHECK-GI-NEXT: and w9, w0, #0x1337; CHECK-GI-NEXT: mov w8, #28 // =0x1c338; CHECK-GI-NEXT: tst w9, #0x1339; CHECK-GI-NEXT: csinc w0, w8, wzr, eq340; CHECK-GI-NEXT: ret341 %sel = select i1 %cond, i8 -4, i8 23342 %bo = add i8 %sel, 5343 ret i8 %bo344}345 346define i8 @sel_constants_sub_constant(i1 %cond) {347; CHECK-SD-LABEL: sel_constants_sub_constant:348; CHECK-SD: // %bb.0:349; CHECK-SD-NEXT: mov w8, #18 // =0x12350; CHECK-SD-NEXT: tst w0, #0x1351; CHECK-SD-NEXT: mov w9, #-9 // =0xfffffff7352; CHECK-SD-NEXT: csel w0, w9, w8, ne353; CHECK-SD-NEXT: ret354;355; CHECK-GI-LABEL: sel_constants_sub_constant:356; CHECK-GI: // %bb.0:357; CHECK-GI-NEXT: and w8, w0, #0x1358; CHECK-GI-NEXT: mov w9, #-9 // =0xfffffff7359; CHECK-GI-NEXT: mov w10, #18 // =0x12360; CHECK-GI-NEXT: tst w8, #0x1361; CHECK-GI-NEXT: csel w0, w9, w10, ne362; CHECK-GI-NEXT: ret363 %sel = select i1 %cond, i8 -4, i8 23364 %bo = sub i8 %sel, 5365 ret i8 %bo366}367 368define i8 @sel_constants_sub_constant_sel_constants(i1 %cond) {369; CHECK-SD-LABEL: sel_constants_sub_constant_sel_constants:370; CHECK-SD: // %bb.0:371; CHECK-SD-NEXT: mov w8, #2 // =0x2372; CHECK-SD-NEXT: tst w0, #0x1373; CHECK-SD-NEXT: mov w9, #9 // =0x9374; CHECK-SD-NEXT: csel w0, w9, w8, ne375; CHECK-SD-NEXT: ret376;377; CHECK-GI-LABEL: sel_constants_sub_constant_sel_constants:378; CHECK-GI: // %bb.0:379; CHECK-GI-NEXT: and w8, w0, #0x1380; CHECK-GI-NEXT: mov w9, #9 // =0x9381; CHECK-GI-NEXT: mov w10, #2 // =0x2382; CHECK-GI-NEXT: tst w8, #0x1383; CHECK-GI-NEXT: csel w0, w9, w10, ne384; CHECK-GI-NEXT: ret385 %sel = select i1 %cond, i8 -4, i8 3386 %bo = sub i8 5, %sel387 ret i8 %bo388}389 390define i8 @sel_constants_mul_constant(i1 %cond) {391; CHECK-SD-LABEL: sel_constants_mul_constant:392; CHECK-SD: // %bb.0:393; CHECK-SD-NEXT: mov w8, #115 // =0x73394; CHECK-SD-NEXT: tst w0, #0x1395; CHECK-SD-NEXT: mov w9, #-20 // =0xffffffec396; CHECK-SD-NEXT: csel w0, w9, w8, ne397; CHECK-SD-NEXT: ret398;399; CHECK-GI-LABEL: sel_constants_mul_constant:400; CHECK-GI: // %bb.0:401; CHECK-GI-NEXT: and w8, w0, #0x1402; CHECK-GI-NEXT: mov w9, #-4 // =0xfffffffc403; CHECK-GI-NEXT: mov w10, #23 // =0x17404; CHECK-GI-NEXT: tst w8, #0x1405; CHECK-GI-NEXT: csel w8, w9, w10, ne406; CHECK-GI-NEXT: add w0, w8, w8, lsl #2407; CHECK-GI-NEXT: ret408 %sel = select i1 %cond, i8 -4, i8 23409 %bo = mul i8 %sel, 5410 ret i8 %bo411}412 413define i8 @sel_constants_sdiv_constant(i1 %cond) {414; CHECK-SD-LABEL: sel_constants_sdiv_constant:415; CHECK-SD: // %bb.0:416; CHECK-SD-NEXT: mov w8, #4 // =0x4417; CHECK-SD-NEXT: tst w0, #0x1418; CHECK-SD-NEXT: csel w0, wzr, w8, ne419; CHECK-SD-NEXT: ret420;421; CHECK-GI-LABEL: sel_constants_sdiv_constant:422; CHECK-GI: // %bb.0:423; CHECK-GI-NEXT: eor w8, w0, #0x1424; CHECK-GI-NEXT: and w8, w8, #0x1425; CHECK-GI-NEXT: lsl w0, w8, #2426; CHECK-GI-NEXT: ret427 %sel = select i1 %cond, i8 -4, i8 23428 %bo = sdiv i8 %sel, 5429 ret i8 %bo430}431 432define i8 @sdiv_constant_sel_constants(i1 %cond) {433; CHECK-SD-LABEL: sdiv_constant_sel_constants:434; CHECK-SD: // %bb.0:435; CHECK-SD-NEXT: mov w8, #5 // =0x5436; CHECK-SD-NEXT: tst w0, #0x1437; CHECK-SD-NEXT: csel w0, wzr, w8, ne438; CHECK-SD-NEXT: ret439;440; CHECK-GI-LABEL: sdiv_constant_sel_constants:441; CHECK-GI: // %bb.0:442; CHECK-GI-NEXT: and w9, w0, #0x1443; CHECK-GI-NEXT: mov w8, #5 // =0x5444; CHECK-GI-NEXT: tst w9, #0x1445; CHECK-GI-NEXT: csel w0, wzr, w8, ne446; CHECK-GI-NEXT: ret447 %sel = select i1 %cond, i8 121, i8 23448 %bo = sdiv i8 120, %sel449 ret i8 %bo450}451 452define i8 @sel_constants_udiv_constant(i1 %cond) {453; CHECK-SD-LABEL: sel_constants_udiv_constant:454; CHECK-SD: // %bb.0:455; CHECK-SD-NEXT: mov w8, #4 // =0x4456; CHECK-SD-NEXT: tst w0, #0x1457; CHECK-SD-NEXT: mov w9, #50 // =0x32458; CHECK-SD-NEXT: csel w0, w9, w8, ne459; CHECK-SD-NEXT: ret460;461; CHECK-GI-LABEL: sel_constants_udiv_constant:462; CHECK-GI: // %bb.0:463; CHECK-GI-NEXT: and w8, w0, #0x1464; CHECK-GI-NEXT: mov w9, #50 // =0x32465; CHECK-GI-NEXT: mov w10, #4 // =0x4466; CHECK-GI-NEXT: tst w8, #0x1467; CHECK-GI-NEXT: csel w0, w9, w10, ne468; CHECK-GI-NEXT: ret469 %sel = select i1 %cond, i8 -4, i8 23470 %bo = udiv i8 %sel, 5471 ret i8 %bo472}473 474define i8 @udiv_constant_sel_constants(i1 %cond) {475; CHECK-SD-LABEL: udiv_constant_sel_constants:476; CHECK-SD: // %bb.0:477; CHECK-SD-NEXT: mov w8, #5 // =0x5478; CHECK-SD-NEXT: tst w0, #0x1479; CHECK-SD-NEXT: csel w0, wzr, w8, ne480; CHECK-SD-NEXT: ret481;482; CHECK-GI-LABEL: udiv_constant_sel_constants:483; CHECK-GI: // %bb.0:484; CHECK-GI-NEXT: and w9, w0, #0x1485; CHECK-GI-NEXT: mov w8, #5 // =0x5486; CHECK-GI-NEXT: tst w9, #0x1487; CHECK-GI-NEXT: csel w0, wzr, w8, ne488; CHECK-GI-NEXT: ret489 %sel = select i1 %cond, i8 -4, i8 23490 %bo = udiv i8 120, %sel491 ret i8 %bo492}493 494define i8 @sel_constants_srem_constant(i1 %cond) {495; CHECK-SD-LABEL: sel_constants_srem_constant:496; CHECK-SD: // %bb.0:497; CHECK-SD-NEXT: mov w8, #-4 // =0xfffffffc498; CHECK-SD-NEXT: tst w0, #0x1499; CHECK-SD-NEXT: cinv w0, w8, eq500; CHECK-SD-NEXT: ret501;502; CHECK-GI-LABEL: sel_constants_srem_constant:503; CHECK-GI: // %bb.0:504; CHECK-GI-NEXT: and w8, w0, #0x1505; CHECK-GI-NEXT: mov w9, #-4 // =0xfffffffc506; CHECK-GI-NEXT: mov w10, #3 // =0x3507; CHECK-GI-NEXT: tst w8, #0x1508; CHECK-GI-NEXT: csel w0, w9, w10, ne509; CHECK-GI-NEXT: ret510 %sel = select i1 %cond, i8 -4, i8 23511 %bo = srem i8 %sel, 5512 ret i8 %bo513}514 515define i8 @srem_constant_sel_constants(i1 %cond) {516; CHECK-SD-LABEL: srem_constant_sel_constants:517; CHECK-SD: // %bb.0:518; CHECK-SD-NEXT: mov w8, #5 // =0x5519; CHECK-SD-NEXT: tst w0, #0x1520; CHECK-SD-NEXT: mov w9, #120 // =0x78521; CHECK-SD-NEXT: csel w0, w9, w8, ne522; CHECK-SD-NEXT: ret523;524; CHECK-GI-LABEL: srem_constant_sel_constants:525; CHECK-GI: // %bb.0:526; CHECK-GI-NEXT: and w8, w0, #0x1527; CHECK-GI-NEXT: mov w9, #120 // =0x78528; CHECK-GI-NEXT: mov w10, #5 // =0x5529; CHECK-GI-NEXT: tst w8, #0x1530; CHECK-GI-NEXT: csel w0, w9, w10, ne531; CHECK-GI-NEXT: ret532 %sel = select i1 %cond, i8 121, i8 23533 %bo = srem i8 120, %sel534 ret i8 %bo535}536 537define i8 @sel_constants_urem_constant(i1 %cond) {538; CHECK-SD-LABEL: sel_constants_urem_constant:539; CHECK-SD: // %bb.0:540; CHECK-SD-NEXT: mov w8, #2 // =0x2541; CHECK-SD-NEXT: tst w0, #0x1542; CHECK-SD-NEXT: cinc w0, w8, eq543; CHECK-SD-NEXT: ret544;545; CHECK-GI-LABEL: sel_constants_urem_constant:546; CHECK-GI: // %bb.0:547; CHECK-GI-NEXT: sbfx w8, w0, #0, #1548; CHECK-GI-NEXT: add w0, w8, #3549; CHECK-GI-NEXT: ret550 %sel = select i1 %cond, i8 -4, i8 23551 %bo = urem i8 %sel, 5552 ret i8 %bo553}554 555define i8 @urem_constant_sel_constants(i1 %cond) {556; CHECK-SD-LABEL: urem_constant_sel_constants:557; CHECK-SD: // %bb.0:558; CHECK-SD-NEXT: mov w8, #5 // =0x5559; CHECK-SD-NEXT: tst w0, #0x1560; CHECK-SD-NEXT: mov w9, #120 // =0x78561; CHECK-SD-NEXT: csel w0, w9, w8, ne562; CHECK-SD-NEXT: ret563;564; CHECK-GI-LABEL: urem_constant_sel_constants:565; CHECK-GI: // %bb.0:566; CHECK-GI-NEXT: and w8, w0, #0x1567; CHECK-GI-NEXT: mov w9, #120 // =0x78568; CHECK-GI-NEXT: mov w10, #5 // =0x5569; CHECK-GI-NEXT: tst w8, #0x1570; CHECK-GI-NEXT: csel w0, w9, w10, ne571; CHECK-GI-NEXT: ret572 %sel = select i1 %cond, i8 -4, i8 23573 %bo = urem i8 120, %sel574 ret i8 %bo575}576 577define i8 @sel_constants_and_constant(i1 %cond) {578; CHECK-SD-LABEL: sel_constants_and_constant:579; CHECK-SD: // %bb.0:580; CHECK-SD-NEXT: mov w8, #4 // =0x4581; CHECK-SD-NEXT: tst w0, #0x1582; CHECK-SD-NEXT: cinc w0, w8, eq583; CHECK-SD-NEXT: ret584;585; CHECK-GI-LABEL: sel_constants_and_constant:586; CHECK-GI: // %bb.0:587; CHECK-GI-NEXT: sbfx w8, w0, #0, #1588; CHECK-GI-NEXT: add w0, w8, #5589; CHECK-GI-NEXT: ret590 %sel = select i1 %cond, i8 -4, i8 23591 %bo = and i8 %sel, 5592 ret i8 %bo593}594 595define i8 @sel_constants_or_constant(i1 %cond) {596; CHECK-SD-LABEL: sel_constants_or_constant:597; CHECK-SD: // %bb.0:598; CHECK-SD-NEXT: mov w8, #23 // =0x17599; CHECK-SD-NEXT: tst w0, #0x1600; CHECK-SD-NEXT: mov w9, #-3 // =0xfffffffd601; CHECK-SD-NEXT: csel w0, w9, w8, ne602; CHECK-SD-NEXT: ret603;604; CHECK-GI-LABEL: sel_constants_or_constant:605; CHECK-GI: // %bb.0:606; CHECK-GI-NEXT: and w8, w0, #0x1607; CHECK-GI-NEXT: mov w9, #-3 // =0xfffffffd608; CHECK-GI-NEXT: mov w10, #23 // =0x17609; CHECK-GI-NEXT: tst w8, #0x1610; CHECK-GI-NEXT: csel w0, w9, w10, ne611; CHECK-GI-NEXT: ret612 %sel = select i1 %cond, i8 -4, i8 23613 %bo = or i8 %sel, 5614 ret i8 %bo615}616 617define i8 @sel_constants_xor_constant(i1 %cond) {618; CHECK-SD-LABEL: sel_constants_xor_constant:619; CHECK-SD: // %bb.0:620; CHECK-SD-NEXT: mov w8, #18 // =0x12621; CHECK-SD-NEXT: tst w0, #0x1622; CHECK-SD-NEXT: mov w9, #-7 // =0xfffffff9623; CHECK-SD-NEXT: csel w0, w9, w8, ne624; CHECK-SD-NEXT: ret625;626; CHECK-GI-LABEL: sel_constants_xor_constant:627; CHECK-GI: // %bb.0:628; CHECK-GI-NEXT: and w8, w0, #0x1629; CHECK-GI-NEXT: mov w9, #-7 // =0xfffffff9630; CHECK-GI-NEXT: mov w10, #18 // =0x12631; CHECK-GI-NEXT: tst w8, #0x1632; CHECK-GI-NEXT: csel w0, w9, w10, ne633; CHECK-GI-NEXT: ret634 %sel = select i1 %cond, i8 -4, i8 23635 %bo = xor i8 %sel, 5636 ret i8 %bo637}638 639define i8 @sel_constants_shl_constant(i1 %cond) {640; CHECK-SD-LABEL: sel_constants_shl_constant:641; CHECK-SD: // %bb.0:642; CHECK-SD-NEXT: mov w8, #-32 // =0xffffffe0643; CHECK-SD-NEXT: tst w0, #0x1644; CHECK-SD-NEXT: mov w9, #-128 // =0xffffff80645; CHECK-SD-NEXT: csel w0, w9, w8, ne646; CHECK-SD-NEXT: ret647;648; CHECK-GI-LABEL: sel_constants_shl_constant:649; CHECK-GI: // %bb.0:650; CHECK-GI-NEXT: and w8, w0, #0x1651; CHECK-GI-NEXT: mov w9, #-128 // =0xffffff80652; CHECK-GI-NEXT: mov w10, #-32 // =0xffffffe0653; CHECK-GI-NEXT: tst w8, #0x1654; CHECK-GI-NEXT: csel w0, w9, w10, ne655; CHECK-GI-NEXT: ret656 %sel = select i1 %cond, i8 -4, i8 23657 %bo = shl i8 %sel, 5658 ret i8 %bo659}660 661define i8 @shl_constant_sel_constants(i1 %cond) {662; CHECK-SD-LABEL: shl_constant_sel_constants:663; CHECK-SD: // %bb.0:664; CHECK-SD-NEXT: mov w8, #8 // =0x8665; CHECK-SD-NEXT: tst w0, #0x1666; CHECK-SD-NEXT: mov w9, #4 // =0x4667; CHECK-SD-NEXT: csel w0, w9, w8, ne668; CHECK-SD-NEXT: ret669;670; CHECK-GI-LABEL: shl_constant_sel_constants:671; CHECK-GI: // %bb.0:672; CHECK-GI-NEXT: sbfx w9, w0, #0, #1673; CHECK-GI-NEXT: mov w8, #1 // =0x1674; CHECK-GI-NEXT: add w9, w9, #3675; CHECK-GI-NEXT: and w9, w9, #0xff676; CHECK-GI-NEXT: lsl w0, w8, w9677; CHECK-GI-NEXT: ret678 %sel = select i1 %cond, i8 2, i8 3679 %bo = shl i8 1, %sel680 ret i8 %bo681}682 683define i8 @sel_constants_lshr_constant(i1 %cond) {684; CHECK-SD-LABEL: sel_constants_lshr_constant:685; CHECK-SD: // %bb.0:686; CHECK-SD-NEXT: mov w8, #7 // =0x7687; CHECK-SD-NEXT: tst w0, #0x1688; CHECK-SD-NEXT: csel w0, w8, wzr, ne689; CHECK-SD-NEXT: ret690;691; CHECK-GI-LABEL: sel_constants_lshr_constant:692; CHECK-GI: // %bb.0:693; CHECK-GI-NEXT: and w9, w0, #0x1694; CHECK-GI-NEXT: mov w8, #7 // =0x7695; CHECK-GI-NEXT: tst w9, #0x1696; CHECK-GI-NEXT: csel w0, w8, wzr, ne697; CHECK-GI-NEXT: ret698 %sel = select i1 %cond, i8 -4, i8 23699 %bo = lshr i8 %sel, 5700 ret i8 %bo701}702 703define i8 @lshr_constant_sel_constants(i1 %cond) {704; CHECK-SD-LABEL: lshr_constant_sel_constants:705; CHECK-SD: // %bb.0:706; CHECK-SD-NEXT: mov w8, #8 // =0x8707; CHECK-SD-NEXT: tst w0, #0x1708; CHECK-SD-NEXT: mov w9, #16 // =0x10709; CHECK-SD-NEXT: csel w0, w9, w8, ne710; CHECK-SD-NEXT: ret711;712; CHECK-GI-LABEL: lshr_constant_sel_constants:713; CHECK-GI: // %bb.0:714; CHECK-GI-NEXT: sbfx w9, w0, #0, #1715; CHECK-GI-NEXT: mov w8, #64 // =0x40716; CHECK-GI-NEXT: add w9, w9, #3717; CHECK-GI-NEXT: and w9, w9, #0xff718; CHECK-GI-NEXT: lsr w0, w8, w9719; CHECK-GI-NEXT: ret720 %sel = select i1 %cond, i8 2, i8 3721 %bo = lshr i8 64, %sel722 ret i8 %bo723}724 725 726define i8 @sel_constants_ashr_constant(i1 %cond) {727; CHECK-LABEL: sel_constants_ashr_constant:728; CHECK: // %bb.0:729; CHECK-NEXT: sbfx w0, w0, #0, #1730; CHECK-NEXT: ret731 %sel = select i1 %cond, i8 -4, i8 23732 %bo = ashr i8 %sel, 5733 ret i8 %bo734}735 736define i8 @ashr_constant_sel_constants(i1 %cond) {737; CHECK-SD-LABEL: ashr_constant_sel_constants:738; CHECK-SD: // %bb.0:739; CHECK-SD-NEXT: mov w8, #-16 // =0xfffffff0740; CHECK-SD-NEXT: tst w0, #0x1741; CHECK-SD-NEXT: mov w9, #-32 // =0xffffffe0742; CHECK-SD-NEXT: csel w0, w9, w8, ne743; CHECK-SD-NEXT: ret744;745; CHECK-GI-LABEL: ashr_constant_sel_constants:746; CHECK-GI: // %bb.0:747; CHECK-GI-NEXT: sbfx w9, w0, #0, #1748; CHECK-GI-NEXT: mov w8, #-128 // =0xffffff80749; CHECK-GI-NEXT: add w9, w9, #3750; CHECK-GI-NEXT: and w9, w9, #0xff751; CHECK-GI-NEXT: asr w0, w8, w9752; CHECK-GI-NEXT: ret753 %sel = select i1 %cond, i8 2, i8 3754 %bo = ashr i8 128, %sel755 ret i8 %bo756}757 758define double @sel_constants_fadd_constant(i1 %cond) {759; CHECK-SD-LABEL: sel_constants_fadd_constant:760; CHECK-SD: // %bb.0:761; CHECK-SD-NEXT: mov x9, #7378697629483820646 // =0x6666666666666666762; CHECK-SD-NEXT: adrp x8, .LCPI42_0763; CHECK-SD-NEXT: tst w0, #0x1764; CHECK-SD-NEXT: movk x9, #16444, lsl #48765; CHECK-SD-NEXT: ldr d0, [x8, :lo12:.LCPI42_0]766; CHECK-SD-NEXT: fmov d1, x9767; CHECK-SD-NEXT: fcsel d0, d0, d1, ne768; CHECK-SD-NEXT: ret769;770; CHECK-GI-LABEL: sel_constants_fadd_constant:771; CHECK-GI: // %bb.0:772; CHECK-GI-NEXT: mov x9, #7378697629483820646 // =0x6666666666666666773; CHECK-GI-NEXT: adrp x8, .LCPI42_0774; CHECK-GI-NEXT: movk x9, #16444, lsl #48775; CHECK-GI-NEXT: ldr d0, [x8, :lo12:.LCPI42_0]776; CHECK-GI-NEXT: and w8, w0, #0x1777; CHECK-GI-NEXT: fmov d1, x9778; CHECK-GI-NEXT: tst w8, #0x1779; CHECK-GI-NEXT: fcsel d0, d0, d1, ne780; CHECK-GI-NEXT: ret781 %sel = select i1 %cond, double -4.0, double 23.3782 %bo = fadd double %sel, 5.1783 ret double %bo784}785 786define double @sel_constants_fsub_constant(i1 %cond) {787; CHECK-SD-LABEL: sel_constants_fsub_constant:788; CHECK-SD: // %bb.0:789; CHECK-SD-NEXT: adrp x8, .LCPI43_0790; CHECK-SD-NEXT: tst w0, #0x1791; CHECK-SD-NEXT: ldr d0, [x8, :lo12:.LCPI43_0]792; CHECK-SD-NEXT: mov x8, #3689348814741910323 // =0x3333333333333333793; CHECK-SD-NEXT: movk x8, #49186, lsl #48794; CHECK-SD-NEXT: fmov d1, x8795; CHECK-SD-NEXT: fcsel d0, d1, d0, ne796; CHECK-SD-NEXT: ret797;798; CHECK-GI-LABEL: sel_constants_fsub_constant:799; CHECK-GI: // %bb.0:800; CHECK-GI-NEXT: adrp x8, .LCPI43_0801; CHECK-GI-NEXT: and w9, w0, #0x1802; CHECK-GI-NEXT: ldr d0, [x8, :lo12:.LCPI43_0]803; CHECK-GI-NEXT: mov x8, #3689348814741910323 // =0x3333333333333333804; CHECK-GI-NEXT: tst w9, #0x1805; CHECK-GI-NEXT: movk x8, #49186, lsl #48806; CHECK-GI-NEXT: fmov d1, x8807; CHECK-GI-NEXT: fcsel d0, d1, d0, ne808; CHECK-GI-NEXT: ret809 %sel = select i1 %cond, double -4.0, double 23.3810 %bo = fsub double %sel, 5.1811 ret double %bo812}813 814define double @fsub_constant_sel_constants(i1 %cond) {815; CHECK-SD-LABEL: fsub_constant_sel_constants:816; CHECK-SD: // %bb.0:817; CHECK-SD-NEXT: adrp x8, .LCPI44_0818; CHECK-SD-NEXT: tst w0, #0x1819; CHECK-SD-NEXT: ldr d0, [x8, :lo12:.LCPI44_0]820; CHECK-SD-NEXT: mov x8, #3689348814741910323 // =0x3333333333333333821; CHECK-SD-NEXT: movk x8, #16418, lsl #48822; CHECK-SD-NEXT: fmov d1, x8823; CHECK-SD-NEXT: fcsel d0, d1, d0, ne824; CHECK-SD-NEXT: ret825;826; CHECK-GI-LABEL: fsub_constant_sel_constants:827; CHECK-GI: // %bb.0:828; CHECK-GI-NEXT: adrp x8, .LCPI44_0829; CHECK-GI-NEXT: and w9, w0, #0x1830; CHECK-GI-NEXT: ldr d0, [x8, :lo12:.LCPI44_0]831; CHECK-GI-NEXT: mov x8, #3689348814741910323 // =0x3333333333333333832; CHECK-GI-NEXT: tst w9, #0x1833; CHECK-GI-NEXT: movk x8, #16418, lsl #48834; CHECK-GI-NEXT: fmov d1, x8835; CHECK-GI-NEXT: fcsel d0, d1, d0, ne836; CHECK-GI-NEXT: ret837 %sel = select i1 %cond, double -4.0, double 23.3838 %bo = fsub double 5.1, %sel839 ret double %bo840}841 842define double @sel_constants_fmul_constant(i1 %cond) {843; CHECK-SD-LABEL: sel_constants_fmul_constant:844; CHECK-SD: // %bb.0:845; CHECK-SD-NEXT: adrp x8, .LCPI45_0846; CHECK-SD-NEXT: tst w0, #0x1847; CHECK-SD-NEXT: ldr d0, [x8, :lo12:.LCPI45_0]848; CHECK-SD-NEXT: mov x8, #7378697629483820646 // =0x6666666666666666849; CHECK-SD-NEXT: movk x8, #49204, lsl #48850; CHECK-SD-NEXT: fmov d1, x8851; CHECK-SD-NEXT: fcsel d0, d1, d0, ne852; CHECK-SD-NEXT: ret853;854; CHECK-GI-LABEL: sel_constants_fmul_constant:855; CHECK-GI: // %bb.0:856; CHECK-GI-NEXT: adrp x8, .LCPI45_0857; CHECK-GI-NEXT: and w9, w0, #0x1858; CHECK-GI-NEXT: ldr d0, [x8, :lo12:.LCPI45_0]859; CHECK-GI-NEXT: mov x8, #7378697629483820646 // =0x6666666666666666860; CHECK-GI-NEXT: tst w9, #0x1861; CHECK-GI-NEXT: movk x8, #49204, lsl #48862; CHECK-GI-NEXT: fmov d1, x8863; CHECK-GI-NEXT: fcsel d0, d1, d0, ne864; CHECK-GI-NEXT: ret865 %sel = select i1 %cond, double -4.0, double 23.3866 %bo = fmul double %sel, 5.1867 ret double %bo868}869 870define double @sel_constants_fdiv_constant(i1 %cond) {871; CHECK-SD-LABEL: sel_constants_fdiv_constant:872; CHECK-SD: // %bb.0:873; CHECK-SD-NEXT: adrp x8, .LCPI46_0874; CHECK-SD-NEXT: adrp x9, .LCPI46_1875; CHECK-SD-NEXT: tst w0, #0x1876; CHECK-SD-NEXT: ldr d0, [x8, :lo12:.LCPI46_0]877; CHECK-SD-NEXT: ldr d1, [x9, :lo12:.LCPI46_1]878; CHECK-SD-NEXT: fcsel d0, d1, d0, ne879; CHECK-SD-NEXT: ret880;881; CHECK-GI-LABEL: sel_constants_fdiv_constant:882; CHECK-GI: // %bb.0:883; CHECK-GI-NEXT: adrp x8, .LCPI46_1884; CHECK-GI-NEXT: adrp x9, .LCPI46_0885; CHECK-GI-NEXT: ldr d0, [x8, :lo12:.LCPI46_1]886; CHECK-GI-NEXT: ldr d1, [x9, :lo12:.LCPI46_0]887; CHECK-GI-NEXT: and w8, w0, #0x1888; CHECK-GI-NEXT: tst w8, #0x1889; CHECK-GI-NEXT: fcsel d0, d1, d0, ne890; CHECK-GI-NEXT: ret891 %sel = select i1 %cond, double -4.0, double 23.3892 %bo = fdiv double %sel, 5.1893 ret double %bo894}895 896define double @fdiv_constant_sel_constants(i1 %cond) {897; CHECK-SD-LABEL: fdiv_constant_sel_constants:898; CHECK-SD: // %bb.0:899; CHECK-SD-NEXT: adrp x8, .LCPI47_0900; CHECK-SD-NEXT: tst w0, #0x1901; CHECK-SD-NEXT: ldr d0, [x8, :lo12:.LCPI47_0]902; CHECK-SD-NEXT: mov x8, #7378697629483820646 // =0x6666666666666666903; CHECK-SD-NEXT: movk x8, #49140, lsl #48904; CHECK-SD-NEXT: fmov d1, x8905; CHECK-SD-NEXT: fcsel d0, d1, d0, ne906; CHECK-SD-NEXT: ret907;908; CHECK-GI-LABEL: fdiv_constant_sel_constants:909; CHECK-GI: // %bb.0:910; CHECK-GI-NEXT: adrp x8, .LCPI47_0911; CHECK-GI-NEXT: and w9, w0, #0x1912; CHECK-GI-NEXT: ldr d0, [x8, :lo12:.LCPI47_0]913; CHECK-GI-NEXT: mov x8, #7378697629483820646 // =0x6666666666666666914; CHECK-GI-NEXT: tst w9, #0x1915; CHECK-GI-NEXT: movk x8, #49140, lsl #48916; CHECK-GI-NEXT: fmov d1, x8917; CHECK-GI-NEXT: fcsel d0, d1, d0, ne918; CHECK-GI-NEXT: ret919 %sel = select i1 %cond, double -4.0, double 23.3920 %bo = fdiv double 5.1, %sel921 ret double %bo922}923 924define double @sel_constants_frem_constant(i1 %cond) {925; CHECK-SD-LABEL: sel_constants_frem_constant:926; CHECK-SD: // %bb.0:927; CHECK-SD-NEXT: adrp x8, .LCPI48_0928; CHECK-SD-NEXT: fmov d0, #-4.00000000929; CHECK-SD-NEXT: tst w0, #0x1930; CHECK-SD-NEXT: ldr d1, [x8, :lo12:.LCPI48_0]931; CHECK-SD-NEXT: fcsel d0, d0, d1, ne932; CHECK-SD-NEXT: ret933;934; CHECK-GI-LABEL: sel_constants_frem_constant:935; CHECK-GI: // %bb.0:936; CHECK-GI-NEXT: adrp x8, .LCPI48_0937; CHECK-GI-NEXT: fmov d0, #-4.00000000938; CHECK-GI-NEXT: ldr d1, [x8, :lo12:.LCPI48_0]939; CHECK-GI-NEXT: and w8, w0, #0x1940; CHECK-GI-NEXT: tst w8, #0x1941; CHECK-GI-NEXT: fcsel d0, d0, d1, ne942; CHECK-GI-NEXT: ret943 %sel = select i1 %cond, double -4.0, double 23.3944 %bo = frem double %sel, 5.1945 ret double %bo946}947 948define double @frem_constant_sel_constants(i1 %cond) {949; CHECK-SD-LABEL: frem_constant_sel_constants:950; CHECK-SD: // %bb.0:951; CHECK-SD-NEXT: mov x9, #7378697629483820646 // =0x6666666666666666952; CHECK-SD-NEXT: adrp x8, .LCPI49_0953; CHECK-SD-NEXT: tst w0, #0x1954; CHECK-SD-NEXT: movk x9, #16404, lsl #48955; CHECK-SD-NEXT: ldr d0, [x8, :lo12:.LCPI49_0]956; CHECK-SD-NEXT: fmov d1, x9957; CHECK-SD-NEXT: fcsel d0, d0, d1, ne958; CHECK-SD-NEXT: ret959;960; CHECK-GI-LABEL: frem_constant_sel_constants:961; CHECK-GI: // %bb.0:962; CHECK-GI-NEXT: adrp x8, .LCPI49_0963; CHECK-GI-NEXT: and w9, w0, #0x1964; CHECK-GI-NEXT: ldr d0, [x8, :lo12:.LCPI49_0]965; CHECK-GI-NEXT: mov x8, #7378697629483820646 // =0x6666666666666666966; CHECK-GI-NEXT: tst w9, #0x1967; CHECK-GI-NEXT: movk x8, #16404, lsl #48968; CHECK-GI-NEXT: fmov d1, x8969; CHECK-GI-NEXT: fcsel d0, d0, d1, ne970; CHECK-GI-NEXT: ret971 %sel = select i1 %cond, double -4.0, double 23.3972 %bo = frem double 5.1, %sel973 ret double %bo974}975