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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=aarch64-unknown-unknown | FileCheck %s --check-prefixes=CHECK,CHECK-SD3; RUN: llc < %s -mtriple=aarch64-unknown-unknown -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI4 5; Compare if negative and select of constants where one constant is zero.6 7define i32 @neg_sel_constants(i32 %a) {8; CHECK-SD-LABEL: neg_sel_constants:9; CHECK-SD: // %bb.0:10; CHECK-SD-NEXT: mov w8, #5 // =0x511; CHECK-SD-NEXT: and w0, w8, w0, asr #3112; CHECK-SD-NEXT: ret13;14; CHECK-GI-LABEL: neg_sel_constants:15; CHECK-GI: // %bb.0:16; CHECK-GI-NEXT: mov w8, #5 // =0x517; CHECK-GI-NEXT: cmp w0, #018; CHECK-GI-NEXT: csel w0, w8, wzr, mi19; CHECK-GI-NEXT: ret20 %tmp.1 = icmp slt i32 %a, 021 %retval = select i1 %tmp.1, i32 5, i32 022 ret i32 %retval23}24 25; Compare if negative and select of constants where one constant is zero and the other is a single bit.26 27define i32 @neg_sel_special_constant(i32 %a) {28; CHECK-SD-LABEL: neg_sel_special_constant:29; CHECK-SD: // %bb.0:30; CHECK-SD-NEXT: lsr w8, w0, #2231; CHECK-SD-NEXT: and w0, w8, #0x20032; CHECK-SD-NEXT: ret33;34; CHECK-GI-LABEL: neg_sel_special_constant:35; CHECK-GI: // %bb.0:36; CHECK-GI-NEXT: cmp w0, #037; CHECK-GI-NEXT: cset w8, mi38; CHECK-GI-NEXT: lsl w0, w8, #939; CHECK-GI-NEXT: ret40 %tmp.1 = icmp slt i32 %a, 041 %retval = select i1 %tmp.1, i32 512, i32 042 ret i32 %retval43}44 45; Compare if negative and select variable or zero.46 47define i32 @neg_sel_variable_and_zero(i32 %a, i32 %b) {48; CHECK-SD-LABEL: neg_sel_variable_and_zero:49; CHECK-SD: // %bb.0:50; CHECK-SD-NEXT: and w0, w1, w0, asr #3151; CHECK-SD-NEXT: ret52;53; CHECK-GI-LABEL: neg_sel_variable_and_zero:54; CHECK-GI: // %bb.0:55; CHECK-GI-NEXT: cmp w0, #056; CHECK-GI-NEXT: csel w0, w1, wzr, mi57; CHECK-GI-NEXT: ret58 %tmp.1 = icmp slt i32 %a, 059 %retval = select i1 %tmp.1, i32 %b, i32 060 ret i32 %retval61}62 63; Compare if not positive and select the same variable as being compared: smin(a, 0).64 65define i32 @not_pos_sel_same_variable(i32 %a) {66; CHECK-SD-LABEL: not_pos_sel_same_variable:67; CHECK-SD: // %bb.0:68; CHECK-SD-NEXT: and w0, w0, w0, asr #3169; CHECK-SD-NEXT: ret70;71; CHECK-GI-LABEL: not_pos_sel_same_variable:72; CHECK-GI: // %bb.0:73; CHECK-GI-NEXT: cmp w0, #174; CHECK-GI-NEXT: csel w0, w0, wzr, lt75; CHECK-GI-NEXT: ret76 %tmp = icmp slt i32 %a, 177 %min = select i1 %tmp, i32 %a, i32 078 ret i32 %min79}80 81; Flipping the comparison condition can be handled by getting the bitwise not of the sign mask.82 83; Compare if positive and select of constants where one constant is zero.84 85define i32 @pos_sel_constants(i32 %a) {86; CHECK-SD-LABEL: pos_sel_constants:87; CHECK-SD: // %bb.0:88; CHECK-SD-NEXT: mov w8, #5 // =0x589; CHECK-SD-NEXT: bic w0, w8, w0, asr #3190; CHECK-SD-NEXT: ret91;92; CHECK-GI-LABEL: pos_sel_constants:93; CHECK-GI: // %bb.0:94; CHECK-GI-NEXT: mov w8, #5 // =0x595; CHECK-GI-NEXT: cmp w0, #096; CHECK-GI-NEXT: csel w0, w8, wzr, pl97; CHECK-GI-NEXT: ret98 %tmp.1 = icmp sgt i32 %a, -199 %retval = select i1 %tmp.1, i32 5, i32 0100 ret i32 %retval101}102 103; Compare if positive and select of constants where one constant is zero and the other is a single bit.104 105define i32 @pos_sel_special_constant(i32 %a) {106; CHECK-SD-LABEL: pos_sel_special_constant:107; CHECK-SD: // %bb.0:108; CHECK-SD-NEXT: mov w8, #512 // =0x200109; CHECK-SD-NEXT: bic w0, w8, w0, lsr #22110; CHECK-SD-NEXT: ret111;112; CHECK-GI-LABEL: pos_sel_special_constant:113; CHECK-GI: // %bb.0:114; CHECK-GI-NEXT: cmp w0, #0115; CHECK-GI-NEXT: cset w8, pl116; CHECK-GI-NEXT: lsl w0, w8, #9117; CHECK-GI-NEXT: ret118 %tmp.1 = icmp sgt i32 %a, -1119 %retval = select i1 %tmp.1, i32 512, i32 0120 ret i32 %retval121}122 123; Compare if positive and select variable or zero.124 125define i32 @pos_sel_variable_and_zero(i32 %a, i32 %b) {126; CHECK-SD-LABEL: pos_sel_variable_and_zero:127; CHECK-SD: // %bb.0:128; CHECK-SD-NEXT: bic w0, w1, w0, asr #31129; CHECK-SD-NEXT: ret130;131; CHECK-GI-LABEL: pos_sel_variable_and_zero:132; CHECK-GI: // %bb.0:133; CHECK-GI-NEXT: cmp w0, #0134; CHECK-GI-NEXT: csel w0, w1, wzr, pl135; CHECK-GI-NEXT: ret136 %tmp.1 = icmp sgt i32 %a, -1137 %retval = select i1 %tmp.1, i32 %b, i32 0138 ret i32 %retval139}140 141; Compare if not negative or zero and select the same variable as being compared: smax(a, 0).142 143define i32 @not_neg_sel_same_variable(i32 %a) {144; CHECK-SD-LABEL: not_neg_sel_same_variable:145; CHECK-SD: // %bb.0:146; CHECK-SD-NEXT: bic w0, w0, w0, asr #31147; CHECK-SD-NEXT: ret148;149; CHECK-GI-LABEL: not_neg_sel_same_variable:150; CHECK-GI: // %bb.0:151; CHECK-GI-NEXT: cmp w0, #0152; CHECK-GI-NEXT: csel w0, w0, wzr, gt153; CHECK-GI-NEXT: ret154 %tmp = icmp sgt i32 %a, 0155 %min = select i1 %tmp, i32 %a, i32 0156 ret i32 %min157}158 159; https://llvm.org/bugs/show_bug.cgi?id=31175160 161; ret = (x-y) > 0 ? x-y : 0162define i32 @PR31175(i32 %x, i32 %y) {163; CHECK-SD-LABEL: PR31175:164; CHECK-SD: // %bb.0:165; CHECK-SD-NEXT: sub w8, w0, w1166; CHECK-SD-NEXT: bic w0, w8, w8, asr #31167; CHECK-SD-NEXT: ret168;169; CHECK-GI-LABEL: PR31175:170; CHECK-GI: // %bb.0:171; CHECK-GI-NEXT: subs w8, w0, w1172; CHECK-GI-NEXT: csel w0, w8, wzr, gt173; CHECK-GI-NEXT: ret174 %sub = sub nsw i32 %x, %y175 %cmp = icmp sgt i32 %sub, 0176 %sel = select i1 %cmp, i32 %sub, i32 0177 ret i32 %sel178}179 180define i8 @sel_shift_bool_i8(i1 %t) {181; CHECK-SD-LABEL: sel_shift_bool_i8:182; CHECK-SD: // %bb.0:183; CHECK-SD-NEXT: mov w8, #-128 // =0xffffff80184; CHECK-SD-NEXT: tst w0, #0x1185; CHECK-SD-NEXT: csel w0, w8, wzr, ne186; CHECK-SD-NEXT: ret187;188; CHECK-GI-LABEL: sel_shift_bool_i8:189; CHECK-GI: // %bb.0:190; CHECK-GI-NEXT: lsl w0, w0, #7191; CHECK-GI-NEXT: ret192 %shl = select i1 %t, i8 128, i8 0193 ret i8 %shl194}195 196define i16 @sel_shift_bool_i16(i1 %t) {197; CHECK-SD-LABEL: sel_shift_bool_i16:198; CHECK-SD: // %bb.0:199; CHECK-SD-NEXT: mov w8, #128 // =0x80200; CHECK-SD-NEXT: tst w0, #0x1201; CHECK-SD-NEXT: csel w0, w8, wzr, ne202; CHECK-SD-NEXT: ret203;204; CHECK-GI-LABEL: sel_shift_bool_i16:205; CHECK-GI: // %bb.0:206; CHECK-GI-NEXT: and w8, w0, #0x1207; CHECK-GI-NEXT: lsl w0, w8, #7208; CHECK-GI-NEXT: ret209 %shl = select i1 %t, i16 128, i16 0210 ret i16 %shl211}212 213define i32 @sel_shift_bool_i32(i1 %t) {214; CHECK-SD-LABEL: sel_shift_bool_i32:215; CHECK-SD: // %bb.0:216; CHECK-SD-NEXT: mov w8, #64 // =0x40217; CHECK-SD-NEXT: tst w0, #0x1218; CHECK-SD-NEXT: csel w0, w8, wzr, ne219; CHECK-SD-NEXT: ret220;221; CHECK-GI-LABEL: sel_shift_bool_i32:222; CHECK-GI: // %bb.0:223; CHECK-GI-NEXT: and w8, w0, #0x1224; CHECK-GI-NEXT: lsl w0, w8, #6225; CHECK-GI-NEXT: ret226 %shl = select i1 %t, i32 64, i32 0227 ret i32 %shl228}229 230define i64 @sel_shift_bool_i64(i1 %t) {231; CHECK-SD-LABEL: sel_shift_bool_i64:232; CHECK-SD: // %bb.0:233; CHECK-SD-NEXT: mov w8, #65536 // =0x10000234; CHECK-SD-NEXT: tst w0, #0x1235; CHECK-SD-NEXT: csel x0, x8, xzr, ne236; CHECK-SD-NEXT: ret237;238; CHECK-GI-LABEL: sel_shift_bool_i64:239; CHECK-GI: // %bb.0:240; CHECK-GI-NEXT: // kill: def $w0 killed $w0 def $x0241; CHECK-GI-NEXT: and x8, x0, #0x1242; CHECK-GI-NEXT: lsl x0, x8, #16243; CHECK-GI-NEXT: ret244 %shl = select i1 %t, i64 65536, i64 0245 ret i64 %shl246}247 248define <16 x i8> @sel_shift_bool_v16i8(<16 x i1> %t) {249; CHECK-SD-LABEL: sel_shift_bool_v16i8:250; CHECK-SD: // %bb.0:251; CHECK-SD-NEXT: shl v0.16b, v0.16b, #7252; CHECK-SD-NEXT: ret253;254; CHECK-GI-LABEL: sel_shift_bool_v16i8:255; CHECK-GI: // %bb.0:256; CHECK-GI-NEXT: shl v0.16b, v0.16b, #7257; CHECK-GI-NEXT: movi v1.16b, #128258; CHECK-GI-NEXT: cmlt v0.16b, v0.16b, #0259; CHECK-GI-NEXT: and v0.16b, v1.16b, v0.16b260; CHECK-GI-NEXT: ret261 %shl = select <16 x i1> %t, <16 x i8> <i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128, i8 128>, <16 x i8> zeroinitializer262 ret <16 x i8> %shl263}264 265define <8 x i16> @sel_shift_bool_v8i16(<8 x i1> %t) {266; CHECK-SD-LABEL: sel_shift_bool_v8i16:267; CHECK-SD: // %bb.0:268; CHECK-SD-NEXT: ushll v0.8h, v0.8b, #0269; CHECK-SD-NEXT: movi v1.8h, #128270; CHECK-SD-NEXT: shl v0.8h, v0.8h, #15271; CHECK-SD-NEXT: cmlt v0.8h, v0.8h, #0272; CHECK-SD-NEXT: and v0.16b, v0.16b, v1.16b273; CHECK-SD-NEXT: ret274;275; CHECK-GI-LABEL: sel_shift_bool_v8i16:276; CHECK-GI: // %bb.0:277; CHECK-GI-NEXT: ushll v0.8h, v0.8b, #0278; CHECK-GI-NEXT: movi v1.8h, #128279; CHECK-GI-NEXT: shl v0.8h, v0.8h, #15280; CHECK-GI-NEXT: cmlt v0.8h, v0.8h, #0281; CHECK-GI-NEXT: and v0.16b, v1.16b, v0.16b282; CHECK-GI-NEXT: ret283 %shl= select <8 x i1> %t, <8 x i16> <i16 128, i16 128, i16 128, i16 128, i16 128, i16 128, i16 128, i16 128>, <8 x i16> zeroinitializer284 ret <8 x i16> %shl285}286 287define <4 x i32> @sel_shift_bool_v4i32(<4 x i1> %t) {288; CHECK-SD-LABEL: sel_shift_bool_v4i32:289; CHECK-SD: // %bb.0:290; CHECK-SD-NEXT: ushll v0.4s, v0.4h, #0291; CHECK-SD-NEXT: movi v1.4s, #64292; CHECK-SD-NEXT: shl v0.4s, v0.4s, #31293; CHECK-SD-NEXT: cmlt v0.4s, v0.4s, #0294; CHECK-SD-NEXT: and v0.16b, v0.16b, v1.16b295; CHECK-SD-NEXT: ret296;297; CHECK-GI-LABEL: sel_shift_bool_v4i32:298; CHECK-GI: // %bb.0:299; CHECK-GI-NEXT: ushll v0.4s, v0.4h, #0300; CHECK-GI-NEXT: movi v1.4s, #64301; CHECK-GI-NEXT: shl v0.4s, v0.4s, #31302; CHECK-GI-NEXT: cmlt v0.4s, v0.4s, #0303; CHECK-GI-NEXT: and v0.16b, v1.16b, v0.16b304; CHECK-GI-NEXT: ret305 %shl = select <4 x i1> %t, <4 x i32> <i32 64, i32 64, i32 64, i32 64>, <4 x i32> zeroinitializer306 ret <4 x i32> %shl307}308 309define <2 x i64> @sel_shift_bool_v2i64(<2 x i1> %t) {310; CHECK-SD-LABEL: sel_shift_bool_v2i64:311; CHECK-SD: // %bb.0:312; CHECK-SD-NEXT: ushll v0.2d, v0.2s, #0313; CHECK-SD-NEXT: mov w8, #65536 // =0x10000314; CHECK-SD-NEXT: dup v1.2d, x8315; CHECK-SD-NEXT: shl v0.2d, v0.2d, #63316; CHECK-SD-NEXT: cmlt v0.2d, v0.2d, #0317; CHECK-SD-NEXT: and v0.16b, v0.16b, v1.16b318; CHECK-SD-NEXT: ret319;320; CHECK-GI-LABEL: sel_shift_bool_v2i64:321; CHECK-GI: // %bb.0:322; CHECK-GI-NEXT: ushll v0.2d, v0.2s, #0323; CHECK-GI-NEXT: adrp x8, .LCPI16_0324; CHECK-GI-NEXT: ldr q1, [x8, :lo12:.LCPI16_0]325; CHECK-GI-NEXT: shl v0.2d, v0.2d, #63326; CHECK-GI-NEXT: cmlt v0.2d, v0.2d, #0327; CHECK-GI-NEXT: and v0.16b, v1.16b, v0.16b328; CHECK-GI-NEXT: ret329 %shl = select <2 x i1> %t, <2 x i64> <i64 65536, i64 65536>, <2 x i64> zeroinitializer330 ret <2 x i64> %shl331}332;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:333; CHECK: {{.*}}334