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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-- -o - %s | FileCheck %s3 4declare i32 @llvm.fshl.i32(i32, i32, i32)5declare i16 @llvm.fshr.i16(i16, i16, i16)6declare i64 @llvm.fshr.i64(i64, i64, i64)7declare <4 x i32> @llvm.fshl.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)8 9define i1 @fshl_or_eq_0(i32 %x, i32 %y) {10; CHECK-LABEL: fshl_or_eq_0:11; CHECK: // %bb.0:12; CHECK-NEXT: orr w8, w0, w1, lsl #513; CHECK-NEXT: cmp w8, #014; CHECK-NEXT: cset w0, eq15; CHECK-NEXT: ret16 %or = or i32 %x, %y17 %f = call i32 @llvm.fshl.i32(i32 %or, i32 %x, i32 5)18 %r = icmp eq i32 %f, 019 ret i1 %r20}21 22define i1 @fshl_or_commute_eq_0(i32 %x, i32 %y) {23; CHECK-LABEL: fshl_or_commute_eq_0:24; CHECK: // %bb.0:25; CHECK-NEXT: orr w8, w0, w1, lsl #526; CHECK-NEXT: cmp w8, #027; CHECK-NEXT: cset w0, eq28; CHECK-NEXT: ret29 %or = or i32 %y, %x30 %f = call i32 @llvm.fshl.i32(i32 %or, i32 %x, i32 5)31 %r = icmp eq i32 %f, 032 ret i1 %r33}34 35define <4 x i1> @fshl_or2_eq_0(<4 x i32> %x, <4 x i32> %y) {36; CHECK-LABEL: fshl_or2_eq_0:37; CHECK: // %bb.0:38; CHECK-NEXT: ushr v1.4s, v1.4s, #739; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b40; CHECK-NEXT: cmeq v0.4s, v0.4s, #041; CHECK-NEXT: xtn v0.4h, v0.4s42; CHECK-NEXT: ret43 %or = or <4 x i32> %x, %y44 %f = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %x, <4 x i32> %or, <4 x i32> <i32 25, i32 25, i32 25, i32 25>)45 %r = icmp eq <4 x i32> %f, zeroinitializer46 ret <4 x i1> %r47}48 49define <4 x i1> @fshl_or2_commute_eq_0(<4 x i32> %x, <4 x i32> %y) {50; CHECK-LABEL: fshl_or2_commute_eq_0:51; CHECK: // %bb.0:52; CHECK-NEXT: ushr v1.4s, v1.4s, #753; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b54; CHECK-NEXT: cmeq v0.4s, v0.4s, #055; CHECK-NEXT: xtn v0.4h, v0.4s56; CHECK-NEXT: ret57 %or = or <4 x i32> %y, %x58 %f = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %x, <4 x i32> %or, <4 x i32> <i32 25, i32 25, i32 25, i32 25>)59 %r = icmp eq <4 x i32> %f, zeroinitializer60 ret <4 x i1> %r61}62 63define i1 @fshr_or_eq_0(i16 %x, i16 %y) {64; CHECK-LABEL: fshr_or_eq_0:65; CHECK: // %bb.0:66; CHECK-NEXT: orr w8, w0, w1, lsl #867; CHECK-NEXT: tst w8, #0xffff68; CHECK-NEXT: cset w0, eq69; CHECK-NEXT: ret70 %or = or i16 %x, %y71 %f = call i16 @llvm.fshr.i16(i16 %or, i16 %x, i16 8)72 %r = icmp eq i16 %f, 073 ret i1 %r74}75 76define i1 @fshr_or_commute_eq_0(i16 %x, i16 %y) {77; CHECK-LABEL: fshr_or_commute_eq_0:78; CHECK: // %bb.0:79; CHECK-NEXT: orr w8, w0, w1, lsl #880; CHECK-NEXT: tst w8, #0xffff81; CHECK-NEXT: cset w0, eq82; CHECK-NEXT: ret83 %or = or i16 %y, %x84 %f = call i16 @llvm.fshr.i16(i16 %or, i16 %x, i16 8)85 %r = icmp eq i16 %f, 086 ret i1 %r87}88 89define i1 @fshr_or2_eq_0(i64 %x, i64 %y) {90; CHECK-LABEL: fshr_or2_eq_0:91; CHECK: // %bb.0:92; CHECK-NEXT: orr x8, x0, x1, lsr #393; CHECK-NEXT: cmp x8, #094; CHECK-NEXT: cset w0, eq95; CHECK-NEXT: ret96 %or = or i64 %x, %y97 %f = call i64 @llvm.fshr.i64(i64 %x, i64 %or, i64 3)98 %r = icmp eq i64 %f, 099 ret i1 %r100}101 102define i1 @fshl_or_ne_0(i32 %x, i32 %y) {103; CHECK-LABEL: fshl_or_ne_0:104; CHECK: // %bb.0:105; CHECK-NEXT: orr w8, w0, w1, lsl #7106; CHECK-NEXT: cmp w8, #0107; CHECK-NEXT: cset w0, ne108; CHECK-NEXT: ret109 %or = or i32 %x, %y110 %f = call i32 @llvm.fshl.i32(i32 %or, i32 %x, i32 7)111 %r = icmp ne i32 %f, 0112 ret i1 %r113}114 115define i1 @fshl_or_commute_ne_0(i32 %x, i32 %y) {116; CHECK-LABEL: fshl_or_commute_ne_0:117; CHECK: // %bb.0:118; CHECK-NEXT: orr w8, w0, w1, lsl #7119; CHECK-NEXT: cmp w8, #0120; CHECK-NEXT: cset w0, ne121; CHECK-NEXT: ret122 %or = or i32 %y, %x123 %f = call i32 @llvm.fshl.i32(i32 %or, i32 %x, i32 7)124 %r = icmp ne i32 %f, 0125 ret i1 %r126}127 128define <4 x i1> @fshl_or2_ne_0(<4 x i32> %x, <4 x i32> %y) {129; CHECK-LABEL: fshl_or2_ne_0:130; CHECK: // %bb.0:131; CHECK-NEXT: ushr v1.4s, v1.4s, #27132; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b133; CHECK-NEXT: cmtst v0.4s, v0.4s, v0.4s134; CHECK-NEXT: xtn v0.4h, v0.4s135; CHECK-NEXT: ret136 %or = or <4 x i32> %x, %y137 %f = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %x, <4 x i32> %or, <4 x i32> <i32 5, i32 5, i32 5, i32 5>)138 %r = icmp ne <4 x i32> %f, zeroinitializer139 ret <4 x i1> %r140}141 142define <4 x i1> @fshl_or2_commute_ne_0(<4 x i32> %x, <4 x i32> %y) {143; CHECK-LABEL: fshl_or2_commute_ne_0:144; CHECK: // %bb.0:145; CHECK-NEXT: ushr v1.4s, v1.4s, #27146; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b147; CHECK-NEXT: cmtst v0.4s, v0.4s, v0.4s148; CHECK-NEXT: xtn v0.4h, v0.4s149; CHECK-NEXT: ret150 %or = or <4 x i32> %y, %x151 %f = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %x, <4 x i32> %or, <4 x i32> <i32 5, i32 5, i32 5, i32 5>)152 %r = icmp ne <4 x i32> %f, zeroinitializer153 ret <4 x i1> %r154}155 156define i1 @fshr_or_ne_0(i64 %x, i64 %y) {157; CHECK-LABEL: fshr_or_ne_0:158; CHECK: // %bb.0:159; CHECK-NEXT: orr x8, x0, x1, lsl #63160; CHECK-NEXT: cmp x8, #0161; CHECK-NEXT: cset w0, ne162; CHECK-NEXT: ret163 %or = or i64 %x, %y164 %f = call i64 @llvm.fshr.i64(i64 %or, i64 %x, i64 1)165 %r = icmp ne i64 %f, 0166 ret i1 %r167}168 169define i1 @fshr_or_commute_ne_0(i64 %x, i64 %y) {170; CHECK-LABEL: fshr_or_commute_ne_0:171; CHECK: // %bb.0:172; CHECK-NEXT: orr x8, x0, x1, lsl #63173; CHECK-NEXT: cmp x8, #0174; CHECK-NEXT: cset w0, ne175; CHECK-NEXT: ret176 %or = or i64 %y, %x177 %f = call i64 @llvm.fshr.i64(i64 %or, i64 %x, i64 1)178 %r = icmp ne i64 %f, 0179 ret i1 %r180}181 182define i1 @fshr_or2_ne_0(i16 %x, i16 %y) {183; CHECK-LABEL: fshr_or2_ne_0:184; CHECK: // %bb.0:185; CHECK-NEXT: and w8, w1, #0xfffc186; CHECK-NEXT: orr w8, w0, w8, lsr #2187; CHECK-NEXT: tst w8, #0xffff188; CHECK-NEXT: cset w0, ne189; CHECK-NEXT: ret190 %or = or i16 %x, %y191 %f = call i16 @llvm.fshr.i16(i16 %x, i16 %or, i16 2)192 %r = icmp ne i16 %f, 0193 ret i1 %r194}195 196define i1 @fshr_or2_commute_ne_0(i16 %x, i16 %y) {197; CHECK-LABEL: fshr_or2_commute_ne_0:198; CHECK: // %bb.0:199; CHECK-NEXT: and w8, w1, #0xfffc200; CHECK-NEXT: orr w8, w0, w8, lsr #2201; CHECK-NEXT: tst w8, #0xffff202; CHECK-NEXT: cset w0, ne203; CHECK-NEXT: ret204 %or = or i16 %y, %x205 %f = call i16 @llvm.fshr.i16(i16 %x, i16 %or, i16 2)206 %r = icmp ne i16 %f, 0207 ret i1 %r208}209 210define i1 @fshl_xor_eq_0(i32 %x, i32 %y) {211; CHECK-LABEL: fshl_xor_eq_0:212; CHECK: // %bb.0:213; CHECK-NEXT: eor w8, w0, w1214; CHECK-NEXT: extr w8, w8, w0, #30215; CHECK-NEXT: cmp w8, #0216; CHECK-NEXT: cset w0, eq217; CHECK-NEXT: ret218 %or = xor i32 %x, %y219 %f = call i32 @llvm.fshl.i32(i32 %or, i32 %x, i32 2)220 %r = icmp eq i32 %f, 0221 ret i1 %r222}223 224define i1 @fshl_or_sgt_0(i32 %x, i32 %y) {225; CHECK-LABEL: fshl_or_sgt_0:226; CHECK: // %bb.0:227; CHECK-NEXT: orr w8, w0, w1228; CHECK-NEXT: extr w8, w8, w0, #30229; CHECK-NEXT: cmp w8, #0230; CHECK-NEXT: cset w0, gt231; CHECK-NEXT: ret232 %or = or i32 %x, %y233 %f = call i32 @llvm.fshl.i32(i32 %or, i32 %x, i32 2)234 %r = icmp sgt i32 %f, 0235 ret i1 %r236}237 238define i1 @fshl_or_ne_2(i32 %x, i32 %y) {239; CHECK-LABEL: fshl_or_ne_2:240; CHECK: // %bb.0:241; CHECK-NEXT: orr w8, w0, w1242; CHECK-NEXT: extr w8, w8, w0, #30243; CHECK-NEXT: cmp w8, #2244; CHECK-NEXT: cset w0, ne245; CHECK-NEXT: ret246 %or = or i32 %x, %y247 %f = call i32 @llvm.fshl.i32(i32 %or, i32 %x, i32 2)248 %r = icmp ne i32 %f, 2249 ret i1 %r250}251 252define i1 @fshr_0_or_eq_0(i16 %x, i16 %y) {253; CHECK-LABEL: fshr_0_or_eq_0:254; CHECK: // %bb.0:255; CHECK-NEXT: tst w0, #0xffff256; CHECK-NEXT: cset w0, eq257; CHECK-NEXT: ret258 %or = or i16 %x, %y259 %f = call i16 @llvm.fshr.i16(i16 %or, i16 %x, i16 0)260 %r = icmp eq i16 %f, 0261 ret i1 %r262}263 264define i1 @fshr_32_or_eq_0(i16 %x, i16 %y) {265; CHECK-LABEL: fshr_32_or_eq_0:266; CHECK: // %bb.0:267; CHECK-NEXT: tst w0, #0xffff268; CHECK-NEXT: cset w0, eq269; CHECK-NEXT: ret270 %or = or i16 %x, %y271 %f = call i16 @llvm.fshr.i16(i16 %or, i16 %x, i16 32)272 %r = icmp eq i16 %f, 0273 ret i1 %r274}275