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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s3 4; If we have a shift by sign-extended value, we can replace sign-extension5; with zero-extension.6 7define i32 @t0_shl(i32 %x, i8 %shamt) nounwind {8; CHECK-LABEL: t0_shl:9; CHECK: // %bb.0:10; CHECK-NEXT: sxtb w8, w111; CHECK-NEXT: lsl w0, w0, w812; CHECK-NEXT: ret13 %shamt_wide = sext i8 %shamt to i3214 %r = shl i32 %x, %shamt_wide15 ret i32 %r16}17define i32 @t1_lshr(i32 %x, i8 %shamt) nounwind {18; CHECK-LABEL: t1_lshr:19; CHECK: // %bb.0:20; CHECK-NEXT: sxtb w8, w121; CHECK-NEXT: lsr w0, w0, w822; CHECK-NEXT: ret23 %shamt_wide = sext i8 %shamt to i3224 %r = lshr i32 %x, %shamt_wide25 ret i32 %r26}27define i32 @t2_ashr(i32 %x, i8 %shamt) nounwind {28; CHECK-LABEL: t2_ashr:29; CHECK: // %bb.0:30; CHECK-NEXT: sxtb w8, w131; CHECK-NEXT: asr w0, w0, w832; CHECK-NEXT: ret33 %shamt_wide = sext i8 %shamt to i3234 %r = ashr i32 %x, %shamt_wide35 ret i32 %r36}37 38define <4 x i32> @t3_vec_shl(<4 x i32> %x, <4 x i8> %shamt) nounwind {39; CHECK-LABEL: t3_vec_shl:40; CHECK: // %bb.0:41; CHECK-NEXT: ushll v1.4s, v1.4h, #042; CHECK-NEXT: shl v1.4s, v1.4s, #2443; CHECK-NEXT: sshr v1.4s, v1.4s, #2444; CHECK-NEXT: ushl v0.4s, v0.4s, v1.4s45; CHECK-NEXT: ret46 %shamt_wide = sext <4 x i8> %shamt to <4 x i32>47 %r = shl <4 x i32> %x, %shamt_wide48 ret <4 x i32> %r49}50define <4 x i32> @t4_vec_lshr(<4 x i32> %x, <4 x i8> %shamt) nounwind {51; CHECK-LABEL: t4_vec_lshr:52; CHECK: // %bb.0:53; CHECK-NEXT: ushll v1.4s, v1.4h, #054; CHECK-NEXT: shl v1.4s, v1.4s, #2455; CHECK-NEXT: sshr v1.4s, v1.4s, #2456; CHECK-NEXT: neg v1.4s, v1.4s57; CHECK-NEXT: ushl v0.4s, v0.4s, v1.4s58; CHECK-NEXT: ret59 %shamt_wide = sext <4 x i8> %shamt to <4 x i32>60 %r = lshr <4 x i32> %x, %shamt_wide61 ret <4 x i32> %r62}63define <4 x i32> @t5_vec_ashr(<4 x i32> %x, <4 x i8> %shamt) nounwind {64; CHECK-LABEL: t5_vec_ashr:65; CHECK: // %bb.0:66; CHECK-NEXT: ushll v1.4s, v1.4h, #067; CHECK-NEXT: shl v1.4s, v1.4s, #2468; CHECK-NEXT: sshr v1.4s, v1.4s, #2469; CHECK-NEXT: neg v1.4s, v1.4s70; CHECK-NEXT: sshl v0.4s, v0.4s, v1.4s71; CHECK-NEXT: ret72 %shamt_wide = sext <4 x i8> %shamt to <4 x i32>73 %r = ashr <4 x i32> %x, %shamt_wide74 ret <4 x i32> %r75}76 77; This is not valid for funnel shifts78declare i32 @llvm.fshl.i32(i32 %a, i32 %b, i32 %c)79declare i32 @llvm.fshr.i32(i32 %a, i32 %b, i32 %c)80define i32 @n6_fshl(i32 %x, i32 %y, i8 %shamt) nounwind {81; CHECK-LABEL: n6_fshl:82; CHECK: // %bb.0:83; CHECK-NEXT: lsr w8, w1, #184; CHECK-NEXT: mvn w9, w285; CHECK-NEXT: lsl w10, w0, w286; CHECK-NEXT: lsr w8, w8, w987; CHECK-NEXT: orr w0, w10, w888; CHECK-NEXT: ret89 %shamt_wide = sext i8 %shamt to i3290 %r = call i32 @llvm.fshl.i32(i32 %x, i32 %y, i32 %shamt_wide)91 ret i32 %r92}93define i32 @n7_fshr(i32 %x, i32 %y, i8 %shamt) nounwind {94; CHECK-LABEL: n7_fshr:95; CHECK: // %bb.0:96; CHECK-NEXT: lsl w8, w0, #197; CHECK-NEXT: mvn w9, w298; CHECK-NEXT: lsr w10, w1, w299; CHECK-NEXT: lsl w8, w8, w9100; CHECK-NEXT: orr w0, w8, w10101; CHECK-NEXT: ret102 %shamt_wide = sext i8 %shamt to i32103 %r = call i32 @llvm.fshr.i32(i32 %x, i32 %y, i32 %shamt_wide)104 ret i32 %r105}106 107define i32 @n8_extrause(i32 %x, i8 %shamt, ptr %shamt_wide_store) nounwind {108; CHECK-LABEL: n8_extrause:109; CHECK: // %bb.0:110; CHECK-NEXT: sxtb w8, w1111; CHECK-NEXT: lsl w0, w0, w8112; CHECK-NEXT: str w8, [x2]113; CHECK-NEXT: ret114 %shamt_wide = sext i8 %shamt to i32115 store i32 %shamt_wide, ptr %shamt_wide_store, align 4116 %r = shl i32 %x, %shamt_wide117 ret i32 %r118}119