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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64 < %s | FileCheck %s3 4; Check that we optimize out AND instructions and ADD/SUB instructions5; modulo the shift size to take advantage of the implicit mod done on6; the shift amount value by the variable shift/rotate instructions.7 8define i32 @test1(i32 %x, i64 %y) {9; CHECK-LABEL: test1:10; CHECK: // %bb.0:11; CHECK-NEXT: lsr w0, w0, w112; CHECK-NEXT: ret13 %sh_prom = trunc i64 %y to i3214 %shr = lshr i32 %x, %sh_prom15 ret i32 %shr16}17 18define i64 @test2(i32 %x, i64 %y) {19; CHECK-LABEL: test2:20; CHECK: // %bb.0:21; CHECK-NEXT: neg w8, w022; CHECK-NEXT: asr x0, x1, x823; CHECK-NEXT: ret24 %sub9 = sub nsw i32 64, %x25 %sh_prom12.i = zext i32 %sub9 to i6426 %shr.i = ashr i64 %y, %sh_prom12.i27 ret i64 %shr.i28}29 30define i64 @test3(i64 %x, i64 %y) {31; CHECK-LABEL: test3:32; CHECK: // %bb.0:33; CHECK-NEXT: lsl x0, x1, x034; CHECK-NEXT: ret35 %add = add nsw i64 64, %x36 %shl = shl i64 %y, %add37 ret i64 %shl38}39 40define i64 @test4(i64 %y, i32 %s) {41; CHECK-LABEL: test4:42; CHECK: // %bb.0: // %entry43; CHECK-NEXT: // kill: def $w1 killed $w1 def $x144; CHECK-NEXT: asr x0, x0, x145; CHECK-NEXT: ret46entry:47 %sh_prom = zext i32 %s to i6448 %shr = ashr i64 %y, %sh_prom49 ret i64 %shr50}51 52define i64 @test5(i64 %y, i32 %s) {53; CHECK-LABEL: test5:54; CHECK: // %bb.0: // %entry55; CHECK-NEXT: // kill: def $w1 killed $w1 def $x156; CHECK-NEXT: asr x0, x0, x157; CHECK-NEXT: ret58entry:59 %sh_prom = sext i32 %s to i6460 %shr = ashr i64 %y, %sh_prom61 ret i64 %shr62}63 64define i64 @test6(i64 %y, i32 %s) {65; CHECK-LABEL: test6:66; CHECK: // %bb.0: // %entry67; CHECK-NEXT: // kill: def $w1 killed $w1 def $x168; CHECK-NEXT: lsl x0, x0, x169; CHECK-NEXT: ret70entry:71 %sh_prom = sext i32 %s to i6472 %shr = shl i64 %y, %sh_prom73 ret i64 %shr74}75 76; PR42644 - https://bugs.llvm.org/show_bug.cgi?id=4264477 78define i64 @ashr_add_shl_i32(i64 %r) {79; CHECK-LABEL: ashr_add_shl_i32:80; CHECK: // %bb.0:81; CHECK-NEXT: add w8, w0, #182; CHECK-NEXT: sxtw x0, w883; CHECK-NEXT: ret84 %conv = shl i64 %r, 3285 %sext = add i64 %conv, 429496729686 %conv1 = ashr i64 %sext, 3287 ret i64 %conv188}89 90define i64 @ashr_add_shl_i8(i64 %r) {91; CHECK-LABEL: ashr_add_shl_i8:92; CHECK: // %bb.0:93; CHECK-NEXT: add w8, w0, #194; CHECK-NEXT: sxtb x0, w895; CHECK-NEXT: ret96 %conv = shl i64 %r, 5697 %sext = add i64 %conv, 7205759403792793698 %conv1 = ashr i64 %sext, 5699 ret i64 %conv1100}101 102define <4 x i32> @ashr_add_shl_v4i8(<4 x i32> %r) {103; CHECK-LABEL: ashr_add_shl_v4i8:104; CHECK: // %bb.0:105; CHECK-NEXT: movi v1.4s, #1, lsl #24106; CHECK-NEXT: shl v0.4s, v0.4s, #24107; CHECK-NEXT: add v0.4s, v0.4s, v1.4s108; CHECK-NEXT: sshr v0.4s, v0.4s, #24109; CHECK-NEXT: ret110 %conv = shl <4 x i32> %r, <i32 24, i32 24, i32 24, i32 24>111 %sext = add <4 x i32> %conv, <i32 16777216, i32 16777216, i32 16777216, i32 16777216>112 %conv1 = ashr <4 x i32> %sext, <i32 24, i32 24, i32 24, i32 24>113 ret <4 x i32> %conv1114}115 116define i64 @ashr_add_shl_i36(i64 %r) {117; CHECK-LABEL: ashr_add_shl_i36:118; CHECK: // %bb.0:119; CHECK-NEXT: sbfx x0, x0, #0, #28120; CHECK-NEXT: ret121 %conv = shl i64 %r, 36122 %sext = add i64 %conv, 4294967296123 %conv1 = ashr i64 %sext, 36124 ret i64 %conv1125}126 127define i64 @ashr_add_shl_mismatch_shifts1(i64 %r) {128; CHECK-LABEL: ashr_add_shl_mismatch_shifts1:129; CHECK: // %bb.0:130; CHECK-NEXT: mov x8, #4294967296131; CHECK-NEXT: add x8, x8, x0, lsl #8132; CHECK-NEXT: asr x0, x8, #32133; CHECK-NEXT: ret134 %conv = shl i64 %r, 8135 %sext = add i64 %conv, 4294967296136 %conv1 = ashr i64 %sext, 32137 ret i64 %conv1138}139 140define i64 @ashr_add_shl_mismatch_shifts2(i64 %r) {141; CHECK-LABEL: ashr_add_shl_mismatch_shifts2:142; CHECK: // %bb.0:143; CHECK-NEXT: mov x8, #4294967296144; CHECK-NEXT: add x8, x8, x0, lsr #8145; CHECK-NEXT: lsr x0, x8, #8146; CHECK-NEXT: ret147 %conv = lshr i64 %r, 8148 %sext = add i64 %conv, 4294967296149 %conv1 = ashr i64 %sext, 8150 ret i64 %conv1151}152