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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 42; RUN: llc -mtriple=aarch64 -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-SD3; RUN: llc -mtriple=aarch64 -global-isel -verify-machineinstrs %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-GI4 5define i1 @shl_i1(i1 %0, i1 %1){6; CHECK-SD-LABEL: shl_i1:7; CHECK-SD: // %bb.0:8; CHECK-SD-NEXT: and w0, w0, #0x19; CHECK-SD-NEXT: ret10;11; CHECK-GI-LABEL: shl_i1:12; CHECK-GI: // %bb.0:13; CHECK-GI-NEXT: and w8, w1, #0x114; CHECK-GI-NEXT: lsl w8, w0, w815; CHECK-GI-NEXT: and w0, w8, #0x116; CHECK-GI-NEXT: ret17 %3 = shl i1 %0, %118 ret i1 %319}20 21define i8 @shl_i8(i8 %0, i8 %1){22; CHECK-SD-LABEL: shl_i8:23; CHECK-SD: // %bb.0:24; CHECK-SD-NEXT: lsl w0, w0, w125; CHECK-SD-NEXT: ret26;27; CHECK-GI-LABEL: shl_i8:28; CHECK-GI: // %bb.0:29; CHECK-GI-NEXT: and w8, w1, #0xff30; CHECK-GI-NEXT: lsl w0, w0, w831; CHECK-GI-NEXT: ret32 %3 = shl i8 %0, %133 ret i8 %334}35 36define i16 @shl_i16(i16 %0, i16 %1){37; CHECK-SD-LABEL: shl_i16:38; CHECK-SD: // %bb.0:39; CHECK-SD-NEXT: lsl w0, w0, w140; CHECK-SD-NEXT: ret41;42; CHECK-GI-LABEL: shl_i16:43; CHECK-GI: // %bb.0:44; CHECK-GI-NEXT: and w8, w1, #0xffff45; CHECK-GI-NEXT: lsl w0, w0, w846; CHECK-GI-NEXT: ret47 %3 = shl i16 %0, %148 ret i16 %349}50 51define i32 @shl_i32(i32 %0, i32 %1){52; CHECK-LABEL: shl_i32:53; CHECK: // %bb.0:54; CHECK-NEXT: lsl w0, w0, w155; CHECK-NEXT: ret56 %3 = shl i32 %0, %157 ret i32 %358}59 60define i64 @shl_i64(i64 %0, i64 %1){61; CHECK-LABEL: shl_i64:62; CHECK: // %bb.0:63; CHECK-NEXT: lsl x0, x0, x164; CHECK-NEXT: ret65 %3 = shl i64 %0, %166 ret i64 %367}68 69define i128 @shl_i128(i128 %0, i128 %1){70; CHECK-SD-LABEL: shl_i128:71; CHECK-SD: // %bb.0:72; CHECK-SD-NEXT: lsr x8, x0, #173; CHECK-SD-NEXT: mvn w9, w274; CHECK-SD-NEXT: lsl x10, x1, x275; CHECK-SD-NEXT: tst x2, #0x4076; CHECK-SD-NEXT: lsr x8, x8, x977; CHECK-SD-NEXT: lsl x9, x0, x278; CHECK-SD-NEXT: orr x8, x10, x879; CHECK-SD-NEXT: csel x0, xzr, x9, ne80; CHECK-SD-NEXT: csel x1, x9, x8, ne81; CHECK-SD-NEXT: ret82;83; CHECK-GI-LABEL: shl_i128:84; CHECK-GI: // %bb.0:85; CHECK-GI-NEXT: mov w8, #64 // =0x4086; CHECK-GI-NEXT: sub x9, x2, #6487; CHECK-GI-NEXT: lsl x10, x1, x288; CHECK-GI-NEXT: sub x8, x8, x289; CHECK-GI-NEXT: lsl x11, x0, x290; CHECK-GI-NEXT: lsl x9, x0, x991; CHECK-GI-NEXT: lsr x8, x0, x892; CHECK-GI-NEXT: cmp x2, #6493; CHECK-GI-NEXT: csel x0, x11, xzr, lo94; CHECK-GI-NEXT: orr x8, x8, x1095; CHECK-GI-NEXT: csel x8, x8, x9, lo96; CHECK-GI-NEXT: cmp x2, #097; CHECK-GI-NEXT: csel x1, x1, x8, eq98; CHECK-GI-NEXT: ret99 %3 = shl i128 %0, %1100 ret i128 %3101}102 103define i1 @ashr_i1(i1 %0, i1 %1){104; CHECK-SD-LABEL: ashr_i1:105; CHECK-SD: // %bb.0:106; CHECK-SD-NEXT: and w0, w0, #0x1107; CHECK-SD-NEXT: ret108;109; CHECK-GI-LABEL: ashr_i1:110; CHECK-GI: // %bb.0:111; CHECK-GI-NEXT: sbfx w8, w0, #0, #1112; CHECK-GI-NEXT: and w9, w1, #0x1113; CHECK-GI-NEXT: asr w8, w8, w9114; CHECK-GI-NEXT: and w0, w8, #0x1115; CHECK-GI-NEXT: ret116 %3 = ashr i1 %0, %1117 ret i1 %3118}119 120define i8 @ashr_i8(i8 %0, i8 %1){121; CHECK-SD-LABEL: ashr_i8:122; CHECK-SD: // %bb.0:123; CHECK-SD-NEXT: sxtb w8, w0124; CHECK-SD-NEXT: asr w0, w8, w1125; CHECK-SD-NEXT: ret126;127; CHECK-GI-LABEL: ashr_i8:128; CHECK-GI: // %bb.0:129; CHECK-GI-NEXT: sxtb w8, w0130; CHECK-GI-NEXT: and w9, w1, #0xff131; CHECK-GI-NEXT: asr w0, w8, w9132; CHECK-GI-NEXT: ret133 %3 = ashr i8 %0, %1134 ret i8 %3135}136 137define i16 @ashr_i16(i16 %0, i16 %1){138; CHECK-SD-LABEL: ashr_i16:139; CHECK-SD: // %bb.0:140; CHECK-SD-NEXT: sxth w8, w0141; CHECK-SD-NEXT: asr w0, w8, w1142; CHECK-SD-NEXT: ret143;144; CHECK-GI-LABEL: ashr_i16:145; CHECK-GI: // %bb.0:146; CHECK-GI-NEXT: sxth w8, w0147; CHECK-GI-NEXT: and w9, w1, #0xffff148; CHECK-GI-NEXT: asr w0, w8, w9149; CHECK-GI-NEXT: ret150 %3 = ashr i16 %0, %1151 ret i16 %3152}153 154define i32 @ashr_i32(i32 %0, i32 %1){155; CHECK-LABEL: ashr_i32:156; CHECK: // %bb.0:157; CHECK-NEXT: asr w0, w0, w1158; CHECK-NEXT: ret159 %3 = ashr i32 %0, %1160 ret i32 %3161}162 163define i64 @ashr_i64(i64 %0, i64 %1){164; CHECK-LABEL: ashr_i64:165; CHECK: // %bb.0:166; CHECK-NEXT: asr x0, x0, x1167; CHECK-NEXT: ret168 %3 = ashr i64 %0, %1169 ret i64 %3170}171 172define i128 @ashr_i128(i128 %0, i128 %1){173; CHECK-SD-LABEL: ashr_i128:174; CHECK-SD: // %bb.0:175; CHECK-SD-NEXT: lsl x8, x1, #1176; CHECK-SD-NEXT: mvn w9, w2177; CHECK-SD-NEXT: lsr x10, x0, x2178; CHECK-SD-NEXT: asr x11, x1, #63179; CHECK-SD-NEXT: tst x2, #0x40180; CHECK-SD-NEXT: lsl x8, x8, x9181; CHECK-SD-NEXT: asr x9, x1, x2182; CHECK-SD-NEXT: orr x8, x8, x10183; CHECK-SD-NEXT: csel x1, x11, x9, ne184; CHECK-SD-NEXT: csel x0, x9, x8, ne185; CHECK-SD-NEXT: ret186;187; CHECK-GI-LABEL: ashr_i128:188; CHECK-GI: // %bb.0:189; CHECK-GI-NEXT: mov w8, #64 // =0x40190; CHECK-GI-NEXT: sub x9, x2, #64191; CHECK-GI-NEXT: lsr x10, x0, x2192; CHECK-GI-NEXT: sub x8, x8, x2193; CHECK-GI-NEXT: asr x9, x1, x9194; CHECK-GI-NEXT: cmp x2, #64195; CHECK-GI-NEXT: lsl x8, x1, x8196; CHECK-GI-NEXT: asr x11, x1, x2197; CHECK-GI-NEXT: orr x8, x10, x8198; CHECK-GI-NEXT: asr x10, x1, #63199; CHECK-GI-NEXT: csel x8, x8, x9, lo200; CHECK-GI-NEXT: cmp x2, #0201; CHECK-GI-NEXT: csel x0, x0, x8, eq202; CHECK-GI-NEXT: cmp x2, #64203; CHECK-GI-NEXT: csel x1, x11, x10, lo204; CHECK-GI-NEXT: ret205 %3 = ashr i128 %0, %1206 ret i128 %3207}208 209define i1 @lshr_i1(i1 %0, i1 %1){210; CHECK-SD-LABEL: lshr_i1:211; CHECK-SD: // %bb.0:212; CHECK-SD-NEXT: and w0, w0, #0x1213; CHECK-SD-NEXT: ret214;215; CHECK-GI-LABEL: lshr_i1:216; CHECK-GI: // %bb.0:217; CHECK-GI-NEXT: and w8, w1, #0x1218; CHECK-GI-NEXT: and w9, w0, #0x1219; CHECK-GI-NEXT: lsr w0, w9, w8220; CHECK-GI-NEXT: ret221 %3 = lshr i1 %0, %1222 ret i1 %3223}224 225define i8 @lshr_i8(i8 %0, i8 %1){226; CHECK-SD-LABEL: lshr_i8:227; CHECK-SD: // %bb.0:228; CHECK-SD-NEXT: and w8, w0, #0xff229; CHECK-SD-NEXT: lsr w0, w8, w1230; CHECK-SD-NEXT: ret231;232; CHECK-GI-LABEL: lshr_i8:233; CHECK-GI: // %bb.0:234; CHECK-GI-NEXT: and w8, w1, #0xff235; CHECK-GI-NEXT: and w9, w0, #0xff236; CHECK-GI-NEXT: lsr w0, w9, w8237; CHECK-GI-NEXT: ret238 %3 = lshr i8 %0, %1239 ret i8 %3240}241 242define i16 @lshr_i16(i16 %0, i16 %1){243; CHECK-SD-LABEL: lshr_i16:244; CHECK-SD: // %bb.0:245; CHECK-SD-NEXT: and w8, w0, #0xffff246; CHECK-SD-NEXT: lsr w0, w8, w1247; CHECK-SD-NEXT: ret248;249; CHECK-GI-LABEL: lshr_i16:250; CHECK-GI: // %bb.0:251; CHECK-GI-NEXT: and w8, w1, #0xffff252; CHECK-GI-NEXT: and w9, w0, #0xffff253; CHECK-GI-NEXT: lsr w0, w9, w8254; CHECK-GI-NEXT: ret255 %3 = lshr i16 %0, %1256 ret i16 %3257}258 259define i32 @lshr_i32(i32 %0, i32 %1){260; CHECK-LABEL: lshr_i32:261; CHECK: // %bb.0:262; CHECK-NEXT: lsr w0, w0, w1263; CHECK-NEXT: ret264 %3 = lshr i32 %0, %1265 ret i32 %3266}267 268define i64 @lshr_i64(i64 %0, i64 %1){269; CHECK-LABEL: lshr_i64:270; CHECK: // %bb.0:271; CHECK-NEXT: lsr x0, x0, x1272; CHECK-NEXT: ret273 %3 = lshr i64 %0, %1274 ret i64 %3275}276 277define i128 @lshr_i128(i128 %0, i128 %1){278; CHECK-SD-LABEL: lshr_i128:279; CHECK-SD: // %bb.0:280; CHECK-SD-NEXT: lsl x8, x1, #1281; CHECK-SD-NEXT: mvn w9, w2282; CHECK-SD-NEXT: lsr x10, x0, x2283; CHECK-SD-NEXT: tst x2, #0x40284; CHECK-SD-NEXT: lsl x8, x8, x9285; CHECK-SD-NEXT: lsr x9, x1, x2286; CHECK-SD-NEXT: orr x8, x8, x10287; CHECK-SD-NEXT: csel x1, xzr, x9, ne288; CHECK-SD-NEXT: csel x0, x9, x8, ne289; CHECK-SD-NEXT: ret290;291; CHECK-GI-LABEL: lshr_i128:292; CHECK-GI: // %bb.0:293; CHECK-GI-NEXT: mov w8, #64 // =0x40294; CHECK-GI-NEXT: sub x9, x2, #64295; CHECK-GI-NEXT: lsr x10, x0, x2296; CHECK-GI-NEXT: sub x8, x8, x2297; CHECK-GI-NEXT: lsr x9, x1, x9298; CHECK-GI-NEXT: cmp x2, #64299; CHECK-GI-NEXT: lsl x8, x1, x8300; CHECK-GI-NEXT: orr x8, x10, x8301; CHECK-GI-NEXT: lsr x10, x1, x2302; CHECK-GI-NEXT: csel x8, x8, x9, lo303; CHECK-GI-NEXT: cmp x2, #0304; CHECK-GI-NEXT: csel x0, x0, x8, eq305; CHECK-GI-NEXT: cmp x2, #64306; CHECK-GI-NEXT: csel x1, x10, xzr, lo307; CHECK-GI-NEXT: ret308 %3 = lshr i128 %0, %1309 ret i128 %3310}311 312; ===== Legal Vector Type =====313 314define <8 x i8> @shl_v8i8(<8 x i8> %0, <8 x i8> %1){315; CHECK-LABEL: shl_v8i8:316; CHECK: // %bb.0:317; CHECK-NEXT: ushl v0.8b, v0.8b, v1.8b318; CHECK-NEXT: ret319 %3 = shl <8 x i8> %0, %1320 ret <8 x i8> %3321}322 323define <16 x i8> @shl_v16i8(<16 x i8> %0, <16 x i8> %1){324; CHECK-LABEL: shl_v16i8:325; CHECK: // %bb.0:326; CHECK-NEXT: ushl v0.16b, v0.16b, v1.16b327; CHECK-NEXT: ret328 %3 = shl <16 x i8> %0, %1329 ret <16 x i8> %3330}331 332define <4 x i16> @shl_v4i16(<4 x i16> %0, <4 x i16> %1){333; CHECK-LABEL: shl_v4i16:334; CHECK: // %bb.0:335; CHECK-NEXT: ushl v0.4h, v0.4h, v1.4h336; CHECK-NEXT: ret337 %3 = shl <4 x i16> %0, %1338 ret <4 x i16> %3339}340 341define <8 x i16> @shl_v8i16(<8 x i16> %0, <8 x i16> %1){342; CHECK-LABEL: shl_v8i16:343; CHECK: // %bb.0:344; CHECK-NEXT: ushl v0.8h, v0.8h, v1.8h345; CHECK-NEXT: ret346 %3 = shl <8 x i16> %0, %1347 ret <8 x i16> %3348}349 350define <2 x i32> @shl_v2i32(<2 x i32> %0, <2 x i32> %1){351; CHECK-LABEL: shl_v2i32:352; CHECK: // %bb.0:353; CHECK-NEXT: ushl v0.2s, v0.2s, v1.2s354; CHECK-NEXT: ret355 %3 = shl <2 x i32> %0, %1356 ret <2 x i32> %3357}358 359define <4 x i32> @shl_v4i32(<4 x i32> %0, <4 x i32> %1){360; CHECK-LABEL: shl_v4i32:361; CHECK: // %bb.0:362; CHECK-NEXT: ushl v0.4s, v0.4s, v1.4s363; CHECK-NEXT: ret364 %3 = shl <4 x i32> %0, %1365 ret <4 x i32> %3366}367 368define <2 x i64> @shl_v2i64(<2 x i64> %0, <2 x i64> %1){369; CHECK-LABEL: shl_v2i64:370; CHECK: // %bb.0:371; CHECK-NEXT: ushl v0.2d, v0.2d, v1.2d372; CHECK-NEXT: ret373 %3 = shl <2 x i64> %0, %1374 ret <2 x i64> %3375}376 377define <8 x i8> @ashr_v8i8(<8 x i8> %0, <8 x i8> %1){378; CHECK-LABEL: ashr_v8i8:379; CHECK: // %bb.0:380; CHECK-NEXT: neg v1.8b, v1.8b381; CHECK-NEXT: sshl v0.8b, v0.8b, v1.8b382; CHECK-NEXT: ret383 %3 = ashr <8 x i8> %0, %1384 ret <8 x i8> %3385}386 387define <16 x i8> @ashr_v16i8(<16 x i8> %0, <16 x i8> %1){388; CHECK-LABEL: ashr_v16i8:389; CHECK: // %bb.0:390; CHECK-NEXT: neg v1.16b, v1.16b391; CHECK-NEXT: sshl v0.16b, v0.16b, v1.16b392; CHECK-NEXT: ret393 %3 = ashr <16 x i8> %0, %1394 ret <16 x i8> %3395}396 397define <4 x i16> @ashr_v4i16(<4 x i16> %0, <4 x i16> %1){398; CHECK-LABEL: ashr_v4i16:399; CHECK: // %bb.0:400; CHECK-NEXT: neg v1.4h, v1.4h401; CHECK-NEXT: sshl v0.4h, v0.4h, v1.4h402; CHECK-NEXT: ret403 %3 = ashr <4 x i16> %0, %1404 ret <4 x i16> %3405}406 407define <8 x i16> @ashr_v8i16(<8 x i16> %0, <8 x i16> %1){408; CHECK-LABEL: ashr_v8i16:409; CHECK: // %bb.0:410; CHECK-NEXT: neg v1.8h, v1.8h411; CHECK-NEXT: sshl v0.8h, v0.8h, v1.8h412; CHECK-NEXT: ret413 %3 = ashr <8 x i16> %0, %1414 ret <8 x i16> %3415}416 417define <2 x i32> @ashr_v2i32(<2 x i32> %0, <2 x i32> %1){418; CHECK-LABEL: ashr_v2i32:419; CHECK: // %bb.0:420; CHECK-NEXT: neg v1.2s, v1.2s421; CHECK-NEXT: sshl v0.2s, v0.2s, v1.2s422; CHECK-NEXT: ret423 %3 = ashr <2 x i32> %0, %1424 ret <2 x i32> %3425}426 427define <4 x i32> @ashr_v4i32(<4 x i32> %0, <4 x i32> %1){428; CHECK-LABEL: ashr_v4i32:429; CHECK: // %bb.0:430; CHECK-NEXT: neg v1.4s, v1.4s431; CHECK-NEXT: sshl v0.4s, v0.4s, v1.4s432; CHECK-NEXT: ret433 %3 = ashr <4 x i32> %0, %1434 ret <4 x i32> %3435}436 437define <2 x i64> @ashr_v2i64(<2 x i64> %0, <2 x i64> %1){438; CHECK-LABEL: ashr_v2i64:439; CHECK: // %bb.0:440; CHECK-NEXT: neg v1.2d, v1.2d441; CHECK-NEXT: sshl v0.2d, v0.2d, v1.2d442; CHECK-NEXT: ret443 %3 = ashr <2 x i64> %0, %1444 ret <2 x i64> %3445}446 447define <8 x i8> @lshr_v8i8(<8 x i8> %0, <8 x i8> %1){448; CHECK-LABEL: lshr_v8i8:449; CHECK: // %bb.0:450; CHECK-NEXT: neg v1.8b, v1.8b451; CHECK-NEXT: ushl v0.8b, v0.8b, v1.8b452; CHECK-NEXT: ret453 %3 = lshr <8 x i8> %0, %1454 ret <8 x i8> %3455}456 457define <16 x i8> @lshr_v16i8(<16 x i8> %0, <16 x i8> %1){458; CHECK-LABEL: lshr_v16i8:459; CHECK: // %bb.0:460; CHECK-NEXT: neg v1.16b, v1.16b461; CHECK-NEXT: ushl v0.16b, v0.16b, v1.16b462; CHECK-NEXT: ret463 %3 = lshr <16 x i8> %0, %1464 ret <16 x i8> %3465}466 467define <4 x i16> @lshr_v4i16(<4 x i16> %0, <4 x i16> %1){468; CHECK-LABEL: lshr_v4i16:469; CHECK: // %bb.0:470; CHECK-NEXT: neg v1.4h, v1.4h471; CHECK-NEXT: ushl v0.4h, v0.4h, v1.4h472; CHECK-NEXT: ret473 %3 = lshr <4 x i16> %0, %1474 ret <4 x i16> %3475}476 477define <8 x i16> @lshr_v8i16(<8 x i16> %0, <8 x i16> %1){478; CHECK-LABEL: lshr_v8i16:479; CHECK: // %bb.0:480; CHECK-NEXT: neg v1.8h, v1.8h481; CHECK-NEXT: ushl v0.8h, v0.8h, v1.8h482; CHECK-NEXT: ret483 %3 = lshr <8 x i16> %0, %1484 ret <8 x i16> %3485}486 487define <2 x i32> @lshr_v2i32(<2 x i32> %0, <2 x i32> %1){488; CHECK-LABEL: lshr_v2i32:489; CHECK: // %bb.0:490; CHECK-NEXT: neg v1.2s, v1.2s491; CHECK-NEXT: ushl v0.2s, v0.2s, v1.2s492; CHECK-NEXT: ret493 %3 = lshr <2 x i32> %0, %1494 ret <2 x i32> %3495}496 497define <4 x i32> @lshr_v4i32(<4 x i32> %0, <4 x i32> %1){498; CHECK-LABEL: lshr_v4i32:499; CHECK: // %bb.0:500; CHECK-NEXT: neg v1.4s, v1.4s501; CHECK-NEXT: ushl v0.4s, v0.4s, v1.4s502; CHECK-NEXT: ret503 %3 = lshr <4 x i32> %0, %1504 ret <4 x i32> %3505}506 507define <2 x i64> @lshr_v2i64(<2 x i64> %0, <2 x i64> %1){508; CHECK-LABEL: lshr_v2i64:509; CHECK: // %bb.0:510; CHECK-NEXT: neg v1.2d, v1.2d511; CHECK-NEXT: ushl v0.2d, v0.2d, v1.2d512; CHECK-NEXT: ret513 %3 = lshr <2 x i64> %0, %1514 ret <2 x i64> %3515}516 517; ===== Vector Larger/Smaller than Legal =====518 519define <4 x i8> @shl_v4i8(<4 x i8> %0, <4 x i8> %1){520; CHECK-SD-LABEL: shl_v4i8:521; CHECK-SD: // %bb.0:522; CHECK-SD-NEXT: bic v1.4h, #255, lsl #8523; CHECK-SD-NEXT: ushl v0.4h, v0.4h, v1.4h524; CHECK-SD-NEXT: ret525;526; CHECK-GI-LABEL: shl_v4i8:527; CHECK-GI: // %bb.0:528; CHECK-GI-NEXT: uzp1 v0.8b, v0.8b, v0.8b529; CHECK-GI-NEXT: uzp1 v1.8b, v1.8b, v0.8b530; CHECK-GI-NEXT: ushl v0.8b, v0.8b, v1.8b531; CHECK-GI-NEXT: ushll v0.8h, v0.8b, #0532; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0533; CHECK-GI-NEXT: ret534 %3 = shl <4 x i8> %0, %1535 ret <4 x i8> %3536}537 538define <32 x i8> @shl_v32i8(<32 x i8> %0, <32 x i8> %1){539; CHECK-SD-LABEL: shl_v32i8:540; CHECK-SD: // %bb.0:541; CHECK-SD-NEXT: ushl v1.16b, v1.16b, v3.16b542; CHECK-SD-NEXT: ushl v0.16b, v0.16b, v2.16b543; CHECK-SD-NEXT: ret544;545; CHECK-GI-LABEL: shl_v32i8:546; CHECK-GI: // %bb.0:547; CHECK-GI-NEXT: ushl v0.16b, v0.16b, v2.16b548; CHECK-GI-NEXT: ushl v1.16b, v1.16b, v3.16b549; CHECK-GI-NEXT: ret550 %3 = shl <32 x i8> %0, %1551 ret <32 x i8> %3552}553 554define <2 x i16> @shl_v2i16(<2 x i16> %0, <2 x i16> %1){555; CHECK-SD-LABEL: shl_v2i16:556; CHECK-SD: // %bb.0:557; CHECK-SD-NEXT: movi d2, #0x00ffff0000ffff558; CHECK-SD-NEXT: and v1.8b, v1.8b, v2.8b559; CHECK-SD-NEXT: ushl v0.2s, v0.2s, v1.2s560; CHECK-SD-NEXT: ret561;562; CHECK-GI-LABEL: shl_v2i16:563; CHECK-GI: // %bb.0:564; CHECK-GI-NEXT: uzp1 v0.4h, v0.4h, v0.4h565; CHECK-GI-NEXT: uzp1 v1.4h, v1.4h, v0.4h566; CHECK-GI-NEXT: ushl v0.4h, v0.4h, v1.4h567; CHECK-GI-NEXT: ushll v0.4s, v0.4h, #0568; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0569; CHECK-GI-NEXT: ret570 %3 = shl <2 x i16> %0, %1571 ret <2 x i16> %3572}573 574define <16 x i16> @shl_v16i16(<16 x i16> %0, <16 x i16> %1){575; CHECK-SD-LABEL: shl_v16i16:576; CHECK-SD: // %bb.0:577; CHECK-SD-NEXT: ushl v1.8h, v1.8h, v3.8h578; CHECK-SD-NEXT: ushl v0.8h, v0.8h, v2.8h579; CHECK-SD-NEXT: ret580;581; CHECK-GI-LABEL: shl_v16i16:582; CHECK-GI: // %bb.0:583; CHECK-GI-NEXT: ushl v0.8h, v0.8h, v2.8h584; CHECK-GI-NEXT: ushl v1.8h, v1.8h, v3.8h585; CHECK-GI-NEXT: ret586 %3 = shl <16 x i16> %0, %1587 ret <16 x i16> %3588}589 590define <1 x i32> @shl_v1i32(<1 x i32> %0, <1 x i32> %1){591; CHECK-SD-LABEL: shl_v1i32:592; CHECK-SD: // %bb.0:593; CHECK-SD-NEXT: ushl v0.2s, v0.2s, v1.2s594; CHECK-SD-NEXT: ret595;596; CHECK-GI-LABEL: shl_v1i32:597; CHECK-GI: // %bb.0:598; CHECK-GI-NEXT: fmov w8, s0599; CHECK-GI-NEXT: fmov w9, s1600; CHECK-GI-NEXT: lsl w8, w8, w9601; CHECK-GI-NEXT: fmov s0, w8602; CHECK-GI-NEXT: ret603 %3 = shl <1 x i32> %0, %1604 ret <1 x i32> %3605}606 607define <8 x i32> @shl_v8i32(<8 x i32> %0, <8 x i32> %1){608; CHECK-SD-LABEL: shl_v8i32:609; CHECK-SD: // %bb.0:610; CHECK-SD-NEXT: ushl v1.4s, v1.4s, v3.4s611; CHECK-SD-NEXT: ushl v0.4s, v0.4s, v2.4s612; CHECK-SD-NEXT: ret613;614; CHECK-GI-LABEL: shl_v8i32:615; CHECK-GI: // %bb.0:616; CHECK-GI-NEXT: ushl v0.4s, v0.4s, v2.4s617; CHECK-GI-NEXT: ushl v1.4s, v1.4s, v3.4s618; CHECK-GI-NEXT: ret619 %3 = shl <8 x i32> %0, %1620 ret <8 x i32> %3621}622 623define <4 x i64> @shl_v4i64(<4 x i64> %0, <4 x i64> %1){624; CHECK-SD-LABEL: shl_v4i64:625; CHECK-SD: // %bb.0:626; CHECK-SD-NEXT: ushl v1.2d, v1.2d, v3.2d627; CHECK-SD-NEXT: ushl v0.2d, v0.2d, v2.2d628; CHECK-SD-NEXT: ret629;630; CHECK-GI-LABEL: shl_v4i64:631; CHECK-GI: // %bb.0:632; CHECK-GI-NEXT: ushl v0.2d, v0.2d, v2.2d633; CHECK-GI-NEXT: ushl v1.2d, v1.2d, v3.2d634; CHECK-GI-NEXT: ret635 %3 = shl <4 x i64> %0, %1636 ret <4 x i64> %3637}638 639define <2 x i128> @shl_v2i128(<2 x i128> %0, <2 x i128> %1){640; CHECK-SD-LABEL: shl_v2i128:641; CHECK-SD: // %bb.0:642; CHECK-SD-NEXT: lsr x8, x0, #1643; CHECK-SD-NEXT: mvn w9, w4644; CHECK-SD-NEXT: lsl x10, x1, x4645; CHECK-SD-NEXT: mvn w12, w6646; CHECK-SD-NEXT: lsl x11, x0, x4647; CHECK-SD-NEXT: lsl x13, x3, x6648; CHECK-SD-NEXT: lsr x8, x8, x9649; CHECK-SD-NEXT: lsr x9, x2, #1650; CHECK-SD-NEXT: tst x4, #0x40651; CHECK-SD-NEXT: csel x0, xzr, x11, ne652; CHECK-SD-NEXT: lsr x9, x9, x12653; CHECK-SD-NEXT: orr x8, x10, x8654; CHECK-SD-NEXT: lsl x10, x2, x6655; CHECK-SD-NEXT: csel x1, x11, x8, ne656; CHECK-SD-NEXT: tst x6, #0x40657; CHECK-SD-NEXT: orr x8, x13, x9658; CHECK-SD-NEXT: csel x2, xzr, x10, ne659; CHECK-SD-NEXT: csel x3, x10, x8, ne660; CHECK-SD-NEXT: ret661;662; CHECK-GI-LABEL: shl_v2i128:663; CHECK-GI: // %bb.0:664; CHECK-GI-NEXT: mov w8, #64 // =0x40665; CHECK-GI-NEXT: sub x10, x4, #64666; CHECK-GI-NEXT: lsl x11, x1, x4667; CHECK-GI-NEXT: sub x9, x8, x4668; CHECK-GI-NEXT: lsl x10, x0, x10669; CHECK-GI-NEXT: lsl x12, x0, x4670; CHECK-GI-NEXT: lsr x9, x0, x9671; CHECK-GI-NEXT: cmp x4, #64672; CHECK-GI-NEXT: sub x8, x8, x6673; CHECK-GI-NEXT: lsr x8, x2, x8674; CHECK-GI-NEXT: csel x0, x12, xzr, lo675; CHECK-GI-NEXT: lsl x12, x2, x6676; CHECK-GI-NEXT: orr x9, x9, x11677; CHECK-GI-NEXT: lsl x11, x3, x6678; CHECK-GI-NEXT: csel x9, x9, x10, lo679; CHECK-GI-NEXT: sub x10, x6, #64680; CHECK-GI-NEXT: cmp x4, #0681; CHECK-GI-NEXT: lsl x10, x2, x10682; CHECK-GI-NEXT: csel x1, x1, x9, eq683; CHECK-GI-NEXT: orr x8, x8, x11684; CHECK-GI-NEXT: cmp x6, #64685; CHECK-GI-NEXT: csel x2, x12, xzr, lo686; CHECK-GI-NEXT: csel x8, x8, x10, lo687; CHECK-GI-NEXT: cmp x6, #0688; CHECK-GI-NEXT: csel x3, x3, x8, eq689; CHECK-GI-NEXT: ret690 %3 = shl <2 x i128> %0, %1691 ret <2 x i128> %3692}693 694define <4 x i8> @ashr_v4i8(<4 x i8> %0, <4 x i8> %1){695; CHECK-SD-LABEL: ashr_v4i8:696; CHECK-SD: // %bb.0:697; CHECK-SD-NEXT: shl v0.4h, v0.4h, #8698; CHECK-SD-NEXT: bic v1.4h, #255, lsl #8699; CHECK-SD-NEXT: sshr v0.4h, v0.4h, #8700; CHECK-SD-NEXT: neg v1.4h, v1.4h701; CHECK-SD-NEXT: sshl v0.4h, v0.4h, v1.4h702; CHECK-SD-NEXT: ret703;704; CHECK-GI-LABEL: ashr_v4i8:705; CHECK-GI: // %bb.0:706; CHECK-GI-NEXT: uzp1 v1.8b, v1.8b, v0.8b707; CHECK-GI-NEXT: uzp1 v0.8b, v0.8b, v0.8b708; CHECK-GI-NEXT: neg v1.8b, v1.8b709; CHECK-GI-NEXT: sshl v0.8b, v0.8b, v1.8b710; CHECK-GI-NEXT: ushll v0.8h, v0.8b, #0711; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0712; CHECK-GI-NEXT: ret713 %3 = ashr <4 x i8> %0, %1714 ret <4 x i8> %3715}716 717define <32 x i8> @ashr_v32i8(<32 x i8> %0, <32 x i8> %1){718; CHECK-LABEL: ashr_v32i8:719; CHECK: // %bb.0:720; CHECK-NEXT: neg v2.16b, v2.16b721; CHECK-NEXT: neg v3.16b, v3.16b722; CHECK-NEXT: sshl v0.16b, v0.16b, v2.16b723; CHECK-NEXT: sshl v1.16b, v1.16b, v3.16b724; CHECK-NEXT: ret725 %3 = ashr <32 x i8> %0, %1726 ret <32 x i8> %3727}728 729define <2 x i16> @ashr_v2i16(<2 x i16> %0, <2 x i16> %1){730; CHECK-SD-LABEL: ashr_v2i16:731; CHECK-SD: // %bb.0:732; CHECK-SD-NEXT: movi d2, #0x00ffff0000ffff733; CHECK-SD-NEXT: shl v0.2s, v0.2s, #16734; CHECK-SD-NEXT: sshr v0.2s, v0.2s, #16735; CHECK-SD-NEXT: and v1.8b, v1.8b, v2.8b736; CHECK-SD-NEXT: neg v1.2s, v1.2s737; CHECK-SD-NEXT: sshl v0.2s, v0.2s, v1.2s738; CHECK-SD-NEXT: ret739;740; CHECK-GI-LABEL: ashr_v2i16:741; CHECK-GI: // %bb.0:742; CHECK-GI-NEXT: uzp1 v1.4h, v1.4h, v0.4h743; CHECK-GI-NEXT: uzp1 v0.4h, v0.4h, v0.4h744; CHECK-GI-NEXT: neg v1.4h, v1.4h745; CHECK-GI-NEXT: sshl v0.4h, v0.4h, v1.4h746; CHECK-GI-NEXT: ushll v0.4s, v0.4h, #0747; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0748; CHECK-GI-NEXT: ret749 %3 = ashr <2 x i16> %0, %1750 ret <2 x i16> %3751}752 753define <16 x i16> @ashr_v16i16(<16 x i16> %0, <16 x i16> %1){754; CHECK-LABEL: ashr_v16i16:755; CHECK: // %bb.0:756; CHECK-NEXT: neg v2.8h, v2.8h757; CHECK-NEXT: neg v3.8h, v3.8h758; CHECK-NEXT: sshl v0.8h, v0.8h, v2.8h759; CHECK-NEXT: sshl v1.8h, v1.8h, v3.8h760; CHECK-NEXT: ret761 %3 = ashr <16 x i16> %0, %1762 ret <16 x i16> %3763}764 765define <1 x i32> @ashr_v1i32(<1 x i32> %0, <1 x i32> %1){766; CHECK-SD-LABEL: ashr_v1i32:767; CHECK-SD: // %bb.0:768; CHECK-SD-NEXT: neg v1.2s, v1.2s769; CHECK-SD-NEXT: sshl v0.2s, v0.2s, v1.2s770; CHECK-SD-NEXT: ret771;772; CHECK-GI-LABEL: ashr_v1i32:773; CHECK-GI: // %bb.0:774; CHECK-GI-NEXT: fmov w8, s0775; CHECK-GI-NEXT: fmov w9, s1776; CHECK-GI-NEXT: asr w8, w8, w9777; CHECK-GI-NEXT: fmov s0, w8778; CHECK-GI-NEXT: ret779 %3 = ashr <1 x i32> %0, %1780 ret <1 x i32> %3781}782 783define <8 x i32> @ashr_v8i32(<8 x i32> %0, <8 x i32> %1){784; CHECK-LABEL: ashr_v8i32:785; CHECK: // %bb.0:786; CHECK-NEXT: neg v2.4s, v2.4s787; CHECK-NEXT: neg v3.4s, v3.4s788; CHECK-NEXT: sshl v0.4s, v0.4s, v2.4s789; CHECK-NEXT: sshl v1.4s, v1.4s, v3.4s790; CHECK-NEXT: ret791 %3 = ashr <8 x i32> %0, %1792 ret <8 x i32> %3793}794 795define <4 x i64> @ashr_v4i64(<4 x i64> %0, <4 x i64> %1){796; CHECK-LABEL: ashr_v4i64:797; CHECK: // %bb.0:798; CHECK-NEXT: neg v2.2d, v2.2d799; CHECK-NEXT: neg v3.2d, v3.2d800; CHECK-NEXT: sshl v0.2d, v0.2d, v2.2d801; CHECK-NEXT: sshl v1.2d, v1.2d, v3.2d802; CHECK-NEXT: ret803 %3 = ashr <4 x i64> %0, %1804 ret <4 x i64> %3805}806 807define <2 x i128> @ashr_v2i128(<2 x i128> %0, <2 x i128> %1){808; CHECK-SD-LABEL: ashr_v2i128:809; CHECK-SD: // %bb.0:810; CHECK-SD-NEXT: lsl x8, x1, #1811; CHECK-SD-NEXT: mvn w9, w4812; CHECK-SD-NEXT: lsl x10, x3, #1813; CHECK-SD-NEXT: lsr x11, x0, x4814; CHECK-SD-NEXT: lsr x12, x2, x6815; CHECK-SD-NEXT: asr x13, x1, #63816; CHECK-SD-NEXT: lsl x8, x8, x9817; CHECK-SD-NEXT: mvn w9, w6818; CHECK-SD-NEXT: tst x4, #0x40819; CHECK-SD-NEXT: lsl x9, x10, x9820; CHECK-SD-NEXT: asr x10, x1, x4821; CHECK-SD-NEXT: asr x14, x3, #63822; CHECK-SD-NEXT: orr x8, x8, x11823; CHECK-SD-NEXT: asr x11, x3, x6824; CHECK-SD-NEXT: csel x0, x10, x8, ne825; CHECK-SD-NEXT: orr x8, x9, x12826; CHECK-SD-NEXT: csel x1, x13, x10, ne827; CHECK-SD-NEXT: tst x6, #0x40828; CHECK-SD-NEXT: csel x2, x11, x8, ne829; CHECK-SD-NEXT: csel x3, x14, x11, ne830; CHECK-SD-NEXT: ret831;832; CHECK-GI-LABEL: ashr_v2i128:833; CHECK-GI: // %bb.0:834; CHECK-GI-NEXT: mov w8, #64 // =0x40835; CHECK-GI-NEXT: sub x10, x4, #64836; CHECK-GI-NEXT: lsr x11, x0, x4837; CHECK-GI-NEXT: sub x9, x8, x4838; CHECK-GI-NEXT: asr x10, x1, x10839; CHECK-GI-NEXT: cmp x4, #64840; CHECK-GI-NEXT: lsl x9, x1, x9841; CHECK-GI-NEXT: sub x8, x8, x6842; CHECK-GI-NEXT: asr x12, x1, x4843; CHECK-GI-NEXT: lsl x8, x3, x8844; CHECK-GI-NEXT: orr x9, x11, x9845; CHECK-GI-NEXT: asr x11, x1, #63846; CHECK-GI-NEXT: csel x9, x9, x10, lo847; CHECK-GI-NEXT: cmp x4, #0848; CHECK-GI-NEXT: lsr x10, x2, x6849; CHECK-GI-NEXT: csel x0, x0, x9, eq850; CHECK-GI-NEXT: sub x9, x6, #64851; CHECK-GI-NEXT: cmp x4, #64852; CHECK-GI-NEXT: asr x9, x3, x9853; CHECK-GI-NEXT: csel x1, x12, x11, lo854; CHECK-GI-NEXT: orr x8, x10, x8855; CHECK-GI-NEXT: cmp x6, #64856; CHECK-GI-NEXT: asr x11, x3, x6857; CHECK-GI-NEXT: asr x10, x3, #63858; CHECK-GI-NEXT: csel x8, x8, x9, lo859; CHECK-GI-NEXT: cmp x6, #0860; CHECK-GI-NEXT: csel x2, x2, x8, eq861; CHECK-GI-NEXT: cmp x6, #64862; CHECK-GI-NEXT: csel x3, x11, x10, lo863; CHECK-GI-NEXT: ret864 %3 = ashr <2 x i128> %0, %1865 ret <2 x i128> %3866}867 868define <4 x i8> @lshr_v4i8(<4 x i8> %0, <4 x i8> %1){869; CHECK-SD-LABEL: lshr_v4i8:870; CHECK-SD: // %bb.0:871; CHECK-SD-NEXT: bic v1.4h, #255, lsl #8872; CHECK-SD-NEXT: bic v0.4h, #255, lsl #8873; CHECK-SD-NEXT: neg v1.4h, v1.4h874; CHECK-SD-NEXT: ushl v0.4h, v0.4h, v1.4h875; CHECK-SD-NEXT: ret876;877; CHECK-GI-LABEL: lshr_v4i8:878; CHECK-GI: // %bb.0:879; CHECK-GI-NEXT: uzp1 v1.8b, v1.8b, v0.8b880; CHECK-GI-NEXT: uzp1 v0.8b, v0.8b, v0.8b881; CHECK-GI-NEXT: neg v1.8b, v1.8b882; CHECK-GI-NEXT: ushl v0.8b, v0.8b, v1.8b883; CHECK-GI-NEXT: ushll v0.8h, v0.8b, #0884; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0885; CHECK-GI-NEXT: ret886 %3 = lshr <4 x i8> %0, %1887 ret <4 x i8> %3888}889 890define <32 x i8> @lshr_v32i8(<32 x i8> %0, <32 x i8> %1){891; CHECK-LABEL: lshr_v32i8:892; CHECK: // %bb.0:893; CHECK-NEXT: neg v2.16b, v2.16b894; CHECK-NEXT: neg v3.16b, v3.16b895; CHECK-NEXT: ushl v0.16b, v0.16b, v2.16b896; CHECK-NEXT: ushl v1.16b, v1.16b, v3.16b897; CHECK-NEXT: ret898 %3 = lshr <32 x i8> %0, %1899 ret <32 x i8> %3900}901 902define <2 x i16> @lshr_v2i16(<2 x i16> %0, <2 x i16> %1){903; CHECK-SD-LABEL: lshr_v2i16:904; CHECK-SD: // %bb.0:905; CHECK-SD-NEXT: movi d2, #0x00ffff0000ffff906; CHECK-SD-NEXT: and v1.8b, v1.8b, v2.8b907; CHECK-SD-NEXT: and v0.8b, v0.8b, v2.8b908; CHECK-SD-NEXT: neg v1.2s, v1.2s909; CHECK-SD-NEXT: ushl v0.2s, v0.2s, v1.2s910; CHECK-SD-NEXT: ret911;912; CHECK-GI-LABEL: lshr_v2i16:913; CHECK-GI: // %bb.0:914; CHECK-GI-NEXT: uzp1 v1.4h, v1.4h, v0.4h915; CHECK-GI-NEXT: uzp1 v0.4h, v0.4h, v0.4h916; CHECK-GI-NEXT: neg v1.4h, v1.4h917; CHECK-GI-NEXT: ushl v0.4h, v0.4h, v1.4h918; CHECK-GI-NEXT: ushll v0.4s, v0.4h, #0919; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0920; CHECK-GI-NEXT: ret921 %3 = lshr <2 x i16> %0, %1922 ret <2 x i16> %3923}924 925define <16 x i16> @lshr_v16i16(<16 x i16> %0, <16 x i16> %1){926; CHECK-LABEL: lshr_v16i16:927; CHECK: // %bb.0:928; CHECK-NEXT: neg v2.8h, v2.8h929; CHECK-NEXT: neg v3.8h, v3.8h930; CHECK-NEXT: ushl v0.8h, v0.8h, v2.8h931; CHECK-NEXT: ushl v1.8h, v1.8h, v3.8h932; CHECK-NEXT: ret933 %3 = lshr <16 x i16> %0, %1934 ret <16 x i16> %3935}936 937define <1 x i32> @lshr_v1i32(<1 x i32> %0, <1 x i32> %1){938; CHECK-SD-LABEL: lshr_v1i32:939; CHECK-SD: // %bb.0:940; CHECK-SD-NEXT: neg v1.2s, v1.2s941; CHECK-SD-NEXT: ushl v0.2s, v0.2s, v1.2s942; CHECK-SD-NEXT: ret943;944; CHECK-GI-LABEL: lshr_v1i32:945; CHECK-GI: // %bb.0:946; CHECK-GI-NEXT: fmov w8, s0947; CHECK-GI-NEXT: fmov w9, s1948; CHECK-GI-NEXT: lsr w8, w8, w9949; CHECK-GI-NEXT: fmov s0, w8950; CHECK-GI-NEXT: ret951 %3 = lshr <1 x i32> %0, %1952 ret <1 x i32> %3953}954 955define <8 x i32> @lshr_v8i32(<8 x i32> %0, <8 x i32> %1){956; CHECK-LABEL: lshr_v8i32:957; CHECK: // %bb.0:958; CHECK-NEXT: neg v2.4s, v2.4s959; CHECK-NEXT: neg v3.4s, v3.4s960; CHECK-NEXT: ushl v0.4s, v0.4s, v2.4s961; CHECK-NEXT: ushl v1.4s, v1.4s, v3.4s962; CHECK-NEXT: ret963 %3 = lshr <8 x i32> %0, %1964 ret <8 x i32> %3965}966 967define <4 x i64> @lshr_v4i64(<4 x i64> %0, <4 x i64> %1){968; CHECK-LABEL: lshr_v4i64:969; CHECK: // %bb.0:970; CHECK-NEXT: neg v2.2d, v2.2d971; CHECK-NEXT: neg v3.2d, v3.2d972; CHECK-NEXT: ushl v0.2d, v0.2d, v2.2d973; CHECK-NEXT: ushl v1.2d, v1.2d, v3.2d974; CHECK-NEXT: ret975 %3 = lshr <4 x i64> %0, %1976 ret <4 x i64> %3977}978 979define <2 x i128> @lshr_v2i128(<2 x i128> %0, <2 x i128> %1){980; CHECK-SD-LABEL: lshr_v2i128:981; CHECK-SD: // %bb.0:982; CHECK-SD-NEXT: lsl x8, x1, #1983; CHECK-SD-NEXT: mvn w9, w4984; CHECK-SD-NEXT: lsr x10, x0, x4985; CHECK-SD-NEXT: mvn w12, w6986; CHECK-SD-NEXT: lsr x11, x1, x4987; CHECK-SD-NEXT: lsr x13, x2, x6988; CHECK-SD-NEXT: lsl x8, x8, x9989; CHECK-SD-NEXT: lsl x9, x3, #1990; CHECK-SD-NEXT: tst x4, #0x40991; CHECK-SD-NEXT: csel x1, xzr, x11, ne992; CHECK-SD-NEXT: lsl x9, x9, x12993; CHECK-SD-NEXT: orr x8, x8, x10994; CHECK-SD-NEXT: lsr x10, x3, x6995; CHECK-SD-NEXT: csel x0, x11, x8, ne996; CHECK-SD-NEXT: tst x6, #0x40997; CHECK-SD-NEXT: orr x8, x9, x13998; CHECK-SD-NEXT: csel x3, xzr, x10, ne999; CHECK-SD-NEXT: csel x2, x10, x8, ne1000; CHECK-SD-NEXT: ret1001;1002; CHECK-GI-LABEL: lshr_v2i128:1003; CHECK-GI: // %bb.0:1004; CHECK-GI-NEXT: mov w8, #64 // =0x401005; CHECK-GI-NEXT: sub x10, x4, #641006; CHECK-GI-NEXT: lsr x11, x0, x41007; CHECK-GI-NEXT: sub x9, x8, x41008; CHECK-GI-NEXT: lsr x10, x1, x101009; CHECK-GI-NEXT: cmp x4, #641010; CHECK-GI-NEXT: lsl x9, x1, x91011; CHECK-GI-NEXT: sub x8, x8, x61012; CHECK-GI-NEXT: lsr x12, x1, x41013; CHECK-GI-NEXT: lsl x8, x3, x81014; CHECK-GI-NEXT: orr x9, x11, x91015; CHECK-GI-NEXT: lsr x11, x2, x61016; CHECK-GI-NEXT: csel x9, x9, x10, lo1017; CHECK-GI-NEXT: cmp x4, #01018; CHECK-GI-NEXT: sub x10, x6, #641019; CHECK-GI-NEXT: csel x0, x0, x9, eq1020; CHECK-GI-NEXT: cmp x4, #641021; CHECK-GI-NEXT: lsr x9, x3, x101022; CHECK-GI-NEXT: csel x1, x12, xzr, lo1023; CHECK-GI-NEXT: orr x8, x11, x81024; CHECK-GI-NEXT: cmp x6, #641025; CHECK-GI-NEXT: lsr x10, x3, x61026; CHECK-GI-NEXT: csel x8, x8, x9, lo1027; CHECK-GI-NEXT: cmp x6, #01028; CHECK-GI-NEXT: csel x2, x2, x8, eq1029; CHECK-GI-NEXT: cmp x6, #641030; CHECK-GI-NEXT: csel x3, x10, xzr, lo1031; CHECK-GI-NEXT: ret1032 %3 = lshr <2 x i128> %0, %11033 ret <2 x i128> %31034}1035 1036; ===== Vector with Non-Pow 2 Width =====1037 1038define <3 x i8> @shl_v3i8(<3 x i8> %0, <3 x i8> %1){1039; CHECK-SD-LABEL: shl_v3i8:1040; CHECK-SD: // %bb.0:1041; CHECK-SD-NEXT: fmov s0, w31042; CHECK-SD-NEXT: fmov s1, w01043; CHECK-SD-NEXT: mov v0.h[1], w41044; CHECK-SD-NEXT: mov v1.h[1], w11045; CHECK-SD-NEXT: mov v0.h[2], w51046; CHECK-SD-NEXT: mov v1.h[2], w21047; CHECK-SD-NEXT: bic v0.4h, #255, lsl #81048; CHECK-SD-NEXT: ushl v0.4h, v1.4h, v0.4h1049; CHECK-SD-NEXT: umov w0, v0.h[0]1050; CHECK-SD-NEXT: umov w1, v0.h[1]1051; CHECK-SD-NEXT: umov w2, v0.h[2]1052; CHECK-SD-NEXT: ret1053;1054; CHECK-GI-LABEL: shl_v3i8:1055; CHECK-GI: // %bb.0:1056; CHECK-GI-NEXT: fmov s0, w01057; CHECK-GI-NEXT: fmov s1, w31058; CHECK-GI-NEXT: mov v0.b[1], w11059; CHECK-GI-NEXT: mov v1.b[1], w41060; CHECK-GI-NEXT: mov v0.b[2], w21061; CHECK-GI-NEXT: mov v1.b[2], w51062; CHECK-GI-NEXT: ushl v0.8b, v0.8b, v1.8b1063; CHECK-GI-NEXT: umov w0, v0.b[0]1064; CHECK-GI-NEXT: umov w1, v0.b[1]1065; CHECK-GI-NEXT: umov w2, v0.b[2]1066; CHECK-GI-NEXT: ret1067 %3 = shl <3 x i8> %0, %11068 ret <3 x i8> %31069}1070 1071define <7 x i8> @shl_v7i8(<7 x i8> %0, <7 x i8> %1){1072; CHECK-LABEL: shl_v7i8:1073; CHECK: // %bb.0:1074; CHECK-NEXT: ushl v0.8b, v0.8b, v1.8b1075; CHECK-NEXT: ret1076 %3 = shl <7 x i8> %0, %11077 ret <7 x i8> %31078}1079 1080define <3 x i16> @shl_v3i16(<3 x i16> %0, <3 x i16> %1){1081; CHECK-LABEL: shl_v3i16:1082; CHECK: // %bb.0:1083; CHECK-NEXT: ushl v0.4h, v0.4h, v1.4h1084; CHECK-NEXT: ret1085 %3 = shl <3 x i16> %0, %11086 ret <3 x i16> %31087}1088 1089define <7 x i16> @shl_v7i16(<7 x i16> %0, <7 x i16> %1){1090; CHECK-LABEL: shl_v7i16:1091; CHECK: // %bb.0:1092; CHECK-NEXT: ushl v0.8h, v0.8h, v1.8h1093; CHECK-NEXT: ret1094 %3 = shl <7 x i16> %0, %11095 ret <7 x i16> %31096}1097 1098define <3 x i32> @shl_v3i32(<3 x i32> %0, <3 x i32> %1){1099; CHECK-LABEL: shl_v3i32:1100; CHECK: // %bb.0:1101; CHECK-NEXT: ushl v0.4s, v0.4s, v1.4s1102; CHECK-NEXT: ret1103 %3 = shl <3 x i32> %0, %11104 ret <3 x i32> %31105}1106 1107define <3 x i8> @ashr_v3i8(<3 x i8> %0, <3 x i8> %1){1108; CHECK-SD-LABEL: ashr_v3i8:1109; CHECK-SD: // %bb.0:1110; CHECK-SD-NEXT: fmov s0, w01111; CHECK-SD-NEXT: fmov s1, w31112; CHECK-SD-NEXT: mov v0.h[1], w11113; CHECK-SD-NEXT: mov v1.h[1], w41114; CHECK-SD-NEXT: mov v0.h[2], w21115; CHECK-SD-NEXT: mov v1.h[2], w51116; CHECK-SD-NEXT: shl v0.4h, v0.4h, #81117; CHECK-SD-NEXT: bic v1.4h, #255, lsl #81118; CHECK-SD-NEXT: sshr v0.4h, v0.4h, #81119; CHECK-SD-NEXT: neg v1.4h, v1.4h1120; CHECK-SD-NEXT: sshl v0.4h, v0.4h, v1.4h1121; CHECK-SD-NEXT: umov w0, v0.h[0]1122; CHECK-SD-NEXT: umov w1, v0.h[1]1123; CHECK-SD-NEXT: umov w2, v0.h[2]1124; CHECK-SD-NEXT: ret1125;1126; CHECK-GI-LABEL: ashr_v3i8:1127; CHECK-GI: // %bb.0:1128; CHECK-GI-NEXT: fmov s0, w31129; CHECK-GI-NEXT: fmov s1, w01130; CHECK-GI-NEXT: mov v0.b[1], w41131; CHECK-GI-NEXT: mov v1.b[1], w11132; CHECK-GI-NEXT: mov v0.b[2], w51133; CHECK-GI-NEXT: mov v1.b[2], w21134; CHECK-GI-NEXT: neg v0.8b, v0.8b1135; CHECK-GI-NEXT: sshl v0.8b, v1.8b, v0.8b1136; CHECK-GI-NEXT: umov w0, v0.b[0]1137; CHECK-GI-NEXT: umov w1, v0.b[1]1138; CHECK-GI-NEXT: umov w2, v0.b[2]1139; CHECK-GI-NEXT: ret1140 %3 = ashr <3 x i8> %0, %11141 ret <3 x i8> %31142}1143 1144define <7 x i8> @ashr_v7i8(<7 x i8> %0, <7 x i8> %1){1145; CHECK-LABEL: ashr_v7i8:1146; CHECK: // %bb.0:1147; CHECK-NEXT: neg v1.8b, v1.8b1148; CHECK-NEXT: sshl v0.8b, v0.8b, v1.8b1149; CHECK-NEXT: ret1150 %3 = ashr <7 x i8> %0, %11151 ret <7 x i8> %31152}1153 1154define <3 x i16> @ashr_v3i16(<3 x i16> %0, <3 x i16> %1){1155; CHECK-LABEL: ashr_v3i16:1156; CHECK: // %bb.0:1157; CHECK-NEXT: neg v1.4h, v1.4h1158; CHECK-NEXT: sshl v0.4h, v0.4h, v1.4h1159; CHECK-NEXT: ret1160 %3 = ashr <3 x i16> %0, %11161 ret <3 x i16> %31162}1163 1164define <7 x i16> @ashr_v7i16(<7 x i16> %0, <7 x i16> %1){1165; CHECK-LABEL: ashr_v7i16:1166; CHECK: // %bb.0:1167; CHECK-NEXT: neg v1.8h, v1.8h1168; CHECK-NEXT: sshl v0.8h, v0.8h, v1.8h1169; CHECK-NEXT: ret1170 %3 = ashr <7 x i16> %0, %11171 ret <7 x i16> %31172}1173 1174define <3 x i32> @ashr_v3i32(<3 x i32> %0, <3 x i32> %1){1175; CHECK-LABEL: ashr_v3i32:1176; CHECK: // %bb.0:1177; CHECK-NEXT: neg v1.4s, v1.4s1178; CHECK-NEXT: sshl v0.4s, v0.4s, v1.4s1179; CHECK-NEXT: ret1180 %3 = ashr <3 x i32> %0, %11181 ret <3 x i32> %31182}1183 1184define <3 x i8> @lshr_v3i8(<3 x i8> %0, <3 x i8> %1){1185; CHECK-SD-LABEL: lshr_v3i8:1186; CHECK-SD: // %bb.0:1187; CHECK-SD-NEXT: fmov s0, w31188; CHECK-SD-NEXT: fmov s1, w01189; CHECK-SD-NEXT: mov v0.h[1], w41190; CHECK-SD-NEXT: mov v1.h[1], w11191; CHECK-SD-NEXT: mov v0.h[2], w51192; CHECK-SD-NEXT: mov v1.h[2], w21193; CHECK-SD-NEXT: bic v0.4h, #255, lsl #81194; CHECK-SD-NEXT: bic v1.4h, #255, lsl #81195; CHECK-SD-NEXT: neg v0.4h, v0.4h1196; CHECK-SD-NEXT: ushl v0.4h, v1.4h, v0.4h1197; CHECK-SD-NEXT: umov w0, v0.h[0]1198; CHECK-SD-NEXT: umov w1, v0.h[1]1199; CHECK-SD-NEXT: umov w2, v0.h[2]1200; CHECK-SD-NEXT: ret1201;1202; CHECK-GI-LABEL: lshr_v3i8:1203; CHECK-GI: // %bb.0:1204; CHECK-GI-NEXT: fmov s0, w31205; CHECK-GI-NEXT: fmov s1, w01206; CHECK-GI-NEXT: mov v0.b[1], w41207; CHECK-GI-NEXT: mov v1.b[1], w11208; CHECK-GI-NEXT: mov v0.b[2], w51209; CHECK-GI-NEXT: mov v1.b[2], w21210; CHECK-GI-NEXT: neg v0.8b, v0.8b1211; CHECK-GI-NEXT: ushl v0.8b, v1.8b, v0.8b1212; CHECK-GI-NEXT: umov w0, v0.b[0]1213; CHECK-GI-NEXT: umov w1, v0.b[1]1214; CHECK-GI-NEXT: umov w2, v0.b[2]1215; CHECK-GI-NEXT: ret1216 %3 = lshr <3 x i8> %0, %11217 ret <3 x i8> %31218}1219 1220define <7 x i8> @lshr_v7i8(<7 x i8> %0, <7 x i8> %1){1221; CHECK-LABEL: lshr_v7i8:1222; CHECK: // %bb.0:1223; CHECK-NEXT: neg v1.8b, v1.8b1224; CHECK-NEXT: ushl v0.8b, v0.8b, v1.8b1225; CHECK-NEXT: ret1226 %3 = lshr <7 x i8> %0, %11227 ret <7 x i8> %31228}1229 1230define <3 x i16> @lshr_v3i16(<3 x i16> %0, <3 x i16> %1){1231; CHECK-LABEL: lshr_v3i16:1232; CHECK: // %bb.0:1233; CHECK-NEXT: neg v1.4h, v1.4h1234; CHECK-NEXT: ushl v0.4h, v0.4h, v1.4h1235; CHECK-NEXT: ret1236 %3 = lshr <3 x i16> %0, %11237 ret <3 x i16> %31238}1239 1240define <7 x i16> @lshr_v7i16(<7 x i16> %0, <7 x i16> %1){1241; CHECK-LABEL: lshr_v7i16:1242; CHECK: // %bb.0:1243; CHECK-NEXT: neg v1.8h, v1.8h1244; CHECK-NEXT: ushl v0.8h, v0.8h, v1.8h1245; CHECK-NEXT: ret1246 %3 = lshr <7 x i16> %0, %11247 ret <7 x i16> %31248}1249 1250define <3 x i32> @lshr_v3i32(<3 x i32> %0, <3 x i32> %1){1251; CHECK-LABEL: lshr_v3i32:1252; CHECK: // %bb.0:1253; CHECK-NEXT: neg v1.4s, v1.4s1254; CHECK-NEXT: ushl v0.4s, v0.4s, v1.4s1255; CHECK-NEXT: ret1256 %3 = lshr <3 x i32> %0, %11257 ret <3 x i32> %31258}1259 1260; TODO:1261; ===== Vector with Odd Element Sizes =====1262