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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s3 4; logic shift reg pattern: and5; already optimized by another pattern6 7define i64 @and_shiftedreg_from_and(i64 %a, i64 %b) {8; CHECK-LABEL: and_shiftedreg_from_and:9; CHECK: // %bb.0:10; CHECK-NEXT: and x8, x1, x0, asr #2311; CHECK-NEXT: and x0, x8, #0xffffffffff00000012; CHECK-NEXT: ret13 %ashr = ashr i64 %a, 2314 %and = and i64 %ashr, -1677721615 %r = and i64 %b, %and16 ret i64 %r17}18 19; TODO: logic shift reg pattern: bic20 21define i64 @bic_shiftedreg_from_and(i64 %a, i64 %b) {22; CHECK-LABEL: bic_shiftedreg_from_and:23; CHECK: // %bb.0:24; CHECK-NEXT: mov w8, #16777215 // =0xffffff25; CHECK-NEXT: orn x8, x8, x0, asr #2326; CHECK-NEXT: and x0, x1, x827; CHECK-NEXT: ret28 %ashr = ashr i64 %a, 2329 %and = and i64 %ashr, -1677721630 %not = xor i64 %and, -131 %r = and i64 %b, %not32 ret i64 %r33}34 35; logic shift reg pattern: eon36 37define i64 @eon_shiftedreg_from_and(i64 %a, i64 %b) {38; CHECK-LABEL: eon_shiftedreg_from_and:39; CHECK: // %bb.0:40; CHECK-NEXT: lsr x8, x0, #1741; CHECK-NEXT: eon x0, x1, x8, lsl #5342; CHECK-NEXT: ret43 %shl = shl i64 %a, 3644 %and = and i64 %shl, -900719925474099245 %xor = xor i64 %and, -146 %r = xor i64 %b, %xor47 ret i64 %r48}49 50; logic shift reg pattern: eor51 52define i64 @eor_shiftedreg_from_and(i64 %a, i64 %b) {53; CHECK-LABEL: eor_shiftedreg_from_and:54; CHECK: // %bb.0:55; CHECK-NEXT: lsr x8, x0, #4756; CHECK-NEXT: eor x0, x1, x8, lsl #2457; CHECK-NEXT: ret58 %lshr = lshr i64 %a, 2359 %and = and i64 %lshr, 219900647833660 %or = xor i64 %and, %b61 ret i64 %or62}63 64; logic shift reg pattern: mvn65; already optimized by another pattern66 67define i64 @mvn_shiftedreg_from_and(i64 %a) {68; CHECK-LABEL: mvn_shiftedreg_from_and:69; CHECK: // %bb.0:70; CHECK-NEXT: mov x8, #9007199254740991 // =0x1fffffffffffff71; CHECK-NEXT: orn x0, x8, x0, lsl #3672; CHECK-NEXT: ret73 %shl = shl i64 %a, 3674 %and = and i64 %shl, -900719925474099275 %xor = xor i64 %and, -176 ret i64 %xor77}78 79; logic shift reg pattern: orn80; already optimized by another pattern81 82define i64 @orn_shiftedreg_from_and(i64 %a, i64 %b) {83; CHECK-LABEL: orn_shiftedreg_from_and:84; CHECK: // %bb.0:85; CHECK-NEXT: orn x8, x1, x0, lsr #2386; CHECK-NEXT: orr x0, x8, #0xfffffe0000ffffff87; CHECK-NEXT: ret88 %lshr = lshr i64 %a, 2389 %and = and i64 %lshr, 219900647833690 %not = xor i64 %and, -191 %or = or i64 %not, %b92 ret i64 %or93}94 95; logic shift reg pattern: orr96; srl constant bitwidth == (lowbits + masklen + shiftamt)97 98define i64 @orr_shiftedreg_from_and(i64 %a, i64 %b) {99; CHECK-LABEL: orr_shiftedreg_from_and:100; CHECK: // %bb.0:101; CHECK-NEXT: lsr x8, x0, #47102; CHECK-NEXT: orr x0, x1, x8, lsl #24103; CHECK-NEXT: ret104 %lshr = lshr i64 %a, 23105 %and = and i64 %lshr, 2199006478336 ; 0x1ffff000000106 %or = or i64 %and, %b107 ret i64 %or108}109 110; logic shift reg pattern: orr111; srl constant bitwidth < (lowbits + masklen + shiftamt)112 113define i64 @orr_shiftedreg_from_and_mask2(i64 %a, i64 %b) {114; CHECK-LABEL: orr_shiftedreg_from_and_mask2:115; CHECK: // %bb.0:116; CHECK-NEXT: lsr x8, x0, #47117; CHECK-NEXT: orr x0, x1, x8, lsl #24118; CHECK-NEXT: ret119 %lshr = lshr i64 %a, 23120 %and = and i64 %lshr, 4398029733888 ; 0x3ffff000000121 %or = or i64 %and, %b122 ret i64 %or123}124 125 126; arithmetic shift reg pattern: add127 128define i32 @add_shiftedreg_from_and(i32 %a, i32 %b) {129; CHECK-LABEL: add_shiftedreg_from_and:130; CHECK: // %bb.0:131; CHECK-NEXT: asr w8, w0, #27132; CHECK-NEXT: add w0, w1, w8, lsl #24133; CHECK-NEXT: ret134 %ashr = ashr i32 %a, 3135 %and = and i32 %ashr, -16777216136 %add = add i32 %and, %b137 ret i32 %add138}139 140; arithmetic shift reg pattern: sub141 142define i64 @sub_shiftedreg_from_and_shl(i64 %a, i64 %b) {143; CHECK-LABEL: sub_shiftedreg_from_and_shl:144; CHECK: // %bb.0:145; CHECK-NEXT: lsr x8, x0, #17146; CHECK-NEXT: sub x0, x1, x8, lsl #53147; CHECK-NEXT: ret148 %shl = shl i64 %a, 36149 %and = and i64 %shl, -9007199254740992150 %sub = sub i64 %b, %and151 ret i64 %sub152}153 154; negative test: type is not i32 or i64155 156define <2 x i32> @shiftedreg_from_and_negative_type(<2 x i32> %a, <2 x i32> %b) {157; CHECK-LABEL: shiftedreg_from_and_negative_type:158; CHECK: // %bb.0:159; CHECK-NEXT: shl v0.2s, v0.2s, #2160; CHECK-NEXT: bic v0.2s, #28161; CHECK-NEXT: sub v0.2s, v1.2s, v0.2s162; CHECK-NEXT: ret163 %shl = shl <2 x i32> %a, <i32 2, i32 2>164 %and = and <2 x i32> %shl, <i32 -32, i32 -32>165 %sub = sub <2 x i32> %b, %and166 ret <2 x i32> %sub167}168 169; negative test: shift one-use170 171define i32 @shiftedreg_from_and_negative_oneuse1(i32 %a, i32 %b) {172; CHECK-LABEL: shiftedreg_from_and_negative_oneuse1:173; CHECK: // %bb.0:174; CHECK-NEXT: asr w8, w0, #23175; CHECK-NEXT: and w9, w8, #0xff000000176; CHECK-NEXT: add w9, w9, w1177; CHECK-NEXT: mul w0, w8, w9178; CHECK-NEXT: ret179 %ashr = ashr i32 %a, 23180 %and = and i32 %ashr, -16777216181 %add = add i32 %and, %b182 %r = mul i32 %ashr, %add183 ret i32 %r184}185 186; negative test: and one-use187 188define i32 @shiftedreg_from_and_negative_oneuse2(i32 %a, i32 %b) {189; CHECK-LABEL: shiftedreg_from_and_negative_oneuse2:190; CHECK: // %bb.0:191; CHECK-NEXT: asr w8, w0, #23192; CHECK-NEXT: and w8, w8, #0xff000000193; CHECK-NEXT: add w9, w8, w1194; CHECK-NEXT: mul w0, w8, w9195; CHECK-NEXT: ret196 %ashr = ashr i32 %a, 23197 %and = and i32 %ashr, -16777216198 %add = add i32 %and, %b199 %r = mul i32 %and, %add200 ret i32 %r201}202 203; negative test: and c is not mask204 205define i32 @shiftedreg_from_and_negative_andc1(i32 %a, i32 %b) {206; CHECK-LABEL: shiftedreg_from_and_negative_andc1:207; CHECK: // %bb.0:208; CHECK-NEXT: mov w8, #26215 // =0x6667209; CHECK-NEXT: movk w8, #65510, lsl #16210; CHECK-NEXT: and w8, w8, w0, asr #23211; CHECK-NEXT: add w0, w8, w1212; CHECK-NEXT: ret213 %ashr = ashr i32 %a, 23214 %and = and i32 %ashr, -1677721215 %add = add i32 %and, %b216 ret i32 %add217}218 219; negative test: sra with and c is not legal mask220 221define i32 @shiftedreg_from_and_negative_andc2(i32 %a, i32 %b) {222; CHECK-LABEL: shiftedreg_from_and_negative_andc2:223; CHECK: // %bb.0:224; CHECK-NEXT: mov w8, #-285212672 // =0xef000000225; CHECK-NEXT: and w8, w8, w0, asr #23226; CHECK-NEXT: add w0, w8, w1227; CHECK-NEXT: ret228 %ashr = ashr i32 %a, 23229 %and = and i32 %ashr, 4009754624 ; 0xef000000230 %add = add i32 %and, %b231 ret i32 %add232}233 234; negative test: shl with and c is not legal mask235 236define i64 @shiftedreg_from_and_negative_andc3(i64 %a, i64 %b) {237; CHECK-LABEL: shiftedreg_from_and_negative_andc3:238; CHECK: // %bb.0:239; CHECK-NEXT: eor x0, x1, x0, lsl #36240; CHECK-NEXT: ret241 %shl = shl i64 %a, 36242 %and = and i64 %shl, -4294967296243 %xor = xor i64 %and, %b244 ret i64 %xor245}246 247; negative test: shl with and c is not legal mask248 249define i64 @shiftedreg_from_and_negative_andc4(i64 %a, i64 %b) {250; CHECK-LABEL: shiftedreg_from_and_negative_andc4:251; CHECK: // %bb.0:252; CHECK-NEXT: lsl x8, x0, #36253; CHECK-NEXT: and x8, x8, #0x7fe0000000000000254; CHECK-NEXT: eor x0, x8, x1255; CHECK-NEXT: ret256 %shl = shl i64 %a, 36257 %and = and i64 %shl, 9214364837600034816258 %xor = xor i64 %and, %b259 ret i64 %xor260}261 262; negative test: sra with and c is not legal mask263 264define i32 @shiftedreg_from_and_negative_andc5(i32 %a, i32 %b) {265; CHECK-LABEL: shiftedreg_from_and_negative_andc5:266; CHECK: // %bb.0:267; CHECK-NEXT: asr w8, w0, #23268; CHECK-NEXT: and w8, w8, #0xff000000269; CHECK-NEXT: add w0, w8, w1270; CHECK-NEXT: ret271 %ashr = ashr i32 %a, 23272 %and = and i32 %ashr, -16777216273 %add = add i32 %and, %b274 ret i32 %add275}276 277; negative test: srl with and c is not legal mask278; srl constant bitwidth > (lowbits + masklen + shiftamt)279 280define i64 @shiftedreg_from_and_negative_andc6(i64 %a, i64 %b) {281; CHECK-LABEL: shiftedreg_from_and_negative_andc6:282; CHECK: // %bb.0:283; CHECK-NEXT: lsr x8, x0, #2284; CHECK-NEXT: and x8, x8, #0x6285; CHECK-NEXT: add x0, x8, x1286; CHECK-NEXT: ret287 %lshr = lshr i64 %a, 2288 %and = and i64 %lshr, 6289 %add = add i64 %and, %b290 ret i64 %add291}292