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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc < %s -mtriple=aarch64--linux-gnu | FileCheck %s3 4define <8 x i8> @sel_v8i8(<8 x i8> %v0, <8 x i8> %v1) {5; CHECK-LABEL: sel_v8i8:6; CHECK: // %bb.0:7; CHECK-NEXT: movi d2, #0xff00ff00ff00ff8; CHECK-NEXT: bif v0.8b, v1.8b, v2.8b9; CHECK-NEXT: ret10 %tmp0 = shufflevector <8 x i8> %v0, <8 x i8> %v1, <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>11 ret <8 x i8> %tmp012}13 14define <16 x i8> @sel_v16i8(<16 x i8> %v0, <16 x i8> %v1) {15; CHECK-LABEL: sel_v16i8:16; CHECK: // %bb.0:17; CHECK-NEXT: movi v2.2d, #0xff00ff00ff00ff18; CHECK-NEXT: bif v0.16b, v1.16b, v2.16b19; CHECK-NEXT: ret20 %tmp0 = shufflevector <16 x i8> %v0, <16 x i8> %v1, <16 x i32> <i32 0, i32 17, i32 2, i32 19, i32 4, i32 21, i32 6, i32 23, i32 8, i32 25, i32 10, i32 27, i32 12, i32 29, i32 14, i32 31>21 ret <16 x i8> %tmp022}23 24define <16 x i8> @sel_v16i8_poison(<16 x i8> %v0, <16 x i8> %v1) {25; CHECK-LABEL: sel_v16i8_poison:26; CHECK: // %bb.0:27; CHECK-NEXT: adrp x8, .LCPI2_028; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI2_0]29; CHECK-NEXT: bif v0.16b, v1.16b, v2.16b30; CHECK-NEXT: ret31 %tmp0 = shufflevector <16 x i8> %v0, <16 x i8> %v1, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 22, i32 23, i32 24, i32 25, i32 26, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>32 ret <16 x i8> %tmp033}34 35define <16 x i8> @sel_v16i8_unregular(<16 x i8> %v0, <16 x i8> %v1) {36; CHECK-LABEL: sel_v16i8_unregular:37; CHECK: // %bb.0:38; CHECK-NEXT: adrp x8, .LCPI3_039; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI3_0]40; CHECK-NEXT: bif v0.16b, v1.16b, v2.16b41; CHECK-NEXT: ret42 %tmp0 = shufflevector <16 x i8> %v0, <16 x i8> %v1, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 27, i32 28, i32 29, i32 30, i32 31>43 ret <16 x i8> %tmp044}45 46define <4 x i16> @sel_v4i16(<4 x i16> %v0, <4 x i16> %v1) {47; CHECK-LABEL: sel_v4i16:48; CHECK: // %bb.0:49; CHECK-NEXT: rev32 v0.4h, v0.4h50; CHECK-NEXT: trn2 v0.4h, v0.4h, v1.4h51; CHECK-NEXT: ret52 %tmp0 = shufflevector <4 x i16> %v0, <4 x i16> %v1, <4 x i32> <i32 0, i32 5, i32 2, i32 7>53 ret <4 x i16> %tmp054}55 56define <8 x i16> @sel_v8i16(<8 x i16> %v0, <8 x i16> %v1) {57; CHECK-LABEL: sel_v8i16:58; CHECK: // %bb.0:59; CHECK-NEXT: movi v2.2d, #0x00ffff0000ffff60; CHECK-NEXT: bif v0.16b, v1.16b, v2.16b61; CHECK-NEXT: ret62 %tmp0 = shufflevector <8 x i16> %v0, <8 x i16> %v1, <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>63 ret <8 x i16> %tmp064}65 66define <2 x i32> @sel_v2i32(<2 x i32> %v0, <2 x i32> %v1) {67; CHECK-LABEL: sel_v2i32:68; CHECK: // %bb.0:69; CHECK-NEXT: // kill: def $d0 killed $d0 def $q070; CHECK-NEXT: // kill: def $d1 killed $d1 def $q171; CHECK-NEXT: mov v0.s[1], v1.s[1]72; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q073; CHECK-NEXT: ret74 %tmp0 = shufflevector <2 x i32> %v0, <2 x i32> %v1, <2 x i32> <i32 0, i32 3>75 ret <2 x i32> %tmp076}77 78define <4 x i32> @sel_v4i32(<4 x i32> %v0, <4 x i32> %v1) {79; CHECK-LABEL: sel_v4i32:80; CHECK: // %bb.0:81; CHECK-NEXT: rev64 v0.4s, v0.4s82; CHECK-NEXT: trn2 v0.4s, v0.4s, v1.4s83; CHECK-NEXT: ret84 %tmp0 = shufflevector <4 x i32> %v0, <4 x i32> %v1, <4 x i32> <i32 0, i32 5, i32 2, i32 7>85 ret <4 x i32> %tmp086}87 88define <2 x i64> @sel_v2i64(<2 x i64> %v0, <2 x i64> %v1) {89; CHECK-LABEL: sel_v2i64:90; CHECK: // %bb.0:91; CHECK-NEXT: mov v0.d[1], v1.d[1]92; CHECK-NEXT: ret93 %tmp0 = shufflevector <2 x i64> %v0, <2 x i64> %v1, <2 x i32> <i32 0, i32 3>94 ret <2 x i64> %tmp095}96 97define <4 x half> @sel_v4f16(<4 x half> %v0, <4 x half> %v1) {98; CHECK-LABEL: sel_v4f16:99; CHECK: // %bb.0:100; CHECK-NEXT: rev32 v0.4h, v0.4h101; CHECK-NEXT: trn2 v0.4h, v0.4h, v1.4h102; CHECK-NEXT: ret103 %tmp0 = shufflevector <4 x half> %v0, <4 x half> %v1, <4 x i32> <i32 0, i32 5, i32 2, i32 7>104 ret <4 x half> %tmp0105}106 107define <8 x half> @sel_v8f16(<8 x half> %v0, <8 x half> %v1) {108; CHECK-LABEL: sel_v8f16:109; CHECK: // %bb.0:110; CHECK-NEXT: movi v2.2d, #0x00ffff0000ffff111; CHECK-NEXT: bif v0.16b, v1.16b, v2.16b112; CHECK-NEXT: ret113 %tmp0 = shufflevector <8 x half> %v0, <8 x half> %v1, <8 x i32> <i32 0, i32 9, i32 2, i32 11, i32 4, i32 13, i32 6, i32 15>114 ret <8 x half> %tmp0115}116 117define <2 x float> @sel_v2f32(<2 x float> %v0, <2 x float> %v1) {118; CHECK-LABEL: sel_v2f32:119; CHECK: // %bb.0:120; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0121; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1122; CHECK-NEXT: mov v0.s[1], v1.s[1]123; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0124; CHECK-NEXT: ret125 %tmp0 = shufflevector <2 x float> %v0, <2 x float> %v1, <2 x i32> <i32 0, i32 3>126 ret <2 x float> %tmp0127}128 129define <4 x float> @sel_v4f32(<4 x float> %v0, <4 x float> %v1) {130; CHECK-LABEL: sel_v4f32:131; CHECK: // %bb.0:132; CHECK-NEXT: rev64 v0.4s, v0.4s133; CHECK-NEXT: trn2 v0.4s, v0.4s, v1.4s134; CHECK-NEXT: ret135 %tmp0 = shufflevector <4 x float> %v0, <4 x float> %v1, <4 x i32> <i32 0, i32 5, i32 2, i32 7>136 ret <4 x float> %tmp0137}138 139define <2 x double> @sel_v2f64(<2 x double> %v0, <2 x double> %v1) {140; CHECK-LABEL: sel_v2f64:141; CHECK: // %bb.0:142; CHECK-NEXT: mov v0.d[1], v1.d[1]143; CHECK-NEXT: ret144 %tmp0 = shufflevector <2 x double> %v0, <2 x double> %v1, <2 x i32> <i32 0, i32 3>145 ret <2 x double> %tmp0146}147