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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s3 4; If positive...5 6define i32 @zext_ifpos(i32 %x) {7; CHECK-LABEL: zext_ifpos:8; CHECK: // %bb.0:9; CHECK-NEXT: mvn w8, w010; CHECK-NEXT: lsr w0, w8, #3111; CHECK-NEXT: ret12 %c = icmp sgt i32 %x, -113 %e = zext i1 %c to i3214 ret i32 %e15}16 17define i32 @add_zext_ifpos(i32 %x) {18; CHECK-LABEL: add_zext_ifpos:19; CHECK: // %bb.0:20; CHECK-NEXT: asr w8, w0, #3121; CHECK-NEXT: add w0, w8, #4222; CHECK-NEXT: ret23 %c = icmp sgt i32 %x, -124 %e = zext i1 %c to i3225 %r = add i32 %e, 4126 ret i32 %r27}28 29define <4 x i32> @add_zext_ifpos_vec_splat(<4 x i32> %x) {30; CHECK-LABEL: add_zext_ifpos_vec_splat:31; CHECK: // %bb.0:32; CHECK-NEXT: movi v1.4s, #4133; CHECK-NEXT: cmge v0.4s, v0.4s, #034; CHECK-NEXT: sub v0.4s, v1.4s, v0.4s35; CHECK-NEXT: ret36 %c = icmp sgt <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>37 %e = zext <4 x i1> %c to <4 x i32>38 %r = add <4 x i32> %e, <i32 41, i32 41, i32 41, i32 41>39 ret <4 x i32> %r40}41 42define i32 @sel_ifpos_tval_bigger(i32 %x) {43; CHECK-LABEL: sel_ifpos_tval_bigger:44; CHECK: // %bb.0:45; CHECK-NEXT: mov w8, #41 // =0x2946; CHECK-NEXT: cmn w0, #147; CHECK-NEXT: cinc w0, w8, gt48; CHECK-NEXT: ret49 %c = icmp sgt i32 %x, -150 %r = select i1 %c, i32 42, i32 4151 ret i32 %r52}53 54define i32 @sext_ifpos(i32 %x) {55; CHECK-LABEL: sext_ifpos:56; CHECK: // %bb.0:57; CHECK-NEXT: mvn w8, w058; CHECK-NEXT: asr w0, w8, #3159; CHECK-NEXT: ret60 %c = icmp sgt i32 %x, -161 %e = sext i1 %c to i3262 ret i32 %e63}64 65define i32 @add_sext_ifpos(i32 %x) {66; CHECK-LABEL: add_sext_ifpos:67; CHECK: // %bb.0:68; CHECK-NEXT: lsr w8, w0, #3169; CHECK-NEXT: add w0, w8, #4170; CHECK-NEXT: ret71 %c = icmp sgt i32 %x, -172 %e = sext i1 %c to i3273 %r = add i32 %e, 4274 ret i32 %r75}76 77define <4 x i32> @add_sext_ifpos_vec_splat(<4 x i32> %x) {78; CHECK-LABEL: add_sext_ifpos_vec_splat:79; CHECK: // %bb.0:80; CHECK-NEXT: movi v1.4s, #4281; CHECK-NEXT: cmge v0.4s, v0.4s, #082; CHECK-NEXT: add v0.4s, v0.4s, v1.4s83; CHECK-NEXT: ret84 %c = icmp sgt <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>85 %e = sext <4 x i1> %c to <4 x i32>86 %r = add <4 x i32> %e, <i32 42, i32 42, i32 42, i32 42>87 ret <4 x i32> %r88}89 90define i32 @sel_ifpos_fval_bigger(i32 %x) {91; CHECK-LABEL: sel_ifpos_fval_bigger:92; CHECK: // %bb.0:93; CHECK-NEXT: mov w8, #41 // =0x2994; CHECK-NEXT: cmn w0, #195; CHECK-NEXT: cinc w0, w8, le96; CHECK-NEXT: ret97 %c = icmp sgt i32 %x, -198 %r = select i1 %c, i32 41, i32 4299 ret i32 %r100}101 102; If negative...103 104define i32 @zext_ifneg(i32 %x) {105; CHECK-LABEL: zext_ifneg:106; CHECK: // %bb.0:107; CHECK-NEXT: lsr w0, w0, #31108; CHECK-NEXT: ret109 %c = icmp slt i32 %x, 0110 %r = zext i1 %c to i32111 ret i32 %r112}113 114define i32 @add_zext_ifneg(i32 %x) {115; CHECK-LABEL: add_zext_ifneg:116; CHECK: // %bb.0:117; CHECK-NEXT: lsr w8, w0, #31118; CHECK-NEXT: add w0, w8, #41119; CHECK-NEXT: ret120 %c = icmp slt i32 %x, 0121 %e = zext i1 %c to i32122 %r = add i32 %e, 41123 ret i32 %r124}125 126define i32 @sel_ifneg_tval_bigger(i32 %x) {127; CHECK-LABEL: sel_ifneg_tval_bigger:128; CHECK: // %bb.0:129; CHECK-NEXT: mov w8, #41 // =0x29130; CHECK-NEXT: cmp w0, #0131; CHECK-NEXT: cinc w0, w8, mi132; CHECK-NEXT: ret133 %c = icmp slt i32 %x, 0134 %r = select i1 %c, i32 42, i32 41135 ret i32 %r136}137 138define i32 @sext_ifneg(i32 %x) {139; CHECK-LABEL: sext_ifneg:140; CHECK: // %bb.0:141; CHECK-NEXT: asr w0, w0, #31142; CHECK-NEXT: ret143 %c = icmp slt i32 %x, 0144 %r = sext i1 %c to i32145 ret i32 %r146}147 148define i32 @add_sext_ifneg(i32 %x) {149; CHECK-LABEL: add_sext_ifneg:150; CHECK: // %bb.0:151; CHECK-NEXT: asr w8, w0, #31152; CHECK-NEXT: add w0, w8, #42153; CHECK-NEXT: ret154 %c = icmp slt i32 %x, 0155 %e = sext i1 %c to i32156 %r = add i32 %e, 42157 ret i32 %r158}159 160define i32 @sel_ifneg_fval_bigger(i32 %x) {161; CHECK-LABEL: sel_ifneg_fval_bigger:162; CHECK: // %bb.0:163; CHECK-NEXT: mov w8, #41 // =0x29164; CHECK-NEXT: cmp w0, #0165; CHECK-NEXT: cinc w0, w8, pl166; CHECK-NEXT: ret167 %c = icmp slt i32 %x, 0168 %r = select i1 %c, i32 41, i32 42169 ret i32 %r170}171 172define i32 @add_lshr_not(i32 %x) {173; CHECK-LABEL: add_lshr_not:174; CHECK: // %bb.0:175; CHECK-NEXT: asr w8, w0, #31176; CHECK-NEXT: add w0, w8, #42177; CHECK-NEXT: ret178 %not = xor i32 %x, -1179 %sh = lshr i32 %not, 31180 %r = add i32 %sh, 41181 ret i32 %r182}183 184define <4 x i32> @add_lshr_not_vec_splat(<4 x i32> %x) {185; CHECK-LABEL: add_lshr_not_vec_splat:186; CHECK: // %bb.0:187; CHECK-NEXT: movi v1.4s, #43188; CHECK-NEXT: ssra v1.4s, v0.4s, #31189; CHECK-NEXT: mov v0.16b, v1.16b190; CHECK-NEXT: ret191 %c = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>192 %e = lshr <4 x i32> %c, <i32 31, i32 31, i32 31, i32 31>193 %r = add <4 x i32> %e, <i32 42, i32 42, i32 42, i32 42>194 ret <4 x i32> %r195}196 197define i32 @sub_lshr_not(i32 %x) {198; CHECK-LABEL: sub_lshr_not:199; CHECK: // %bb.0:200; CHECK-NEXT: mov w8, #42 // =0x2a201; CHECK-NEXT: bfxil w8, w0, #31, #1202; CHECK-NEXT: mov w0, w8203; CHECK-NEXT: ret204 %not = xor i32 %x, -1205 %sh = lshr i32 %not, 31206 %r = sub i32 43, %sh207 ret i32 %r208}209 210define <4 x i32> @sub_lshr_not_vec_splat(<4 x i32> %x) {211; CHECK-LABEL: sub_lshr_not_vec_splat:212; CHECK: // %bb.0:213; CHECK-NEXT: movi v1.4s, #41214; CHECK-NEXT: usra v1.4s, v0.4s, #31215; CHECK-NEXT: mov v0.16b, v1.16b216; CHECK-NEXT: ret217 %c = xor <4 x i32> %x, <i32 -1, i32 -1, i32 -1, i32 -1>218 %e = lshr <4 x i32> %c, <i32 31, i32 31, i32 31, i32 31>219 %r = sub <4 x i32> <i32 42, i32 42, i32 42, i32 42>, %e220 ret <4 x i32> %r221}222 223define i32 @sub_lshr(i32 %x, i32 %y) {224; CHECK-LABEL: sub_lshr:225; CHECK: // %bb.0:226; CHECK-NEXT: add w0, w1, w0, asr #31227; CHECK-NEXT: ret228 %sh = lshr i32 %x, 31229 %r = sub i32 %y, %sh230 ret i32 %r231}232 233define <4 x i32> @sub_lshr_vec(<4 x i32> %x, <4 x i32> %y) {234; CHECK-LABEL: sub_lshr_vec:235; CHECK: // %bb.0:236; CHECK-NEXT: ssra v1.4s, v0.4s, #31237; CHECK-NEXT: mov v0.16b, v1.16b238; CHECK-NEXT: ret239 %sh = lshr <4 x i32> %x, <i32 31, i32 31, i32 31, i32 31>240 %r = sub <4 x i32> %y, %sh241 ret <4 x i32> %r242}243 244define i32 @sub_const_op_lshr(i32 %x) {245; CHECK-LABEL: sub_const_op_lshr:246; CHECK: // %bb.0:247; CHECK-NEXT: asr w8, w0, #31248; CHECK-NEXT: add w0, w8, #43249; CHECK-NEXT: ret250 %sh = lshr i32 %x, 31251 %r = sub i32 43, %sh252 ret i32 %r253}254 255define <4 x i32> @sub_const_op_lshr_vec(<4 x i32> %x) {256; CHECK-LABEL: sub_const_op_lshr_vec:257; CHECK: // %bb.0:258; CHECK-NEXT: movi v1.4s, #42259; CHECK-NEXT: ssra v1.4s, v0.4s, #31260; CHECK-NEXT: mov v0.16b, v1.16b261; CHECK-NEXT: ret262 %sh = lshr <4 x i32> %x, <i32 31, i32 31, i32 31, i32 31>263 %r = sub <4 x i32> <i32 42, i32 42, i32 42, i32 42>, %sh264 ret <4 x i32> %r265}266 267