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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-- < %s | FileCheck %s --check-prefixes=CHECK,CHECK-SD3; RUN: llc -mtriple=aarch64-- -global-isel < %s | FileCheck %s --check-prefixes=CHECK,CHECK-GI4 5define i64 @test_clear_mask_i64_i32(i64 %x) nounwind {6; CHECK-SD-LABEL: test_clear_mask_i64_i32:7; CHECK-SD: // %bb.0: // %entry8; CHECK-SD-NEXT: mov w8, #42 // =0x2a9; CHECK-SD-NEXT: cmn w0, #110; CHECK-SD-NEXT: csel x0, x8, x0, gt11; CHECK-SD-NEXT: ret12;13; CHECK-GI-LABEL: test_clear_mask_i64_i32:14; CHECK-GI: // %bb.0: // %entry15; CHECK-GI-NEXT: mov w8, #42 // =0x2a16; CHECK-GI-NEXT: tst x0, #0x8000000017; CHECK-GI-NEXT: csel x0, x8, x0, eq18; CHECK-GI-NEXT: ret19entry:20 %a = and i64 %x, 214748364821 %r = icmp eq i64 %a, 022 br i1 %r, label %t, label %f23t:24 br label %f25f:26 %ret = phi i64 [ %x, %entry], [ 42, %t]27 ret i64 %ret28}29 30define i64 @test_set_mask_i64_i32(i64 %x) nounwind {31; CHECK-LABEL: test_set_mask_i64_i32:32; CHECK: // %bb.0: // %entry33; CHECK-NEXT: mov w8, #42 // =0x2a34; CHECK-NEXT: tst x0, #0x8000000035; CHECK-NEXT: csel x0, x8, x0, ne36; CHECK-NEXT: ret37entry:38 %a = and i64 %x, 214748364839 %r = icmp ne i64 %a, 040 br i1 %r, label %t, label %f41t:42 br label %f43f:44 %ret = phi i64 [ %x, %entry], [ 42, %t]45 ret i64 %ret46}47 48define i64 @test_clear_mask_i64_i16(i64 %x) nounwind {49; CHECK-LABEL: test_clear_mask_i64_i16:50; CHECK: // %bb.0: // %entry51; CHECK-NEXT: mov w8, #42 // =0x2a52; CHECK-NEXT: tst x0, #0x800053; CHECK-NEXT: csel x0, x8, x0, eq54; CHECK-NEXT: ret55entry:56 %a = and i64 %x, 3276857 %r = icmp eq i64 %a, 058 br i1 %r, label %t, label %f59t:60 br label %f61f:62 %ret = phi i64 [ %x, %entry], [ 42, %t]63 ret i64 %ret64}65 66define i64 @test_set_mask_i64_i16(i64 %x) nounwind {67; CHECK-LABEL: test_set_mask_i64_i16:68; CHECK: // %bb.0: // %entry69; CHECK-NEXT: mov w8, #42 // =0x2a70; CHECK-NEXT: tst x0, #0x800071; CHECK-NEXT: csel x0, x8, x0, ne72; CHECK-NEXT: ret73entry:74 %a = and i64 %x, 3276875 %r = icmp ne i64 %a, 076 br i1 %r, label %t, label %f77t:78 br label %f79f:80 %ret = phi i64 [ %x, %entry], [ 42, %t]81 ret i64 %ret82}83 84define i64 @test_clear_mask_i64_i8(i64 %x) nounwind {85; CHECK-LABEL: test_clear_mask_i64_i8:86; CHECK: // %bb.0: // %entry87; CHECK-NEXT: mov w8, #42 // =0x2a88; CHECK-NEXT: tst x0, #0x8089; CHECK-NEXT: csel x0, x8, x0, eq90; CHECK-NEXT: ret91entry:92 %a = and i64 %x, 12893 %r = icmp eq i64 %a, 094 br i1 %r, label %t, label %f95t:96 br label %f97f:98 %ret = phi i64 [ %x, %entry], [ 42, %t]99 ret i64 %ret100}101 102define i64 @test_set_mask_i64_i8(i64 %x) nounwind {103; CHECK-LABEL: test_set_mask_i64_i8:104; CHECK: // %bb.0: // %entry105; CHECK-NEXT: mov w8, #42 // =0x2a106; CHECK-NEXT: tst x0, #0x80107; CHECK-NEXT: csel x0, x8, x0, ne108; CHECK-NEXT: ret109entry:110 %a = and i64 %x, 128111 %r = icmp ne i64 %a, 0112 br i1 %r, label %t, label %f113t:114 br label %f115f:116 %ret = phi i64 [ %x, %entry], [ 42, %t]117 ret i64 %ret118}119 120define i32 @test_clear_mask_i32_i16(i32 %x) nounwind {121; CHECK-LABEL: test_clear_mask_i32_i16:122; CHECK: // %bb.0: // %entry123; CHECK-NEXT: mov w8, #42 // =0x2a124; CHECK-NEXT: tst w0, #0x8000125; CHECK-NEXT: csel w0, w8, w0, eq126; CHECK-NEXT: ret127entry:128 %a = and i32 %x, 32768129 %r = icmp eq i32 %a, 0130 br i1 %r, label %t, label %f131t:132 br label %f133f:134 %ret = phi i32 [ %x, %entry], [ 42, %t]135 ret i32 %ret136}137 138define i32 @test_set_mask_i32_i16(i32 %x) nounwind {139; CHECK-LABEL: test_set_mask_i32_i16:140; CHECK: // %bb.0: // %entry141; CHECK-NEXT: mov w8, #42 // =0x2a142; CHECK-NEXT: tst w0, #0x8000143; CHECK-NEXT: csel w0, w8, w0, ne144; CHECK-NEXT: ret145entry:146 %a = and i32 %x, 32768147 %r = icmp ne i32 %a, 0148 br i1 %r, label %t, label %f149t:150 br label %f151f:152 %ret = phi i32 [ %x, %entry], [ 42, %t]153 ret i32 %ret154}155 156define i32 @test_clear_mask_i32_i8(i32 %x) nounwind {157; CHECK-LABEL: test_clear_mask_i32_i8:158; CHECK: // %bb.0: // %entry159; CHECK-NEXT: mov w8, #42 // =0x2a160; CHECK-NEXT: tst w0, #0x80161; CHECK-NEXT: csel w0, w8, w0, eq162; CHECK-NEXT: ret163entry:164 %a = and i32 %x, 128165 %r = icmp eq i32 %a, 0166 br i1 %r, label %t, label %f167t:168 br label %f169f:170 %ret = phi i32 [ %x, %entry], [ 42, %t]171 ret i32 %ret172}173 174define i32 @test_set_mask_i32_i8(i32 %x) nounwind {175; CHECK-LABEL: test_set_mask_i32_i8:176; CHECK: // %bb.0: // %entry177; CHECK-NEXT: mov w8, #42 // =0x2a178; CHECK-NEXT: tst w0, #0x80179; CHECK-NEXT: csel w0, w8, w0, ne180; CHECK-NEXT: ret181entry:182 %a = and i32 %x, 128183 %r = icmp ne i32 %a, 0184 br i1 %r, label %t, label %f185t:186 br label %f187f:188 %ret = phi i32 [ %x, %entry], [ 42, %t]189 ret i32 %ret190}191 192define i16 @test_clear_mask_i16_i8(i16 %x) nounwind {193; CHECK-LABEL: test_clear_mask_i16_i8:194; CHECK: // %bb.0: // %entry195; CHECK-NEXT: mov w8, #42 // =0x2a196; CHECK-NEXT: tst w0, #0x80197; CHECK-NEXT: csel w0, w8, w0, eq198; CHECK-NEXT: ret199entry:200 %a = and i16 %x, 128201 %r = icmp eq i16 %a, 0202 br i1 %r, label %t, label %f203t:204 br label %f205f:206 %ret = phi i16 [ %x, %entry], [ 42, %t]207 ret i16 %ret208}209 210define i16 @test_set_mask_i16_i8(i16 %x) nounwind {211; CHECK-LABEL: test_set_mask_i16_i8:212; CHECK: // %bb.0: // %entry213; CHECK-NEXT: mov w8, #42 // =0x2a214; CHECK-NEXT: tst w0, #0x80215; CHECK-NEXT: csel w0, w8, w0, ne216; CHECK-NEXT: ret217entry:218 %a = and i16 %x, 128219 %r = icmp ne i16 %a, 0220 br i1 %r, label %t, label %f221t:222 br label %f223f:224 %ret = phi i16 [ %x, %entry], [ 42, %t]225 ret i16 %ret226}227 228define i16 @test_set_mask_i16_i7(i16 %x) nounwind {229; CHECK-LABEL: test_set_mask_i16_i7:230; CHECK: // %bb.0: // %entry231; CHECK-NEXT: mov w8, #42 // =0x2a232; CHECK-NEXT: tst w0, #0x40233; CHECK-NEXT: csel w0, w8, w0, ne234; CHECK-NEXT: ret235entry:236 %a = and i16 %x, 64237 %r = icmp ne i16 %a, 0238 br i1 %r, label %t, label %f239t:240 br label %f241f:242 %ret = phi i16 [ %x, %entry], [ 42, %t]243 ret i16 %ret244}245