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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-linux-gnu -o - %s | FileCheck %s3 4define <4 x i32> @smull(<4 x i16> %x, ptr %y) {5; CHECK-LABEL: smull:6; CHECK: // %bb.0: // %entry7; CHECK-NEXT: fmov d1, d08; CHECK-NEXT: movi v0.2d, #00000000000000009; CHECK-NEXT: ldr d2, [x0]10; CHECK-NEXT: mov w8, #1 // =0x111; CHECK-NEXT: .LBB0_1: // %l112; CHECK-NEXT: // =>This Inner Loop Header: Depth=113; CHECK-NEXT: smlal v0.4s, v2.4h, v1.h[3]14; CHECK-NEXT: subs w8, w8, #115; CHECK-NEXT: b.eq .LBB0_116; CHECK-NEXT: // %bb.2: // %l217; CHECK-NEXT: ret18entry:19 %a = shufflevector <4 x i16> %x, <4 x i16> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3>20 br label %l121 22l1:23 %p = phi i32 [ 0, %entry ], [ %pa, %l1 ]24 %q = phi <4 x i32> [ zeroinitializer, %entry ], [ %c, %l1 ]25 %l = load <4 x i16>, ptr %y26 %b = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %l, <4 x i16> %a)27 %c = add nsw <4 x i32> %q, %b28 %pa = add i32 %p, 129 %c1 = icmp eq i32 %p, 030 br i1 %c1, label %l1, label %l231 32l2:33 ret <4 x i32> %c34}35 36define <4 x i32> @umull(<4 x i16> %x, ptr %y) {37; CHECK-LABEL: umull:38; CHECK: // %bb.0: // %entry39; CHECK-NEXT: fmov d1, d040; CHECK-NEXT: movi v0.2d, #000000000000000041; CHECK-NEXT: ldr d2, [x0]42; CHECK-NEXT: mov w8, #1 // =0x143; CHECK-NEXT: .LBB1_1: // %l144; CHECK-NEXT: // =>This Inner Loop Header: Depth=145; CHECK-NEXT: umlal v0.4s, v2.4h, v1.h[3]46; CHECK-NEXT: subs w8, w8, #147; CHECK-NEXT: b.eq .LBB1_148; CHECK-NEXT: // %bb.2: // %l249; CHECK-NEXT: ret50entry:51 %a = shufflevector <4 x i16> %x, <4 x i16> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3>52 br label %l153 54l1:55 %p = phi i32 [ 0, %entry ], [ %pa, %l1 ]56 %q = phi <4 x i32> [ zeroinitializer, %entry ], [ %c, %l1 ]57 %l = load <4 x i16>, ptr %y58 %b = tail call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> %l, <4 x i16> %a)59 %c = add nsw <4 x i32> %q, %b60 %pa = add i32 %p, 161 %c1 = icmp eq i32 %p, 062 br i1 %c1, label %l1, label %l263 64l2:65 ret <4 x i32> %c66}67 68define <4 x i32> @sqadd(<4 x i32> %x, ptr %y) {69; CHECK-LABEL: sqadd:70; CHECK: // %bb.0: // %entry71; CHECK-NEXT: mov v1.16b, v0.16b72; CHECK-NEXT: ldr q2, [x0]73; CHECK-NEXT: movi v0.2d, #000000000000000074; CHECK-NEXT: mov w8, #1 // =0x175; CHECK-NEXT: sqrdmulh v1.4s, v2.4s, v1.s[3]76; CHECK-NEXT: .LBB2_1: // %l177; CHECK-NEXT: // =>This Inner Loop Header: Depth=178; CHECK-NEXT: sqadd v0.4s, v0.4s, v1.4s79; CHECK-NEXT: subs w8, w8, #180; CHECK-NEXT: b.eq .LBB2_181; CHECK-NEXT: // %bb.2: // %l282; CHECK-NEXT: ret83entry:84 %a = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3>85 br label %l186 87l1:88 %p = phi i32 [ 0, %entry ], [ %pa, %l1 ]89 %q = phi <4 x i32> [ zeroinitializer, %entry ], [ %c, %l1 ]90 %l = load <4 x i32>, ptr %y91 %b = tail call <4 x i32> @llvm.aarch64.neon.sqrdmulh.v4i32(<4 x i32> %l, <4 x i32> %a)92 %c = tail call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> %q, <4 x i32> %b)93 %pa = add i32 %p, 194 %c1 = icmp eq i32 %p, 095 br i1 %c1, label %l1, label %l296 97l2:98 ret <4 x i32> %c99}100 101define <4 x i32> @sqsub(<4 x i32> %x, ptr %y) {102; CHECK-LABEL: sqsub:103; CHECK: // %bb.0: // %entry104; CHECK-NEXT: mov v1.16b, v0.16b105; CHECK-NEXT: ldr q2, [x0]106; CHECK-NEXT: movi v0.2d, #0000000000000000107; CHECK-NEXT: mov w8, #1 // =0x1108; CHECK-NEXT: sqrdmulh v1.4s, v2.4s, v1.s[3]109; CHECK-NEXT: .LBB3_1: // %l1110; CHECK-NEXT: // =>This Inner Loop Header: Depth=1111; CHECK-NEXT: sqsub v0.4s, v0.4s, v1.4s112; CHECK-NEXT: subs w8, w8, #1113; CHECK-NEXT: b.eq .LBB3_1114; CHECK-NEXT: // %bb.2: // %l2115; CHECK-NEXT: ret116entry:117 %a = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3>118 br label %l1119 120l1:121 %p = phi i32 [ 0, %entry ], [ %pa, %l1 ]122 %q = phi <4 x i32> [ zeroinitializer, %entry ], [ %c, %l1 ]123 %l = load <4 x i32>, ptr %y124 %b = tail call <4 x i32> @llvm.aarch64.neon.sqrdmulh.v4i32(<4 x i32> %l, <4 x i32> %a)125 %c = tail call <4 x i32> @llvm.aarch64.neon.sqsub.v4i32(<4 x i32> %q, <4 x i32> %b)126 %pa = add i32 %p, 1127 %c1 = icmp eq i32 %p, 0128 br i1 %c1, label %l1, label %l2129 130l2:131 ret <4 x i32> %c132}133 134define <4 x i32> @sqdmulh(<4 x i32> %x, ptr %y) {135; CHECK-LABEL: sqdmulh:136; CHECK: // %bb.0: // %entry137; CHECK-NEXT: mov v1.16b, v0.16b138; CHECK-NEXT: ldr q2, [x0]139; CHECK-NEXT: movi v0.2d, #0000000000000000140; CHECK-NEXT: mov w8, #1 // =0x1141; CHECK-NEXT: sqdmulh v1.4s, v2.4s, v1.s[3]142; CHECK-NEXT: .LBB4_1: // %l1143; CHECK-NEXT: // =>This Inner Loop Header: Depth=1144; CHECK-NEXT: add v0.4s, v0.4s, v1.4s145; CHECK-NEXT: subs w8, w8, #1146; CHECK-NEXT: b.eq .LBB4_1147; CHECK-NEXT: // %bb.2: // %l2148; CHECK-NEXT: ret149entry:150 %a = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3>151 br label %l1152 153l1:154 %p = phi i32 [ 0, %entry ], [ %pa, %l1 ]155 %q = phi <4 x i32> [ zeroinitializer, %entry ], [ %c, %l1 ]156 %l = load <4 x i32>, ptr %y157 %b = tail call <4 x i32> @llvm.aarch64.neon.sqdmulh.v4i32(<4 x i32> %l, <4 x i32> %a)158 %c = add nsw <4 x i32> %q, %b159 %pa = add i32 %p, 1160 %c1 = icmp eq i32 %p, 0161 br i1 %c1, label %l1, label %l2162 163l2:164 ret <4 x i32> %c165}166 167define <4 x i32> @sqdmull(<4 x i16> %x, ptr %y) {168; CHECK-LABEL: sqdmull:169; CHECK: // %bb.0: // %entry170; CHECK-NEXT: fmov d1, d0171; CHECK-NEXT: ldr d2, [x0]172; CHECK-NEXT: movi v0.2d, #0000000000000000173; CHECK-NEXT: mov w8, #1 // =0x1174; CHECK-NEXT: sqdmull v1.4s, v2.4h, v1.h[3]175; CHECK-NEXT: .LBB5_1: // %l1176; CHECK-NEXT: // =>This Inner Loop Header: Depth=1177; CHECK-NEXT: add v0.4s, v0.4s, v1.4s178; CHECK-NEXT: subs w8, w8, #1179; CHECK-NEXT: b.eq .LBB5_1180; CHECK-NEXT: // %bb.2: // %l2181; CHECK-NEXT: ret182entry:183 %a = shufflevector <4 x i16> %x, <4 x i16> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3>184 br label %l1185 186l1:187 %p = phi i32 [ 0, %entry ], [ %pa, %l1 ]188 %q = phi <4 x i32> [ zeroinitializer, %entry ], [ %c, %l1 ]189 %l = load <4 x i16>, ptr %y190 %b = tail call <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16> %l, <4 x i16> %a)191 %c = add nsw <4 x i32> %q, %b192 %pa = add i32 %p, 1193 %c1 = icmp eq i32 %p, 0194 br i1 %c1, label %l1, label %l2195 196l2:197 ret <4 x i32> %c198}199 200define <4 x i32> @mlal(<4 x i32> %x, ptr %y) {201; CHECK-LABEL: mlal:202; CHECK: // %bb.0: // %entry203; CHECK-NEXT: mov v1.16b, v0.16b204; CHECK-NEXT: movi v0.2d, #0000000000000000205; CHECK-NEXT: ldr q2, [x0]206; CHECK-NEXT: mov w8, #1 // =0x1207; CHECK-NEXT: .LBB6_1: // %l1208; CHECK-NEXT: // =>This Inner Loop Header: Depth=1209; CHECK-NEXT: mla v0.4s, v2.4s, v1.s[3]210; CHECK-NEXT: subs w8, w8, #1211; CHECK-NEXT: b.eq .LBB6_1212; CHECK-NEXT: // %bb.2: // %l2213; CHECK-NEXT: ret214entry:215 %a = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3>216 br label %l1217 218l1:219 %p = phi i32 [ 0, %entry ], [ %pa, %l1 ]220 %q = phi <4 x i32> [ zeroinitializer, %entry ], [ %c, %l1 ]221 %l = load <4 x i32>, ptr %y222 %b = mul <4 x i32> %l, %a223 %c = add <4 x i32> %q, %b224 %pa = add i32 %p, 1225 %c1 = icmp eq i32 %p, 0226 br i1 %c1, label %l1, label %l2227 228l2:229 ret <4 x i32> %c230}231 232define <4 x float> @fmul(ptr %x, ptr %y) {233; CHECK-LABEL: fmul:234; CHECK: // %bb.0: // %entry235; CHECK-NEXT: movi v0.2d, #0000000000000000236; CHECK-NEXT: ldr s1, [x0]237; CHECK-NEXT: mov x8, xzr238; CHECK-NEXT: .LBB7_1: // %l1239; CHECK-NEXT: // =>This Inner Loop Header: Depth=1240; CHECK-NEXT: ldr q2, [x1, x8]241; CHECK-NEXT: add x8, x8, #16242; CHECK-NEXT: cmp w8, #16243; CHECK-NEXT: fmul v2.4s, v2.4s, v1.s[0]244; CHECK-NEXT: fadd v0.4s, v2.4s, v0.4s245; CHECK-NEXT: b.eq .LBB7_1246; CHECK-NEXT: // %bb.2: // %l2247; CHECK-NEXT: ret248entry:249 %x.val = load float, ptr %x250 %x.ins = insertelement <4 x float> poison, float %x.val, i64 0251 %a = shufflevector <4 x float> %x.ins, <4 x float> undef, <4 x i32> zeroinitializer252 br label %l1253 254l1:255 %p = phi i32 [ 0, %entry ], [ %pa, %l1 ]256 %q = phi <4 x float> [ zeroinitializer, %entry ], [ %c, %l1 ]257 %idx.y = mul nuw nsw i32 %p, 4258 %ptr.y = getelementptr float, ptr %y, i32 %idx.y259 %l = load <4 x float>, ptr %ptr.y260 %b = fmul <4 x float> %l, %a261 %c = fadd <4 x float> %b, %q262 %pa = add i32 %p, 1263 %c1 = icmp eq i32 %p, 0264 br i1 %c1, label %l1, label %l2265 266l2:267 ret <4 x float> %c268}269 270define <4 x float> @fmuladd(<4 x float> %x, ptr %y) {271; CHECK-LABEL: fmuladd:272; CHECK: // %bb.0: // %entry273; CHECK-NEXT: mov v1.16b, v0.16b274; CHECK-NEXT: movi v0.2d, #0000000000000000275; CHECK-NEXT: ldr q2, [x0]276; CHECK-NEXT: mov w8, #1 // =0x1277; CHECK-NEXT: .LBB8_1: // %l1278; CHECK-NEXT: // =>This Inner Loop Header: Depth=1279; CHECK-NEXT: fmla v0.4s, v2.4s, v1.s[3]280; CHECK-NEXT: subs w8, w8, #1281; CHECK-NEXT: b.eq .LBB8_1282; CHECK-NEXT: // %bb.2: // %l2283; CHECK-NEXT: ret284entry:285 %a = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3>286 br label %l1287 288l1:289 %p = phi i32 [ 0, %entry ], [ %pa, %l1 ]290 %q = phi <4 x float> [ zeroinitializer, %entry ], [ %c, %l1 ]291 %l = load <4 x float>, ptr %y292 %b = fmul fast <4 x float> %l, %a293 %c = fadd fast <4 x float> %b, %q294 %pa = add i32 %p, 1295 %c1 = icmp eq i32 %p, 0296 br i1 %c1, label %l1, label %l2297 298l2:299 ret <4 x float> %c300}301 302define <4 x float> @fma(<4 x float> %x, ptr %y) {303; CHECK-LABEL: fma:304; CHECK: // %bb.0: // %entry305; CHECK-NEXT: mov v1.16b, v0.16b306; CHECK-NEXT: movi v0.2d, #0000000000000000307; CHECK-NEXT: ldr q2, [x0]308; CHECK-NEXT: mov w8, #1 // =0x1309; CHECK-NEXT: dup v1.4s, v1.s[3]310; CHECK-NEXT: .LBB9_1: // %l1311; CHECK-NEXT: // =>This Inner Loop Header: Depth=1312; CHECK-NEXT: mov v3.16b, v0.16b313; CHECK-NEXT: mov v0.16b, v1.16b314; CHECK-NEXT: subs w8, w8, #1315; CHECK-NEXT: fmla v0.4s, v3.4s, v2.4s316; CHECK-NEXT: b.eq .LBB9_1317; CHECK-NEXT: // %bb.2: // %l2318; CHECK-NEXT: ret319entry:320 %a = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3>321 br label %l1322 323l1:324 %p = phi i32 [ 0, %entry ], [ %pa, %l1 ]325 %q = phi <4 x float> [ zeroinitializer, %entry ], [ %c, %l1 ]326 %l = load <4 x float>, ptr %y327 %c = tail call <4 x float> @llvm.fma.v4f32(<4 x float> %l, <4 x float> %q, <4 x float> %a)328 %pa = add i32 %p, 1329 %c1 = icmp eq i32 %p, 0330 br i1 %c1, label %l1, label %l2331 332l2:333 ret <4 x float> %c334}335 336define <4 x i32> @smull_nonsplat(<4 x i16> %x, ptr %y) {337; CHECK-LABEL: smull_nonsplat:338; CHECK: // %bb.0: // %entry339; CHECK-NEXT: fmov d1, d0340; CHECK-NEXT: movi v0.2d, #0000000000000000341; CHECK-NEXT: mov w8, #1 // =0x1342; CHECK-NEXT: trn2 v2.4h, v1.4h, v1.4h343; CHECK-NEXT: zip2 v1.4h, v2.4h, v1.4h344; CHECK-NEXT: ldr d2, [x0]345; CHECK-NEXT: .LBB10_1: // %l1346; CHECK-NEXT: // =>This Inner Loop Header: Depth=1347; CHECK-NEXT: smlal v0.4s, v2.4h, v1.4h348; CHECK-NEXT: subs w8, w8, #1349; CHECK-NEXT: b.eq .LBB10_1350; CHECK-NEXT: // %bb.2: // %l2351; CHECK-NEXT: ret352entry:353 %a = shufflevector <4 x i16> %x, <4 x i16> undef, <4 x i32> <i32 3, i32 2, i32 3, i32 3>354 br label %l1355 356l1:357 %p = phi i32 [ 0, %entry ], [ %pa, %l1 ]358 %q = phi <4 x i32> [ zeroinitializer, %entry ], [ %c, %l1 ]359 %l = load <4 x i16>, ptr %y360 %b = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %l, <4 x i16> %a)361 %c = add nsw <4 x i32> %q, %b362 %pa = add i32 %p, 1363 %c1 = icmp eq i32 %p, 0364 br i1 %c1, label %l1, label %l2365 366l2:367 ret <4 x i32> %c368}369 370define <4 x i32> @smull_splat_and_extract(<4 x i16> %x, <8 x i16> %l, ptr %y, i1 %co) {371; CHECK-LABEL: smull_splat_and_extract:372; CHECK: // %bb.0: // %entry373; CHECK-NEXT: fmov d2, d0374; CHECK-NEXT: smull v0.4s, v1.4h, v2.h[3]375; CHECK-NEXT: tbz w1, #0, .LBB11_2376; CHECK-NEXT: // %bb.1: // %l1377; CHECK-NEXT: smlal2 v0.4s, v1.8h, v2.h[3]378; CHECK-NEXT: .LBB11_2: // %l2379; CHECK-NEXT: ret380entry:381 %a = shufflevector <4 x i16> %x, <4 x i16> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3>382 %e1 = shufflevector <8 x i16> %l, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>383 %e2 = shufflevector <8 x i16> %l, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>384 %b = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %e1, <4 x i16> %a)385 br i1 %co, label %l1, label %l2386 387l1:388 %b2 = tail call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> %e2, <4 x i16> %a)389 %c2 = add nsw <4 x i32> %b, %b2390 br label %l2391 392l2:393 %r = phi <4 x i32> [ %b, %entry ], [ %c2, %l1 ]394 ret <4 x i32> %r395}396 397define <4 x i32> @umull_splat_and_extract(<4 x i16> %x, <8 x i16> %l, ptr %y, i1 %co) {398; CHECK-LABEL: umull_splat_and_extract:399; CHECK: // %bb.0: // %entry400; CHECK-NEXT: fmov d2, d0401; CHECK-NEXT: umull v0.4s, v1.4h, v2.h[3]402; CHECK-NEXT: tbz w1, #0, .LBB12_2403; CHECK-NEXT: // %bb.1: // %l1404; CHECK-NEXT: umlal2 v0.4s, v1.8h, v2.h[3]405; CHECK-NEXT: .LBB12_2: // %l2406; CHECK-NEXT: ret407entry:408 %a = shufflevector <4 x i16> %x, <4 x i16> undef, <4 x i32> <i32 3, i32 3, i32 3, i32 3>409 %e1 = shufflevector <8 x i16> %l, <8 x i16> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>410 %e2 = shufflevector <8 x i16> %l, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7>411 %b = tail call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> %e1, <4 x i16> %a)412 br i1 %co, label %l1, label %l2413 414l1:415 %b2 = tail call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> %e2, <4 x i16> %a)416 %c2 = add nsw <4 x i32> %b, %b2417 br label %l2418 419l2:420 %r = phi <4 x i32> [ %b, %entry ], [ %c2, %l1 ]421 ret <4 x i32> %r422}423 424; We shouldn't sink without fullfp16.425define <4 x half> @fmul_half(ptr %x, ptr %y) {426; CHECK-LABEL: fmul_half:427; CHECK: // %bb.0: // %entry428; CHECK-NEXT: ld1r { v1.4h }, [x0]429; CHECK-NEXT: movi d0, #0000000000000000430; CHECK-NEXT: mov x8, xzr431; CHECK-NEXT: fcvtl v1.4s, v1.4h432; CHECK-NEXT: .LBB13_1: // %l1433; CHECK-NEXT: // =>This Inner Loop Header: Depth=1434; CHECK-NEXT: ldr d2, [x1, x8]435; CHECK-NEXT: fcvtl v0.4s, v0.4h436; CHECK-NEXT: add x8, x8, #8437; CHECK-NEXT: cmp w8, #8438; CHECK-NEXT: fcvtl v2.4s, v2.4h439; CHECK-NEXT: fmul v2.4s, v2.4s, v1.4s440; CHECK-NEXT: fcvtn v2.4h, v2.4s441; CHECK-NEXT: fcvtl v2.4s, v2.4h442; CHECK-NEXT: fadd v0.4s, v2.4s, v0.4s443; CHECK-NEXT: fcvtn v0.4h, v0.4s444; CHECK-NEXT: b.eq .LBB13_1445; CHECK-NEXT: // %bb.2: // %l2446; CHECK-NEXT: ret447entry:448 %x.val = load half, ptr %x449 %x.ins = insertelement <4 x half> poison, half %x.val, i64 0450 %a = shufflevector <4 x half> %x.ins, <4 x half> undef, <4 x i32> zeroinitializer451 br label %l1452 453l1:454 %p = phi i32 [ 0, %entry ], [ %pa, %l1 ]455 %q = phi <4 x half> [ zeroinitializer, %entry ], [ %c, %l1 ]456 %idx.y = mul nuw nsw i32 %p, 4457 %ptr.y = getelementptr half, ptr %y, i32 %idx.y458 %l = load <4 x half>, ptr %ptr.y459 %b = fmul <4 x half> %l, %a460 %c = fadd <4 x half> %b, %q461 %pa = add i32 %p, 1462 %c1 = icmp eq i32 %p, 0463 br i1 %c1, label %l1, label %l2464 465l2:466 ret <4 x half> %c467}468 469define <4 x half> @fmul_half_fullfp16(ptr %x, ptr %y) "target-features"="+fullfp16" {470; CHECK-LABEL: fmul_half_fullfp16:471; CHECK: // %bb.0: // %entry472; CHECK-NEXT: movi d0, #0000000000000000473; CHECK-NEXT: ldr h1, [x0]474; CHECK-NEXT: mov x8, xzr475; CHECK-NEXT: .LBB14_1: // %l1476; CHECK-NEXT: // =>This Inner Loop Header: Depth=1477; CHECK-NEXT: ldr d2, [x1, x8]478; CHECK-NEXT: add x8, x8, #8479; CHECK-NEXT: cmp w8, #8480; CHECK-NEXT: fmul v2.4h, v2.4h, v1.h[0]481; CHECK-NEXT: fadd v0.4h, v2.4h, v0.4h482; CHECK-NEXT: b.eq .LBB14_1483; CHECK-NEXT: // %bb.2: // %l2484; CHECK-NEXT: ret485entry:486 %x.val = load half, ptr %x487 %x.ins = insertelement <4 x half> poison, half %x.val, i64 0488 %a = shufflevector <4 x half> %x.ins, <4 x half> undef, <4 x i32> zeroinitializer489 br label %l1490 491l1:492 %p = phi i32 [ 0, %entry ], [ %pa, %l1 ]493 %q = phi <4 x half> [ zeroinitializer, %entry ], [ %c, %l1 ]494 %idx.y = mul nuw nsw i32 %p, 4495 %ptr.y = getelementptr half, ptr %y, i32 %idx.y496 %l = load <4 x half>, ptr %ptr.y497 %b = fmul <4 x half> %l, %a498 %c = fadd <4 x half> %b, %q499 %pa = add i32 %p, 1500 %c1 = icmp eq i32 %p, 0501 br i1 %c1, label %l1, label %l2502 503l2:504 ret <4 x half> %c505}506 507; We shouldn't sink the splat operand for scalable vectors.508define <vscale x 4 x float> @fmul_scalable(ptr %x, ptr %y) "target-features"="+sve" {509; CHECK-LABEL: fmul_scalable:510; CHECK: // %bb.0: // %entry511; CHECK-NEXT: ptrue p0.s512; CHECK-NEXT: rdvl x8, #1513; CHECK-NEXT: movi v0.2d, #0000000000000000514; CHECK-NEXT: sxtw x8, w8515; CHECK-NEXT: mov w9, #1 // =0x1516; CHECK-NEXT: ld1rw { z1.s }, p0/z, [x0]517; CHECK-NEXT: lsl x8, x8, #2518; CHECK-NEXT: .LBB15_1: // %l1519; CHECK-NEXT: // =>This Inner Loop Header: Depth=1520; CHECK-NEXT: ldr z2, [x1]521; CHECK-NEXT: subs w9, w9, #1522; CHECK-NEXT: add x1, x1, x8523; CHECK-NEXT: fmul z2.s, z2.s, z1.s524; CHECK-NEXT: fadd z0.s, z2.s, z0.s525; CHECK-NEXT: b.eq .LBB15_1526; CHECK-NEXT: // %bb.2: // %l2527; CHECK-NEXT: ret528entry:529 %x.val = load float, ptr %x530 %x.ins = insertelement <vscale x 4 x float> poison, float %x.val, i64 0531 %a = shufflevector <vscale x 4 x float> %x.ins, <vscale x 4 x float> undef, <vscale x 4 x i32> zeroinitializer532 %33 = tail call i32 @llvm.vscale.i32()533 %34 = shl nuw nsw i32 %33, 4534 br label %l1535 536l1:537 %p = phi i32 [ 0, %entry ], [ %pa, %l1 ]538 %q = phi <vscale x 4 x float> [ zeroinitializer, %entry ], [ %c, %l1 ]539 %idx.y = mul nuw nsw i32 %p, %34540 %ptr.y = getelementptr float, ptr %y, i32 %idx.y541 %l = load <vscale x 4 x float>, ptr %ptr.y542 %b = fmul <vscale x 4 x float> %l, %a543 %c = fadd <vscale x 4 x float> %b, %q544 %pa = add i32 %p, 1545 %c1 = icmp eq i32 %p, 0546 br i1 %c1, label %l1, label %l2547 548l2:549 ret <vscale x 4 x float> %c550}551 552 553declare <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16>, <4 x i16>)554declare <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16>, <4 x i16>)555declare <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32>, <4 x i32>)556declare <4 x i32> @llvm.aarch64.neon.sqsub.v4i32(<4 x i32>, <4 x i32>)557declare <4 x i32> @llvm.aarch64.neon.sqrdmulh.v4i32(<4 x i32>, <4 x i32>)558declare <4 x i32> @llvm.aarch64.neon.sqdmull.v4i32(<4 x i16>, <4 x i16>)559declare <4 x i32> @llvm.aarch64.neon.sqdmulh.v4i32(<4 x i32>, <4 x i32>)560declare <4 x float> @llvm.fma.v4f32(<4 x float> %l, <4 x float> %a, <4 x float> %q)561