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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=aarch64-unknown-linux-gnu -mattr=+sme -aarch64-new-sme-abi -relocation-model=pic < %s | FileCheck %s3 4@x = external thread_local local_unnamed_addr global i32, align 45 6define i32 @load_tls_streaming_compat() nounwind "aarch64_pstate_sm_compatible" {7; CHECK-LABEL: load_tls_streaming_compat:8; CHECK: // %bb.0: // %entry9; CHECK-NEXT: stp d15, d14, [sp, #-80]! // 16-byte Folded Spill10; CHECK-NEXT: stp d13, d12, [sp, #16] // 16-byte Folded Spill11; CHECK-NEXT: stp d11, d10, [sp, #32] // 16-byte Folded Spill12; CHECK-NEXT: stp d9, d8, [sp, #48] // 16-byte Folded Spill13; CHECK-NEXT: str x30, [sp, #64] // 8-byte Spill14; CHECK-NEXT: mrs x8, SVCR15; CHECK-NEXT: tbz w8, #0, .LBB0_216; CHECK-NEXT: // %bb.1: // %entry17; CHECK-NEXT: smstop sm18; CHECK-NEXT: .LBB0_2: // %entry19; CHECK-NEXT: adrp x0, :tlsdesc:x20; CHECK-NEXT: ldr x1, [x0, :tlsdesc_lo12:x]21; CHECK-NEXT: add x0, x0, :tlsdesc_lo12:x22; CHECK-NEXT: .tlsdesccall x23; CHECK-NEXT: blr x124; CHECK-NEXT: tbz w8, #0, .LBB0_425; CHECK-NEXT: // %bb.3: // %entry26; CHECK-NEXT: smstart sm27; CHECK-NEXT: .LBB0_4: // %entry28; CHECK-NEXT: mrs x8, TPIDR_EL029; CHECK-NEXT: ldp d9, d8, [sp, #48] // 16-byte Folded Reload30; CHECK-NEXT: ldp d11, d10, [sp, #32] // 16-byte Folded Reload31; CHECK-NEXT: ldr w0, [x8, x0]32; CHECK-NEXT: ldp d13, d12, [sp, #16] // 16-byte Folded Reload33; CHECK-NEXT: ldr x30, [sp, #64] // 8-byte Reload34; CHECK-NEXT: ldp d15, d14, [sp], #80 // 16-byte Folded Reload35; CHECK-NEXT: ret36entry:37 %0 = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @x)38 %1 = load i32, ptr %0, align 439 ret i32 %140}41 42define i32 @load_tls_streaming() nounwind "aarch64_pstate_sm_enabled" {43; CHECK-LABEL: load_tls_streaming:44; CHECK: // %bb.0: // %entry45; CHECK-NEXT: stp d15, d14, [sp, #-80]! // 16-byte Folded Spill46; CHECK-NEXT: stp d13, d12, [sp, #16] // 16-byte Folded Spill47; CHECK-NEXT: stp d11, d10, [sp, #32] // 16-byte Folded Spill48; CHECK-NEXT: stp d9, d8, [sp, #48] // 16-byte Folded Spill49; CHECK-NEXT: str x30, [sp, #64] // 8-byte Spill50; CHECK-NEXT: smstop sm51; CHECK-NEXT: adrp x0, :tlsdesc:x52; CHECK-NEXT: ldr x1, [x0, :tlsdesc_lo12:x]53; CHECK-NEXT: add x0, x0, :tlsdesc_lo12:x54; CHECK-NEXT: .tlsdesccall x55; CHECK-NEXT: blr x156; CHECK-NEXT: smstart sm57; CHECK-NEXT: mrs x8, TPIDR_EL058; CHECK-NEXT: ldp d9, d8, [sp, #48] // 16-byte Folded Reload59; CHECK-NEXT: ldp d11, d10, [sp, #32] // 16-byte Folded Reload60; CHECK-NEXT: ldr w0, [x8, x0]61; CHECK-NEXT: ldp d13, d12, [sp, #16] // 16-byte Folded Reload62; CHECK-NEXT: ldr x30, [sp, #64] // 8-byte Reload63; CHECK-NEXT: ldp d15, d14, [sp], #80 // 16-byte Folded Reload64; CHECK-NEXT: ret65entry:66 %0 = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @x)67 %1 = load i32, ptr %0, align 468 ret i32 %169}70 71define i32 @load_tls_shared_za() nounwind "aarch64_inout_za" {72; CHECK-LABEL: load_tls_shared_za:73; CHECK: // %bb.0: // %entry74; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill75; CHECK-NEXT: mov x29, sp76; CHECK-NEXT: sub sp, sp, #1677; CHECK-NEXT: rdsvl x8, #178; CHECK-NEXT: mov x9, sp79; CHECK-NEXT: msub x9, x8, x8, x980; CHECK-NEXT: mov sp, x981; CHECK-NEXT: sub x10, x29, #1682; CHECK-NEXT: stp x9, x8, [x29, #-16]83; CHECK-NEXT: msr TPIDR2_EL0, x1084; CHECK-NEXT: adrp x0, :tlsdesc:x85; CHECK-NEXT: ldr x1, [x0, :tlsdesc_lo12:x]86; CHECK-NEXT: add x0, x0, :tlsdesc_lo12:x87; CHECK-NEXT: .tlsdesccall x88; CHECK-NEXT: blr x189; CHECK-NEXT: mrs x8, TPIDR_EL090; CHECK-NEXT: ldr w0, [x8, x0]91; CHECK-NEXT: mov w8, w092; CHECK-NEXT: smstart za93; CHECK-NEXT: mrs x9, TPIDR2_EL094; CHECK-NEXT: sub x0, x29, #1695; CHECK-NEXT: cbnz x9, .LBB2_296; CHECK-NEXT: // %bb.1: // %entry97; CHECK-NEXT: bl __arm_tpidr2_restore98; CHECK-NEXT: .LBB2_2: // %entry99; CHECK-NEXT: mov w0, w8100; CHECK-NEXT: msr TPIDR2_EL0, xzr101; CHECK-NEXT: mov sp, x29102; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload103; CHECK-NEXT: ret104entry:105 %0 = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @x)106 %1 = load i32, ptr %0, align 4107 ret i32 %1108}109 110define i32 @load_tls_streaming_shared_za() nounwind "aarch64_inout_za" "aarch64_pstate_sm_enabled" {111; CHECK-LABEL: load_tls_streaming_shared_za:112; CHECK: // %bb.0: // %entry113; CHECK-NEXT: stp d15, d14, [sp, #-96]! // 16-byte Folded Spill114; CHECK-NEXT: stp d13, d12, [sp, #16] // 16-byte Folded Spill115; CHECK-NEXT: stp d11, d10, [sp, #32] // 16-byte Folded Spill116; CHECK-NEXT: stp d9, d8, [sp, #48] // 16-byte Folded Spill117; CHECK-NEXT: stp x29, x30, [sp, #64] // 16-byte Folded Spill118; CHECK-NEXT: add x29, sp, #64119; CHECK-NEXT: str x19, [sp, #80] // 8-byte Spill120; CHECK-NEXT: sub sp, sp, #16121; CHECK-NEXT: rdsvl x8, #1122; CHECK-NEXT: mov x9, sp123; CHECK-NEXT: msub x9, x8, x8, x9124; CHECK-NEXT: mov sp, x9125; CHECK-NEXT: stp x9, x8, [x29, #-80]126; CHECK-NEXT: smstop sm127; CHECK-NEXT: sub x8, x29, #80128; CHECK-NEXT: msr TPIDR2_EL0, x8129; CHECK-NEXT: adrp x0, :tlsdesc:x130; CHECK-NEXT: ldr x1, [x0, :tlsdesc_lo12:x]131; CHECK-NEXT: add x0, x0, :tlsdesc_lo12:x132; CHECK-NEXT: .tlsdesccall x133; CHECK-NEXT: blr x1134; CHECK-NEXT: smstart sm135; CHECK-NEXT: mrs x8, TPIDR_EL0136; CHECK-NEXT: ldr w0, [x8, x0]137; CHECK-NEXT: mov w8, w0138; CHECK-NEXT: smstart za139; CHECK-NEXT: mrs x9, TPIDR2_EL0140; CHECK-NEXT: sub x0, x29, #80141; CHECK-NEXT: cbnz x9, .LBB3_2142; CHECK-NEXT: // %bb.1: // %entry143; CHECK-NEXT: bl __arm_tpidr2_restore144; CHECK-NEXT: .LBB3_2: // %entry145; CHECK-NEXT: mov w0, w8146; CHECK-NEXT: msr TPIDR2_EL0, xzr147; CHECK-NEXT: sub sp, x29, #64148; CHECK-NEXT: ldp x29, x30, [sp, #64] // 16-byte Folded Reload149; CHECK-NEXT: ldr x19, [sp, #80] // 8-byte Reload150; CHECK-NEXT: ldp d9, d8, [sp, #48] // 16-byte Folded Reload151; CHECK-NEXT: ldp d11, d10, [sp, #32] // 16-byte Folded Reload152; CHECK-NEXT: ldp d13, d12, [sp, #16] // 16-byte Folded Reload153; CHECK-NEXT: ldp d15, d14, [sp], #96 // 16-byte Folded Reload154; CHECK-NEXT: ret155entry:156 %0 = tail call align 4 ptr @llvm.threadlocal.address.p0(ptr align 4 @x)157 %1 = load i32, ptr %0, align 4158 ret i32 %1159}160