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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -verify-machineinstrs < %s | FileCheck %s3 4define i64 @cntsb() {5; CHECK-LABEL: cntsb:6; CHECK: // %bb.0:7; CHECK-NEXT: rdsvl x0, #18; CHECK-NEXT: ret9 %1 = call i64 @llvm.aarch64.sme.cntsd()10 %res = shl nuw nsw i64 %1, 311 ret i64 %res12}13 14define i64 @cntsh() {15; CHECK-LABEL: cntsh:16; CHECK: // %bb.0:17; CHECK-NEXT: rdsvl x8, #118; CHECK-NEXT: lsr x0, x8, #119; CHECK-NEXT: ret20 %1 = call i64 @llvm.aarch64.sme.cntsd()21 %res = shl nuw nsw i64 %1, 222 ret i64 %res23}24 25define i64 @cntsw() {26; CHECK-LABEL: cntsw:27; CHECK: // %bb.0:28; CHECK-NEXT: rdsvl x8, #129; CHECK-NEXT: lsr x0, x8, #230; CHECK-NEXT: ret31 %1 = call i64 @llvm.aarch64.sme.cntsd()32 %res = shl nuw nsw i64 %1, 133 ret i64 %res34}35 36define i64 @cntsd() {37; CHECK-LABEL: cntsd:38; CHECK: // %bb.0:39; CHECK-NEXT: rdsvl x8, #140; CHECK-NEXT: lsr x0, x8, #341; CHECK-NEXT: ret42 %res = call i64 @llvm.aarch64.sme.cntsd()43 ret i64 %res44}45 46define i64 @sme_cntsb_mul() {47; CHECK-LABEL: sme_cntsb_mul:48; CHECK: // %bb.0:49; CHECK-NEXT: rdsvl x0, #450; CHECK-NEXT: ret51 %v = call i64 @llvm.aarch64.sme.cntsd()52 %shl = shl nuw nsw i64 %v, 353 %res = mul nuw nsw i64 %shl, 454 ret i64 %res55}56 57define i64 @sme_cntsh_mul() {58; CHECK-LABEL: sme_cntsh_mul:59; CHECK: // %bb.0:60; CHECK-NEXT: rdsvl x0, #461; CHECK-NEXT: ret62 %v = call i64 @llvm.aarch64.sme.cntsd()63 %shl = shl nuw nsw i64 %v, 264 %res = mul nuw nsw i64 %shl, 865 ret i64 %res66}67 68define i64 @sme_cntsw_mul() {69; CHECK-LABEL: sme_cntsw_mul:70; CHECK: // %bb.0:71; CHECK-NEXT: rdsvl x0, #472; CHECK-NEXT: ret73 %v = call i64 @llvm.aarch64.sme.cntsd()74 %shl = shl nuw nsw i64 %v, 175 %res = mul nuw nsw i64 %shl, 1676 ret i64 %res77}78 79define i64 @sme_cntsd_mul() {80; CHECK-LABEL: sme_cntsd_mul:81; CHECK: // %bb.0:82; CHECK-NEXT: rdsvl x0, #483; CHECK-NEXT: ret84 %v = call i64 @llvm.aarch64.sme.cntsd()85 %res = mul nuw nsw i64 %v, 3286 ret i64 %res87}88 89define i64 @sme_cntsb_mul_pos() {90; CHECK-LABEL: sme_cntsb_mul_pos:91; CHECK: // %bb.0:92; CHECK-NEXT: rdsvl x8, #2493; CHECK-NEXT: lsl x0, x8, #294; CHECK-NEXT: ret95 %v = call i64 @llvm.aarch64.sme.cntsd()96 %shl = shl nuw nsw i64 %v, 397 %res = mul nuw nsw i64 %shl, 9698 ret i64 %res99}100 101define i64 @sme_cntsh_mul_pos() {102; CHECK-LABEL: sme_cntsh_mul_pos:103; CHECK: // %bb.0:104; CHECK-NEXT: rdsvl x8, #3105; CHECK-NEXT: lsr x0, x8, #1106; CHECK-NEXT: ret107 %v = call i64 @llvm.aarch64.sme.cntsd()108 %shl = shl nuw nsw i64 %v, 2109 %res = mul nuw nsw i64 %shl, 3110 ret i64 %res111}112 113define i64 @sme_cntsw_mul_pos() {114; CHECK-LABEL: sme_cntsw_mul_pos:115; CHECK: // %bb.0:116; CHECK-NEXT: rdsvl x8, #31117; CHECK-NEXT: lsr x0, x8, #1118; CHECK-NEXT: ret119 %v = call i64 @llvm.aarch64.sme.cntsd()120 %shl = shl nuw nsw i64 %v, 1121 %res = mul nuw nsw i64 %shl, 62122 ret i64 %res123}124 125define i64 @sme_cntsd_mul_pos() {126; CHECK-LABEL: sme_cntsd_mul_pos:127; CHECK: // %bb.0:128; CHECK-NEXT: rdsvl x8, #31129; CHECK-NEXT: lsl x0, x8, #2130; CHECK-NEXT: ret131 %v = call i64 @llvm.aarch64.sme.cntsd()132 %res = mul nuw nsw i64 %v, 992133 ret i64 %res134}135 136define i64 @sme_cntsb_mul_neg() {137; CHECK-LABEL: sme_cntsb_mul_neg:138; CHECK: // %bb.0:139; CHECK-NEXT: rdsvl x8, #-24140; CHECK-NEXT: lsl x0, x8, #2141; CHECK-NEXT: ret142 %v = call i64 @llvm.aarch64.sme.cntsd()143 %shl = shl nuw nsw i64 %v, 3144 %res = mul nuw nsw i64 %shl, -96145 ret i64 %res146}147 148define i64 @sme_cntsh_mul_neg() {149; CHECK-LABEL: sme_cntsh_mul_neg:150; CHECK: // %bb.0:151; CHECK-NEXT: rdsvl x8, #-3152; CHECK-NEXT: lsr x0, x8, #1153; CHECK-NEXT: ret154 %v = call i64 @llvm.aarch64.sme.cntsd()155 %shl = shl nuw nsw i64 %v, 2156 %res = mul nuw nsw i64 %shl, -3157 ret i64 %res158}159 160define i64 @sme_cntsw_mul_neg() {161; CHECK-LABEL: sme_cntsw_mul_neg:162; CHECK: // %bb.0:163; CHECK-NEXT: rdsvl x8, #-31164; CHECK-NEXT: lsl x0, x8, #3165; CHECK-NEXT: ret166 %v = call i64 @llvm.aarch64.sme.cntsd()167 %shl = shl nuw nsw i64 %v, 1168 %res = mul nuw nsw i64 %shl, -992169 ret i64 %res170}171 172define i64 @sme_cntsd_mul_neg() {173; CHECK-LABEL: sme_cntsd_mul_neg:174; CHECK: // %bb.0:175; CHECK-NEXT: rdsvl x8, #-3176; CHECK-NEXT: lsr x0, x8, #3177; CHECK-NEXT: ret178 %v = call i64 @llvm.aarch64.sme.cntsd()179 %res = mul nuw nsw i64 %v, -3180 ret i64 %res181}182 183; Negative test for optimization failure184define i64 @sme_cntsd_mul_fail() {185; CHECK-LABEL: sme_cntsd_mul_fail:186; CHECK: // %bb.0:187; CHECK-NEXT: rdsvl x8, #1188; CHECK-NEXT: mov w9, #993 // =0x3e1189; CHECK-NEXT: lsr x8, x8, #3190; CHECK-NEXT: mul x0, x8, x9191; CHECK-NEXT: ret192 %v = call i64 @llvm.aarch64.sme.cntsd()193 %res = mul nuw nsw i64 %v, 993194 ret i64 %res195}196 197