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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme2,+fp8 -verify-machineinstrs -force-streaming -enable-subreg-liveness < %s | FileCheck %s3 4; FCVT / FCVTN / BFCVT5 6define <vscale x 16 x i8> @fcvt_x2(<vscale x 8 x half> %zn0, <vscale x 8 x half> %zn1) {7; CHECK-LABEL: fcvt_x2:8; CHECK: // %bb.0:9; CHECK-NEXT: fcvt z0.b, { z0.h, z1.h }10; CHECK-NEXT: ret11 %res = call <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvt.x2.nxv8f16(<vscale x 8 x half> %zn0, <vscale x 8 x half> %zn1)12 ret <vscale x 16 x i8> %res13}14 15define <vscale x 16 x i8> @fcvt_x4(<vscale x 4 x float> %zn0, <vscale x 4 x float> %zn1, <vscale x 4 x float> %zn2, <vscale x 4 x float> %zn3) {16; CHECK-LABEL: fcvt_x4:17; CHECK: // %bb.0:18; CHECK-NEXT: fcvt z0.b, { z0.s - z3.s }19; CHECK-NEXT: ret20 %res = call <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvt.x4(<vscale x 4 x float> %zn0, <vscale x 4 x float> %zn1,21 <vscale x 4 x float> %zn2, <vscale x 4 x float> %zn3)22 ret <vscale x 16 x i8> %res23}24 25define { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @fcvt_x4_tuple(i64 %stride, ptr %ptr) {26; CHECK-LABEL: fcvt_x4_tuple:27; CHECK: // %bb.0: // %entry28; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill29; CHECK-NEXT: addvl sp, sp, #-930; CHECK-NEXT: str p8, [sp, #7, mul vl] // 2-byte Spill31; CHECK-NEXT: str z23, [sp, #1, mul vl] // 16-byte Folded Spill32; CHECK-NEXT: str z22, [sp, #2, mul vl] // 16-byte Folded Spill33; CHECK-NEXT: str z21, [sp, #3, mul vl] // 16-byte Folded Spill34; CHECK-NEXT: str z20, [sp, #4, mul vl] // 16-byte Folded Spill35; CHECK-NEXT: str z19, [sp, #5, mul vl] // 16-byte Folded Spill36; CHECK-NEXT: str z18, [sp, #6, mul vl] // 16-byte Folded Spill37; CHECK-NEXT: str z17, [sp, #7, mul vl] // 16-byte Folded Spill38; CHECK-NEXT: str z16, [sp, #8, mul vl] // 16-byte Folded Spill39; CHECK-NEXT: .cfi_escape 0x0f, 0x0a, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x11, 0xc8, 0x00, 0x1e, 0x22 // sp + 16 + 72 * VG40; CHECK-NEXT: .cfi_offset w29, -1641; CHECK-NEXT: lsl x8, x0, #142; CHECK-NEXT: add x9, x1, x043; CHECK-NEXT: ptrue pn8.b44; CHECK-NEXT: ld1w { z16.s, z20.s, z24.s, z28.s }, pn8/z, [x1]45; CHECK-NEXT: ld1w { z17.s, z21.s, z25.s, z29.s }, pn8/z, [x9]46; CHECK-NEXT: add x10, x1, x847; CHECK-NEXT: add x8, x9, x848; CHECK-NEXT: ld1w { z18.s, z22.s, z26.s, z30.s }, pn8/z, [x10]49; CHECK-NEXT: ld1w { z19.s, z23.s, z27.s, z31.s }, pn8/z, [x8]50; CHECK-NEXT: fcvt z0.b, { z16.s - z19.s }51; CHECK-NEXT: fcvt z1.b, { z20.s - z23.s }52; CHECK-NEXT: fcvt z2.b, { z24.s - z27.s }53; CHECK-NEXT: fcvt z3.b, { z28.s - z31.s }54; CHECK-NEXT: ldr z23, [sp, #1, mul vl] // 16-byte Folded Reload55; CHECK-NEXT: ldr z22, [sp, #2, mul vl] // 16-byte Folded Reload56; CHECK-NEXT: ldr z21, [sp, #3, mul vl] // 16-byte Folded Reload57; CHECK-NEXT: ldr z20, [sp, #4, mul vl] // 16-byte Folded Reload58; CHECK-NEXT: ldr z19, [sp, #5, mul vl] // 16-byte Folded Reload59; CHECK-NEXT: ldr z18, [sp, #6, mul vl] // 16-byte Folded Reload60; CHECK-NEXT: ldr z17, [sp, #7, mul vl] // 16-byte Folded Reload61; CHECK-NEXT: ldr z16, [sp, #8, mul vl] // 16-byte Folded Reload62; CHECK-NEXT: ldr p8, [sp, #7, mul vl] // 2-byte Reload63; CHECK-NEXT: addvl sp, sp, #964; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload65; CHECK-NEXT: ret66entry:67 %0 = tail call target("aarch64.svcount") @llvm.aarch64.sve.ptrue.c8()68 %1 = tail call { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.ld1.pn.x4.nxv4f32(target("aarch64.svcount") %0, ptr %ptr)69 %2 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %1, 070 %3 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %1, 171 %4 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %1, 272 %5 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %1, 373 %arrayidx2 = getelementptr inbounds i8, ptr %ptr, i64 %stride74 %6 = tail call { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.ld1.pn.x4.nxv4f32(target("aarch64.svcount") %0, ptr %arrayidx2)75 %7 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %6, 076 %8 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %6, 177 %9 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %6, 278 %10 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %6, 379 %mul3 = shl i64 %stride, 180 %arrayidx4 = getelementptr inbounds i8, ptr %ptr, i64 %mul381 %11 = tail call { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.ld1.pn.x4.nxv4f32(target("aarch64.svcount") %0, ptr %arrayidx4)82 %12 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %11, 083 %13 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %11, 184 %14 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %11, 285 %15 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %11, 386 %mul5 = mul i64 %stride, 387 %arrayidx6 = getelementptr inbounds i8, ptr %ptr, i64 %mul588 %16 = tail call { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.ld1.pn.x4.nxv4f32(target("aarch64.svcount") %0, ptr %arrayidx6)89 %17 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %16, 090 %18 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %16, 191 %19 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %16, 292 %20 = extractvalue { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %16, 393 %res1 = call <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvt.x4(<vscale x 4 x float> %2, <vscale x 4 x float> %7, <vscale x 4 x float> %12, <vscale x 4 x float> %17)94 %res2 = call <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvt.x4(<vscale x 4 x float> %3, <vscale x 4 x float> %8, <vscale x 4 x float> %13, <vscale x 4 x float> %18)95 %res3 = call <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvt.x4(<vscale x 4 x float> %4, <vscale x 4 x float> %9, <vscale x 4 x float> %14, <vscale x 4 x float> %19)96 %res4 = call <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvt.x4(<vscale x 4 x float> %5, <vscale x 4 x float> %10, <vscale x 4 x float> %15, <vscale x 4 x float> %20)97 %ins1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %res1, 098 %ins2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %ins1, <vscale x 16 x i8> %res2, 199 %ins3 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %ins2, <vscale x 16 x i8> %res3, 2100 %ins4 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %ins3, <vscale x 16 x i8> %res4, 3101 ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %ins4102}103 104define <vscale x 16 x i8> @fcvtn(<vscale x 4 x float> %zn0, <vscale x 4 x float> %zn1, <vscale x 4 x float> %zn2, <vscale x 4 x float> %zn3) {105; CHECK-LABEL: fcvtn:106; CHECK: // %bb.0:107; CHECK-NEXT: fcvtn z0.b, { z0.s - z3.s }108; CHECK-NEXT: ret109 %res = call <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvtn.x4(<vscale x 4 x float> %zn0, <vscale x 4 x float> %zn1,110 <vscale x 4 x float> %zn2, <vscale x 4 x float> %zn3)111 ret <vscale x 16 x i8> %res112}113 114define <vscale x 16 x i8> @bfcvt(<vscale x 8 x bfloat> %zn0, <vscale x 8 x bfloat> %zn1) {115; CHECK-LABEL: bfcvt:116; CHECK: // %bb.0:117; CHECK-NEXT: bfcvt z0.b, { z0.h, z1.h }118; CHECK-NEXT: ret119 %res = call <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvt.x2.nxv8bf16(<vscale x 8 x bfloat> %zn0, <vscale x 8 x bfloat> %zn1)120 ret <vscale x 16 x i8> %res121}122 123 124define { <vscale x 16 x i8>, <vscale x 16 x i8> } @bfcvt_tuple(i64 %stride, ptr %ptr) {125; CHECK-LABEL: bfcvt_tuple:126; CHECK: // %bb.0: // %entry127; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill128; CHECK-NEXT: addvl sp, sp, #-3129; CHECK-NEXT: str p8, [sp, #7, mul vl] // 2-byte Spill130; CHECK-NEXT: str z11, [sp, #1, mul vl] // 16-byte Folded Spill131; CHECK-NEXT: str z10, [sp, #2, mul vl] // 16-byte Folded Spill132; CHECK-NEXT: .cfi_escape 0x0f, 0x08, 0x8f, 0x10, 0x92, 0x2e, 0x00, 0x48, 0x1e, 0x22 // sp + 16 + 24 * VG133; CHECK-NEXT: .cfi_offset w29, -16134; CHECK-NEXT: .cfi_escape 0x10, 0x4a, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x78, 0x1e, 0x22, 0x40, 0x1c // $d10 @ cfa - 8 * VG - 16135; CHECK-NEXT: .cfi_escape 0x10, 0x4b, 0x09, 0x92, 0x2e, 0x00, 0x11, 0x70, 0x1e, 0x22, 0x40, 0x1c // $d11 @ cfa - 16 * VG - 16136; CHECK-NEXT: ptrue pn8.b137; CHECK-NEXT: add x8, x1, x0138; CHECK-NEXT: ld1h { z2.h, z10.h }, pn8/z, [x1]139; CHECK-NEXT: ld1h { z3.h, z11.h }, pn8/z, [x8]140; CHECK-NEXT: bfcvt z0.b, { z2.h, z3.h }141; CHECK-NEXT: bfcvt z1.b, { z10.h, z11.h }142; CHECK-NEXT: ldr z11, [sp, #1, mul vl] // 16-byte Folded Reload143; CHECK-NEXT: ldr z10, [sp, #2, mul vl] // 16-byte Folded Reload144; CHECK-NEXT: ldr p8, [sp, #7, mul vl] // 2-byte Reload145; CHECK-NEXT: addvl sp, sp, #3146; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload147; CHECK-NEXT: ret148entry:149 %0 = tail call target("aarch64.svcount") @llvm.aarch64.sve.ptrue.c8()150 %1 = tail call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.ld1.pn.x2.nxv8bf16(target("aarch64.svcount") %0, ptr %ptr)151 %2 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, 0152 %3 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %1, 1153 %arrayidx2 = getelementptr inbounds i8, ptr %ptr, i64 %stride154 %4 = tail call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.ld1.pn.x2.nxv8bf16(target("aarch64.svcount") %0, ptr %arrayidx2)155 %5 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 0156 %6 = extractvalue { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %4, 1157 %res1 = call <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvt.x2.nxv8bf16(<vscale x 8 x bfloat> %2, <vscale x 8 x bfloat> %5)158 %res2 = call <vscale x 16 x i8> @llvm.aarch64.sve.fp8.cvt.x2.nxv8bf16(<vscale x 8 x bfloat> %3, <vscale x 8 x bfloat> %6)159 %ins1 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } poison, <vscale x 16 x i8> %res1, 0160 %ins2 = insertvalue { <vscale x 16 x i8>, <vscale x 16 x i8> } %ins1, <vscale x 16 x i8> %res2, 1161 ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %ins2162}163 164; F1CVT / F2CVT165 166define { <vscale x 8 x half>, <vscale x 8 x half> } @f1cvt(<vscale x 16 x i8> %zm) {167; CHECK-LABEL: f1cvt:168; CHECK: // %bb.0:169; CHECK-NEXT: f1cvt { z0.h, z1.h }, z0.b170; CHECK-NEXT: ret171 %res = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.fp8.cvt1.x2.nxv8f16(<vscale x 16 x i8> %zm)172 ret { <vscale x 8 x half>, <vscale x 8 x half> } %res173}174 175define { <vscale x 8 x half>, <vscale x 8 x half> } @f2cvt(<vscale x 16 x i8> %zm) {176; CHECK-LABEL: f2cvt:177; CHECK: // %bb.0:178; CHECK-NEXT: f2cvt { z0.h, z1.h }, z0.b179; CHECK-NEXT: ret180 %res = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.fp8.cvt2.x2.nxv8f16(<vscale x 16 x i8> %zm)181 ret { <vscale x 8 x half>, <vscale x 8 x half> } %res182}183 184; BF1CVT / BF2CVT185 186define { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @bf1cvt(<vscale x 16 x i8> %zm) {187; CHECK-LABEL: bf1cvt:188; CHECK: // %bb.0:189; CHECK-NEXT: bf1cvt { z0.h, z1.h }, z0.b190; CHECK-NEXT: ret191 %res = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fp8.cvt1.x2.nxv8bf16(<vscale x 16 x i8> %zm)192 ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %res193}194 195define { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @bf2cvt(<vscale x 16 x i8> %zm) {196; CHECK-LABEL: bf2cvt:197; CHECK: // %bb.0:198; CHECK-NEXT: bf2cvt { z0.h, z1.h }, z0.b199; CHECK-NEXT: ret200 %res = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fp8.cvt2.x2.nxv8bf16(<vscale x 16 x i8> %zm)201 ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %res202}203 204; F1CVTL / F2CVTL205 206define { <vscale x 8 x half>, <vscale x 8 x half> } @f1cvtl(<vscale x 16 x i8> %zm) {207; CHECK-LABEL: f1cvtl:208; CHECK: // %bb.0:209; CHECK-NEXT: f1cvtl { z0.h, z1.h }, z0.b210; CHECK-NEXT: ret211 %res = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.fp8.cvtl1.x2.nxv8f16(<vscale x 16 x i8> %zm)212 ret { <vscale x 8 x half>, <vscale x 8 x half> } %res213}214 215define { <vscale x 8 x half>, <vscale x 8 x half> } @f2cvtl(<vscale x 16 x i8> %zm) {216; CHECK-LABEL: f2cvtl:217; CHECK: // %bb.0:218; CHECK-NEXT: f2cvtl { z0.h, z1.h }, z0.b219; CHECK-NEXT: ret220 %res = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.fp8.cvtl2.x2.nxvbf16(<vscale x 16 x i8> %zm)221 ret { <vscale x 8 x half>, <vscale x 8 x half> } %res222}223 224; BF1CVTL / BF2CVTL225 226define { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @bf1cvtl(<vscale x 16 x i8> %zm) {227; CHECK-LABEL: bf1cvtl:228; CHECK: // %bb.0:229; CHECK-NEXT: bf1cvtl { z0.h, z1.h }, z0.b230; CHECK-NEXT: ret231 %res = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fp8.cvtl1.x2.nxv8bf16(<vscale x 16 x i8> %zm)232 ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %res233}234 235define { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @bf2cvtl( <vscale x 16 x i8> %zm) {236; CHECK-LABEL: bf2cvtl:237; CHECK: // %bb.0:238; CHECK-NEXT: bf2cvtl { z0.h, z1.h }, z0.b239; CHECK-NEXT: ret240 %res = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fp8.cvtl2.x2.nxv8bf16(<vscale x 16 x i8> %zm)241 ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %res242}243