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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --filter-out "// kill:" --version 42; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme-f8f16,+sme-f8f32 -force-streaming < %s | FileCheck %s3 4; FMLAL (indexed)5 6define void @test_fmlal_vg2x1(i32 %slice, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) {7; CHECK-LABEL: test_fmlal_vg2x1:8; CHECK: // %bb.0:9; CHECK: mov w8, w010; CHECK: fmlal za.h[w8, 0:1], z0.b, z1.b[0]11; CHECK: fmlal za.h[w8, 14:15], z0.b, z1.b[15]12; CHECK: ret13 call void @llvm.aarch64.sme.fp8.fmlal.lane.za16.vg2x1(i32 %slice,14 <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm,15 i32 0)16 %add = add i32 %slice, 1417 call void @llvm.aarch64.sme.fp8.fmlal.lane.za16.vg2x1(i32 %add,18 <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm,19 i32 15)20 ret void21}22 23define void @test_fmlal_vg2x2(i32 %slice, <vscale x 16 x i8> %zn0, <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zm) {24; CHECK-LABEL: test_fmlal_vg2x2:25; CHECK: // %bb.0:26; CHECK: mov w8, w027; CHECK: fmlal za.h[w8, 0:1, vgx2], { z0.b, z1.b }, z2.b[0]28; CHECK: fmlal za.h[w8, 6:7, vgx2], { z0.b, z1.b }, z2.b[15]29; CHECK: ret30 call void @llvm.aarch64.sme.fp8.fmlal.lane.za16.vg2x2(i32 %slice,31 <vscale x 16 x i8> %zn0, <vscale x 16 x i8> %zn1,32 <vscale x 16 x i8> %zm,33 i32 0)34 %add = add i32 %slice, 635 call void @llvm.aarch64.sme.fp8.fmlal.lane.za16.vg2x2(i32 %add,36 <vscale x 16 x i8> %zn0, <vscale x 16 x i8> %zn1,37 <vscale x 16 x i8> %zm,38 i32 15)39 ret void40}41 42define void @test_fmlal_vg2x4(i32 %slice, <vscale x 16 x i8> %zn0, <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zn3, <vscale x 16 x i8> %zm) {43; CHECK-LABEL: test_fmlal_vg2x4:44; CHECK: // %bb.0:45; CHECK: mov w8, w046; CHECK: fmlal za.h[w8, 0:1, vgx4], { z0.b - z3.b }, z4.b[0]47; CHECK: fmlal za.h[w8, 6:7, vgx4], { z0.b - z3.b }, z4.b[15]48; CHECK: ret49 call void @llvm.aarch64.sme.fp8.fmlal.lane.za16.vg2x4(i32 %slice,50 <vscale x 16 x i8> %zn0, <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zn3,51 <vscale x 16 x i8> %zm,52 i32 0)53 %add = add i32 %slice, 654 call void @llvm.aarch64.sme.fp8.fmlal.lane.za16.vg2x4(i32 %add,55 <vscale x 16 x i8> %zn0, <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zn3,56 <vscale x 16 x i8> %zm,57 i32 15)58 ret void59}60 61; FMLALL (indexed)62 63define void @test_fmlall_vg4x1(i32 %slice, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) {64; CHECK-LABEL: test_fmlall_vg4x1:65; CHECK: // %bb.0:66; CHECK: mov w8, w067; CHECK: fmlall za.s[w8, 0:3], z0.b, z1.b[0]68; CHECK: fmlall za.s[w8, 12:15], z0.b, z1.b[15]69; CHECK: ret70 call void @llvm.aarch64.sme.fp8.fmlall.lane.za32.vg4x1(i32 %slice,71 <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm,72 i32 0)73 %add = add i32 %slice, 1274 call void @llvm.aarch64.sme.fp8.fmlall.lane.za32.vg4x1(i32 %add,75 <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm,76 i32 15)77 ret void78}79 80define void @test_fmlall_vg4x2(i32 %slice, <vscale x 16 x i8> %zn0, <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zm) {81; CHECK-LABEL: test_fmlall_vg4x2:82; CHECK: // %bb.0:83; CHECK: mov w8, w084; CHECK: fmlall za.s[w8, 0:3, vgx2], { z0.b, z1.b }, z2.b[0]85; CHECK: fmlall za.s[w8, 4:7, vgx2], { z0.b, z1.b }, z2.b[15]86; CHECK: ret87 call void @llvm.aarch64.sme.fp8.fmlall.lane.za32.vg4x2(i32 %slice,88 <vscale x 16 x i8> %zn0, <vscale x 16 x i8> %zn1,89 <vscale x 16 x i8> %zm,90 i32 0)91 %add = add i32 %slice, 492 call void @llvm.aarch64.sme.fp8.fmlall.lane.za32.vg4x2(i32 %add,93 <vscale x 16 x i8> %zn0, <vscale x 16 x i8> %zn1,94 <vscale x 16 x i8> %zm,95 i32 15)96 ret void97}98 99define void @test_fmlall_vg4x4(i32 %slice, <vscale x 16 x i8> %zn0, <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zn3, <vscale x 16 x i8> %zm) {100; CHECK-LABEL: test_fmlall_vg4x4:101; CHECK: // %bb.0:102; CHECK: mov w8, w0103; CHECK: fmlall za.s[w8, 0:3, vgx4], { z0.b - z3.b }, z4.b[8]104; CHECK: fmlall za.s[w8, 4:7, vgx4], { z0.b - z3.b }, z4.b[15]105; CHECK: ret106 call void @llvm.aarch64.sme.fp8.fmlall.lane.za32.vg4x4(i32 %slice,107 <vscale x 16 x i8> %zn0, <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zn3,108 <vscale x 16 x i8> %zm,109 i32 8)110 %add = add i32 %slice, 4111 call void @llvm.aarch64.sme.fp8.fmlall.lane.za32.vg4x4(i32 %add,112 <vscale x 16 x i8> %zn0, <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zn3,113 <vscale x 16 x i8> %zm,114 i32 15)115 ret void116}117 118; FMLAL (single)119 120define void @test_fmlal_single_vg2x1(i32 %slice, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) {121; CHECK-LABEL: test_fmlal_single_vg2x1:122; CHECK: // %bb.0:123; CHECK: mov w8, w0124; CHECK: fmlal za.h[w8, 0:1], z0.b, z1.b125; CHECK: fmlal za.h[w8, 14:15], z0.b, z1.b126; CHECK: ret127 call void @llvm.aarch64.sme.fp8.fmlal.single.za16.vg2x1(i32 %slice, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm)128 %add = add i32 %slice, 14129 call void @llvm.aarch64.sme.fp8.fmlal.single.za16.vg2x1(i32 %add, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm)130 ret void131}132 133define void @test_fmlal_single_vg2x2(i32 %slice, <vscale x 16 x i8> %zn0, <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zm) {134; CHECK-LABEL: test_fmlal_single_vg2x2:135; CHECK: // %bb.0:136; CHECK: mov w8, w0137; CHECK: fmlal za.h[w8, 0:1, vgx2], { z0.b, z1.b }, z2.b138; CHECK: fmlal za.h[w8, 6:7, vgx2], { z0.b, z1.b }, z2.b139; CHECK: ret140 call void @llvm.aarch64.sme.fp8.fmlal.single.za16.vg2x2(i32 %slice,141 <vscale x 16 x i8> %zn0, <vscale x 16 x i8> %zn1,142 <vscale x 16 x i8> %zm)143 %add = add i32 %slice, 6144 call void @llvm.aarch64.sme.fp8.fmlal.single.za16.vg2x2(i32 %add,145 <vscale x 16 x i8> %zn0, <vscale x 16 x i8> %zn1,146 <vscale x 16 x i8> %zm)147 ret void148}149 150define void @test_fmlal_single_vg2x4(i32 %slice, <vscale x 16 x i8> %zn0, <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zn3, <vscale x 16 x i8> %zm) {151; CHECK-LABEL: test_fmlal_single_vg2x4:152; CHECK: // %bb.0:153; CHECK: mov w8, w0154; CHECK: fmlal za.h[w8, 0:1, vgx4], { z0.b - z3.b }, z4.b155; CHECK: fmlal za.h[w8, 6:7, vgx4], { z0.b - z3.b }, z4.b156; CHECK: ret157 call void @llvm.aarch64.sme.fp8.fmlal.single.za16.vg2x4(i32 %slice,158 <vscale x 16 x i8> %zn0, <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zn3,159 <vscale x 16 x i8> %zm)160 %add = add i32 %slice, 6161 call void @llvm.aarch64.sme.fp8.fmlal.single.za16.vg2x4(i32 %add,162 <vscale x 16 x i8> %zn0, <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zn3,163 <vscale x 16 x i8> %zm)164 ret void165}166 167; FMLALL (single)168 169define void @test_fmlall_single_vg4x1(i32 %slice, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) {170; CHECK-LABEL: test_fmlall_single_vg4x1:171; CHECK: // %bb.0:172; CHECK: mov w8, w0173; CHECK: fmlall za.s[w8, 0:3], z0.b, z1.b174; CHECK: fmlall za.s[w8, 12:15], z0.b, z1.b175; CHECK: ret176 call void @llvm.aarch64.sme.fp8.fmlall.single.za32.vg4x1(i32 %slice, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm)177 %add = add i32 %slice, 12178 call void @llvm.aarch64.sme.fp8.fmlall.single.za32.vg4x1(i32 %add, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm)179 ret void180}181 182 183define void @test_fmlall_single_vg4x2(i32 %slice, <vscale x 16 x i8> %zn0, <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zm) {184; CHECK-LABEL: test_fmlall_single_vg4x2:185; CHECK: // %bb.0:186; CHECK: mov w8, w0187; CHECK: fmlall za.s[w8, 0:3, vgx2], { z0.b, z1.b }, z2.b188; CHECK: fmlall za.s[w8, 4:7, vgx2], { z0.b, z1.b }, z2.b189; CHECK: ret190 call void @llvm.aarch64.sme.fp8.fmlall.single.za32.vg4x2(i32 %slice,191 <vscale x 16 x i8> %zn0, <vscale x 16 x i8> %zn1,192 <vscale x 16 x i8> %zm)193 %add = add i32 %slice, 4194 call void @llvm.aarch64.sme.fp8.fmlall.single.za32.vg4x2(i32 %add,195 <vscale x 16 x i8> %zn0, <vscale x 16 x i8> %zn1,196 <vscale x 16 x i8> %zm)197 ret void198}199 200define void @test_fmlall_single_vg4x4(i32 %slice, <vscale x 16 x i8> %zn0, <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zn3, <vscale x 16 x i8> %zm) {201; CHECK-LABEL: test_fmlall_single_vg4x4:202; CHECK: // %bb.0:203; CHECK: mov w8, w0204; CHECK: fmlall za.s[w8, 0:3, vgx4], { z0.b - z3.b }, z4.b205; CHECK: fmlall za.s[w8, 4:7, vgx4], { z0.b - z3.b }, z4.b206; CHECK: ret207 call void @llvm.aarch64.sme.fp8.fmlall.single.za32.vg4x4(i32 %slice,208 <vscale x 16 x i8> %zn0, <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zn3,209 <vscale x 16 x i8> %zm)210 %add = add i32 %slice, 4211 call void @llvm.aarch64.sme.fp8.fmlall.single.za32.vg4x4(i32 %add,212 <vscale x 16 x i8> %zn0, <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zn3,213 <vscale x 16 x i8> %zm)214 ret void215}216 217; FMLAL (multi)218 219define void @test_fmlal_multi_vg2x2(i32 %slice, <vscale x 16 x i8> %zn0, <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zm0, <vscale x 16 x i8> %zm1) {220; CHECK-LABEL: test_fmlal_multi_vg2x2:221; CHECK: // %bb.0:222; CHECK: mov w8, w0223; CHECK: fmlal za.h[w8, 0:1, vgx2], { z0.b, z1.b }, { z2.b, z3.b }224; CHECK: fmlal za.h[w8, 6:7, vgx2], { z0.b, z1.b }, { z2.b, z3.b }225; CHECK: ret226 call void @llvm.aarch64.sme.fp8.fmlal.multi.za16.vg2x2(i32 %slice,227 <vscale x 16 x i8> %zn0, <vscale x 16 x i8> %zn1,228 <vscale x 16 x i8> %zm0, <vscale x 16 x i8> %zm1)229 %add = add i32 %slice, 6230 call void @llvm.aarch64.sme.fp8.fmlal.multi.za16.vg2x2(i32 %add,231 <vscale x 16 x i8> %zn0, <vscale x 16 x i8> %zn1,232 <vscale x 16 x i8> %zm0, <vscale x 16 x i8> %zm1)233 ret void234}235 236define void @test_fmlal_multi_vg2x4(i32 %slice, <vscale x 16 x i8> %zn0, <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zn3,237; CHECK-LABEL: test_fmlal_multi_vg2x4:238; CHECK: // %bb.0:239; CHECK: mov w8, w0240; CHECK: fmlal za.h[w8, 0:1, vgx4], { z0.b - z3.b }, { z4.b - z7.b }241; CHECK: fmlal za.h[w8, 6:7, vgx4], { z0.b - z3.b }, { z4.b - z7.b }242; CHECK: ret243 <vscale x 16 x i8> %zm0, <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2, <vscale x 16 x i8> %zm3) {244 call void @llvm.aarch64.sme.fp8.fmlal.multi.za16.vg2x4(i32 %slice,245 <vscale x 16 x i8> %zn0, <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zn3,246 <vscale x 16 x i8> %zm0, <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2, <vscale x 16 x i8> %zm3)247 %add = add i32 %slice, 6248 call void @llvm.aarch64.sme.fp8.fmlal.multi.za16.vg2x4(i32 %add,249 <vscale x 16 x i8> %zn0, <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zn3,250 <vscale x 16 x i8> %zm0, <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2, <vscale x 16 x i8> %zm3)251 ret void252}253 254; FMLALL (multi)255 256define void @test_fmlal_multi_vg4x2(i32 %slice, <vscale x 16 x i8> %zn0, <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zm0, <vscale x 16 x i8> %zm1) {257; CHECK-LABEL: test_fmlal_multi_vg4x2:258; CHECK: // %bb.0:259; CHECK: mov w8, w0260; CHECK: fmlall za.s[w8, 0:3, vgx2], { z0.b, z1.b }, { z2.b, z3.b }261; CHECK: fmlall za.s[w8, 4:7, vgx2], { z0.b, z1.b }, { z2.b, z3.b }262; CHECK: ret263 call void @llvm.aarch64.sme.fp8.fmlall.multi.za32.vg4x2(i32 %slice,264 <vscale x 16 x i8> %zn0, <vscale x 16 x i8> %zn1,265 <vscale x 16 x i8> %zm0, <vscale x 16 x i8> %zm1)266 %add = add i32 %slice, 4267 call void @llvm.aarch64.sme.fp8.fmlall.multi.za32.vg4x2(i32 %add,268 <vscale x 16 x i8> %zn0, <vscale x 16 x i8> %zn1,269 <vscale x 16 x i8> %zm0, <vscale x 16 x i8> %zm1)270 ret void271}272 273define void @test_fmlal_multi_vg4x4(i32 %slice, <vscale x 16 x i8> %zn0, <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zn3,274; CHECK-LABEL: test_fmlal_multi_vg4x4:275; CHECK: // %bb.0:276; CHECK: mov w8, w0277; CHECK: fmlall za.s[w8, 0:3, vgx4], { z0.b - z3.b }, { z4.b - z7.b }278; CHECK: fmlall za.s[w8, 4:7, vgx4], { z0.b - z3.b }, { z4.b - z7.b }279; CHECK: ret280 <vscale x 16 x i8> %zm0, <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2, <vscale x 16 x i8> %zm3) {281 call void @llvm.aarch64.sme.fp8.fmlall.multi.za32.vg4x4(i32 %slice,282 <vscale x 16 x i8> %zn0, <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zn3,283 <vscale x 16 x i8> %zm0, <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2, <vscale x 16 x i8> %zm3)284 %add = add i32 %slice, 4285 call void @llvm.aarch64.sme.fp8.fmlall.multi.za32.vg4x4(i32 %add,286 <vscale x 16 x i8> %zn0, <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zn3,287 <vscale x 16 x i8> %zm0, <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2, <vscale x 16 x i8> %zm3)288 ret void289}290