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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 42; RUN: llc -force-streaming -verify-machineinstrs < %s | FileCheck %s3 4target triple = "aarch64-linux"5 6define void @add_f16_vg1x2(i32 %slice, <vscale x 8 x half> %zn0, <vscale x 8 x half> %zn1) #0 {7; CHECK-LABEL: add_f16_vg1x2:8; CHECK: // %bb.0:9; CHECK-NEXT: // kill: def $z1 killed $z1 killed $z0_z1 def $z0_z110; CHECK-NEXT: mov w8, w011; CHECK-NEXT: // kill: def $z0 killed $z0 killed $z0_z1 def $z0_z112; CHECK-NEXT: fadd za.h[w8, 0, vgx2], { z0.h, z1.h }13; CHECK-NEXT: fadd za.h[w8, 7, vgx2], { z0.h, z1.h }14; CHECK-NEXT: ret15 call void @llvm.aarch64.sme.add.za16.vg1x2.nxv8f16(i32 %slice, <vscale x 8 x half> %zn0, <vscale x 8 x half> %zn1)16 %slice.7 = add i32 %slice, 717 call void @llvm.aarch64.sme.add.za16.vg1x2.nxv8f16(i32 %slice.7, <vscale x 8 x half> %zn0, <vscale x 8 x half> %zn1)18 ret void19}20 21define void @add_f16_vg1x4(i32 %slice, <vscale x 8 x half> %zn0, <vscale x 8 x half> %zn1,22; CHECK-LABEL: add_f16_vg1x4:23; CHECK: // %bb.0:24; CHECK-NEXT: // kill: def $z3 killed $z3 killed $z0_z1_z2_z3 def $z0_z1_z2_z325; CHECK-NEXT: mov w8, w026; CHECK-NEXT: // kill: def $z2 killed $z2 killed $z0_z1_z2_z3 def $z0_z1_z2_z327; CHECK-NEXT: // kill: def $z1 killed $z1 killed $z0_z1_z2_z3 def $z0_z1_z2_z328; CHECK-NEXT: // kill: def $z0 killed $z0 killed $z0_z1_z2_z3 def $z0_z1_z2_z329; CHECK-NEXT: fadd za.h[w8, 0, vgx4], { z0.h - z3.h }30; CHECK-NEXT: fadd za.h[w8, 7, vgx4], { z0.h - z3.h }31; CHECK-NEXT: ret32 <vscale x 8 x half> %zn2, <vscale x 8 x half> %zn3) #1 {33 call void @llvm.aarch64.sme.add.za16.vg1x4.nxv8f16(i32 %slice, <vscale x 8 x half> %zn0, <vscale x 8 x half> %zn1,34 <vscale x 8 x half> %zn2, <vscale x 8 x half> %zn3);35 %slice.7 = add i32 %slice, 736 call void @llvm.aarch64.sme.add.za16.vg1x4.nxv8f16(i32 %slice.7, <vscale x 8 x half> %zn0, <vscale x 8 x half> %zn1,37 <vscale x 8 x half> %zn2, <vscale x 8 x half> %zn3);38 ret void39}40 41define void @sub_f16_vg1x2(i32 %slice, <vscale x 8 x half> %zn0, <vscale x 8 x half> %zn1) #1 {42; CHECK-LABEL: sub_f16_vg1x2:43; CHECK: // %bb.0:44; CHECK-NEXT: // kill: def $z1 killed $z1 killed $z0_z1 def $z0_z145; CHECK-NEXT: mov w8, w046; CHECK-NEXT: // kill: def $z0 killed $z0 killed $z0_z1 def $z0_z147; CHECK-NEXT: fsub za.h[w8, 0, vgx2], { z0.h, z1.h }48; CHECK-NEXT: fsub za.h[w8, 7, vgx2], { z0.h, z1.h }49; CHECK-NEXT: ret50 call void @llvm.aarch64.sme.sub.za16.vg1x2.nxv8f16(i32 %slice, <vscale x 8 x half> %zn0, <vscale x 8 x half> %zn1)51 %slice.7 = add i32 %slice, 752 call void @llvm.aarch64.sme.sub.za16.vg1x2.nxv8f16(i32 %slice.7, <vscale x 8 x half> %zn0, <vscale x 8 x half> %zn1)53 ret void54}55 56define void @sub_f16_vg1x4(i32 %slice, <vscale x 8 x half> %zn0, <vscale x 8 x half> %zn1,57; CHECK-LABEL: sub_f16_vg1x4:58; CHECK: // %bb.0:59; CHECK-NEXT: // kill: def $z3 killed $z3 killed $z0_z1_z2_z3 def $z0_z1_z2_z360; CHECK-NEXT: mov w8, w061; CHECK-NEXT: // kill: def $z2 killed $z2 killed $z0_z1_z2_z3 def $z0_z1_z2_z362; CHECK-NEXT: // kill: def $z1 killed $z1 killed $z0_z1_z2_z3 def $z0_z1_z2_z363; CHECK-NEXT: // kill: def $z0 killed $z0 killed $z0_z1_z2_z3 def $z0_z1_z2_z364; CHECK-NEXT: fsub za.h[w8, 0, vgx4], { z0.h - z3.h }65; CHECK-NEXT: fsub za.h[w8, 7, vgx4], { z0.h - z3.h }66; CHECK-NEXT: ret67 <vscale x 8 x half> %zn2, <vscale x 8 x half> %zn3) #0 {68 call void @llvm.aarch64.sme.sub.za16.vg1x4.nxv8f16(i32 %slice, <vscale x 8 x half> %zn0, <vscale x 8 x half> %zn1,69 <vscale x 8 x half> %zn2, <vscale x 8 x half> %zn3);70 %slice.7 = add i32 %slice, 771 call void @llvm.aarch64.sme.sub.za16.vg1x4.nxv8f16(i32 %slice.7, <vscale x 8 x half> %zn0, <vscale x 8 x half> %zn1,72 <vscale x 8 x half> %zn2, <vscale x 8 x half> %zn3);73 ret void74}75 76define void @add_bf16_vg1x2(i32 %slice, <vscale x 8 x bfloat> %zn0, <vscale x 8 x bfloat> %zn1) #2 {77; CHECK-LABEL: add_bf16_vg1x2:78; CHECK: // %bb.0:79; CHECK-NEXT: // kill: def $z1 killed $z1 killed $z0_z1 def $z0_z180; CHECK-NEXT: mov w8, w081; CHECK-NEXT: // kill: def $z0 killed $z0 killed $z0_z1 def $z0_z182; CHECK-NEXT: bfadd za.h[w8, 0, vgx2], { z0.h, z1.h }83; CHECK-NEXT: bfadd za.h[w8, 7, vgx2], { z0.h, z1.h }84; CHECK-NEXT: ret85 call void @llvm.aarch64.sme.add.za16.vg1x2.nxv8bf16(i32 %slice, <vscale x 8 x bfloat> %zn0, <vscale x 8 x bfloat> %zn1)86 %slice.7 = add i32 %slice, 787 call void @llvm.aarch64.sme.add.za16.vg1x2.nxv8bf16(i32 %slice.7, <vscale x 8 x bfloat> %zn0, <vscale x 8 x bfloat> %zn1)88 ret void89}90 91define void @add_bf16_vg1x4(i32 %slice, <vscale x 8 x bfloat> %zn0, <vscale x 8 x bfloat> %zn1,92; CHECK-LABEL: add_bf16_vg1x4:93; CHECK: // %bb.0:94; CHECK-NEXT: // kill: def $z3 killed $z3 killed $z0_z1_z2_z3 def $z0_z1_z2_z395; CHECK-NEXT: mov w8, w096; CHECK-NEXT: // kill: def $z2 killed $z2 killed $z0_z1_z2_z3 def $z0_z1_z2_z397; CHECK-NEXT: // kill: def $z1 killed $z1 killed $z0_z1_z2_z3 def $z0_z1_z2_z398; CHECK-NEXT: // kill: def $z0 killed $z0 killed $z0_z1_z2_z3 def $z0_z1_z2_z399; CHECK-NEXT: bfadd za.h[w8, 0, vgx4], { z0.h - z3.h }100; CHECK-NEXT: bfadd za.h[w8, 7, vgx4], { z0.h - z3.h }101; CHECK-NEXT: ret102 <vscale x 8 x bfloat> %zn2, <vscale x 8 x bfloat> %zn3) #2 {103 call void @llvm.aarch64.sme.add.za16.vg1x4.nxv8bf16(i32 %slice, <vscale x 8 x bfloat> %zn0, <vscale x 8 x bfloat> %zn1,104 <vscale x 8 x bfloat> %zn2, <vscale x 8 x bfloat> %zn3);105 %slice.7 = add i32 %slice, 7106 call void @llvm.aarch64.sme.add.za16.vg1x4.nxv8bf16(i32 %slice.7, <vscale x 8 x bfloat> %zn0, <vscale x 8 x bfloat> %zn1,107 <vscale x 8 x bfloat> %zn2, <vscale x 8 x bfloat> %zn3);108 ret void109}110 111define void @sub_bf16_vg1x2(i32 %slice, <vscale x 8 x bfloat> %zn0, <vscale x 8 x bfloat> %zn1) #2 {112; CHECK-LABEL: sub_bf16_vg1x2:113; CHECK: // %bb.0:114; CHECK-NEXT: // kill: def $z1 killed $z1 killed $z0_z1 def $z0_z1115; CHECK-NEXT: mov w8, w0116; CHECK-NEXT: // kill: def $z0 killed $z0 killed $z0_z1 def $z0_z1117; CHECK-NEXT: bfsub za.h[w8, 0, vgx2], { z0.h, z1.h }118; CHECK-NEXT: bfsub za.h[w8, 7, vgx2], { z0.h, z1.h }119; CHECK-NEXT: ret120 call void @llvm.aarch64.sme.sub.za16.vg1x2.nxv8bf16(i32 %slice, <vscale x 8 x bfloat> %zn0, <vscale x 8 x bfloat> %zn1)121 %slice.7 = add i32 %slice, 7122 call void @llvm.aarch64.sme.sub.za16.vg1x2.nxv8bf16(i32 %slice.7, <vscale x 8 x bfloat> %zn0, <vscale x 8 x bfloat> %zn1)123 ret void124}125 126define void @sub_bf16_vg1x4(i32 %slice, <vscale x 8 x bfloat> %zn0, <vscale x 8 x bfloat> %zn1,127; CHECK-LABEL: sub_bf16_vg1x4:128; CHECK: // %bb.0:129; CHECK-NEXT: // kill: def $z3 killed $z3 killed $z0_z1_z2_z3 def $z0_z1_z2_z3130; CHECK-NEXT: mov w8, w0131; CHECK-NEXT: // kill: def $z2 killed $z2 killed $z0_z1_z2_z3 def $z0_z1_z2_z3132; CHECK-NEXT: // kill: def $z1 killed $z1 killed $z0_z1_z2_z3 def $z0_z1_z2_z3133; CHECK-NEXT: // kill: def $z0 killed $z0 killed $z0_z1_z2_z3 def $z0_z1_z2_z3134; CHECK-NEXT: bfsub za.h[w8, 0, vgx4], { z0.h - z3.h }135; CHECK-NEXT: bfsub za.h[w8, 7, vgx4], { z0.h - z3.h }136; CHECK-NEXT: ret137 <vscale x 8 x bfloat> %zn2, <vscale x 8 x bfloat> %zn3) #2 {138 call void @llvm.aarch64.sme.sub.za16.vg1x4.nxv8bf16(i32 %slice, <vscale x 8 x bfloat> %zn0, <vscale x 8 x bfloat> %zn1,139 <vscale x 8 x bfloat> %zn2, <vscale x 8 x bfloat> %zn3);140 %slice.7 = add i32 %slice, 7141 call void @llvm.aarch64.sme.sub.za16.vg1x4.nxv8bf16(i32 %slice.7, <vscale x 8 x bfloat> %zn0, <vscale x 8 x bfloat> %zn1,142 <vscale x 8 x bfloat> %zn2, <vscale x 8 x bfloat> %zn3);143 ret void144}145 146attributes #0 = { nounwind "target-features"="+sme-f16f16" }147attributes #1 = { nounwind "target-features"="+sme-f8f16" }148attributes #2 = { nounwind "target-features"="+sme-b16b16,+bf16" }149