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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme-f16f16 -force-streaming -verify-machineinstrs < %s | FileCheck %s3 4;5; FCVT6;7 8define <vscale x 8 x half> @multi_vector_cvt_x2_f16(<vscale x 4 x float> %unused, <vscale x 4 x float> %zn1, <vscale x 4 x float> %zn2) {9; CHECK-LABEL: multi_vector_cvt_x2_f16:10; CHECK: // %bb.0:11; CHECK-NEXT: mov z3.d, z2.d12; CHECK-NEXT: mov z2.d, z1.d13; CHECK-NEXT: fcvt z0.h, { z2.s, z3.s }14; CHECK-NEXT: ret15 %res = call <vscale x 8 x half> @llvm.aarch64.sve.fcvt.x2.nxv4f32(<vscale x 4 x float> %zn1, <vscale x 4 x float> %zn2)16 ret <vscale x 8 x half> %res17}18 19;20; BFCVT21;22 23define <vscale x 8 x bfloat> @multi_vector_cvt_x2_bf16(<vscale x 4 x float> %unused, <vscale x 4 x float> %zn1, <vscale x 4 x float> %zn2) {24; CHECK-LABEL: multi_vector_cvt_x2_bf16:25; CHECK: // %bb.0:26; CHECK-NEXT: mov z3.d, z2.d27; CHECK-NEXT: mov z2.d, z1.d28; CHECK-NEXT: bfcvt z0.h, { z2.s, z3.s }29; CHECK-NEXT: ret30 %res = call <vscale x 8 x bfloat> @llvm.aarch64.sve.bfcvt.x2(<vscale x 4 x float> %zn1, <vscale x 4 x float> %zn2)31 ret <vscale x 8 x bfloat> %res32}33 34;35; FCVTZS36;37define {<vscale x 4 x i32>, <vscale x 4 x i32>} @multi_vector_cvt_x2_s32_f32(<vscale x 4 x float> %unused, <vscale x 4 x float> %zn0, <vscale x 4 x float> %zn1) {38; CHECK-LABEL: multi_vector_cvt_x2_s32_f32:39; CHECK: // %bb.0:40; CHECK-NEXT: mov z3.d, z2.d41; CHECK-NEXT: mov z2.d, z1.d42; CHECK-NEXT: fcvtzs { z0.s, z1.s }, { z2.s, z3.s }43; CHECK-NEXT: ret44 %res = call {<vscale x 4 x i32>, <vscale x 4 x i32>} @llvm.aarch64.sve.fcvtzs.x2.nxv4i32.nxv4f32(<vscale x 4 x float> %zn0, <vscale x 4 x float> %zn1)45 ret {<vscale x 4 x i32>, <vscale x 4 x i32>} %res46}47 48define {<vscale x 4 x i32>, <vscale x 4 x i32>,<vscale x 4 x i32>, <vscale x 4 x i32>} @multi_vector_cvt_x4_s32_f32(<vscale x 4 x float> %unused, <vscale x 4 x float> %zn0, <vscale x 4 x float> %zn1, <vscale x 4 x float> %zn2, <vscale x 4 x float> %zn3) {49; CHECK-LABEL: multi_vector_cvt_x4_s32_f32:50; CHECK: // %bb.0:51; CHECK-NEXT: mov z7.d, z4.d52; CHECK-NEXT: mov z6.d, z3.d53; CHECK-NEXT: mov z5.d, z2.d54; CHECK-NEXT: mov z4.d, z1.d55; CHECK-NEXT: fcvtzs { z0.s - z3.s }, { z4.s - z7.s }56; CHECK-NEXT: ret57 %res = call {<vscale x 4 x i32>, <vscale x 4 x i32>,<vscale x 4 x i32>, <vscale x 4 x i32>} @llvm.aarch64.sve.fcvtzs.x4.nxv4i32.nxv4f32(<vscale x 4 x float> %zn0, <vscale x 4 x float> %zn1, <vscale x 4 x float> %zn2, <vscale x 4 x float> %zn3)58 ret {<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>} %res59}60 61;62; FCVTZU63;64define {<vscale x 4 x i32>, <vscale x 4 x i32>} @multi_vector_cvt_x2_u32_f32(<vscale x 4 x float> %unused, <vscale x 4 x float> %zn0, <vscale x 4 x float> %zn1) {65; CHECK-LABEL: multi_vector_cvt_x2_u32_f32:66; CHECK: // %bb.0:67; CHECK-NEXT: mov z3.d, z2.d68; CHECK-NEXT: mov z2.d, z1.d69; CHECK-NEXT: fcvtzu { z0.s, z1.s }, { z2.s, z3.s }70; CHECK-NEXT: ret71 %res = call {<vscale x 4 x i32>, <vscale x 4 x i32>} @llvm.aarch64.sve.fcvtzu.x2.nxv4i32.nxv4f32(<vscale x 4 x float> %zn0, <vscale x 4 x float> %zn1)72 ret {<vscale x 4 x i32>, <vscale x 4 x i32>} %res73}74 75define {<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>} @multi_vector_cvt_x4_u32_f32(<vscale x 4 x float> %unused, <vscale x 4 x float> %zn0, <vscale x 4 x float> %zn1, <vscale x 4 x float> %zn2, <vscale x 4 x float> %zn3) {76; CHECK-LABEL: multi_vector_cvt_x4_u32_f32:77; CHECK: // %bb.0:78; CHECK-NEXT: mov z7.d, z4.d79; CHECK-NEXT: mov z6.d, z3.d80; CHECK-NEXT: mov z5.d, z2.d81; CHECK-NEXT: mov z4.d, z1.d82; CHECK-NEXT: fcvtzu { z0.s - z3.s }, { z4.s - z7.s }83; CHECK-NEXT: ret84 %res = call {<vscale x 4 x i32>, <vscale x 4 x i32>,<vscale x 4 x i32>, <vscale x 4 x i32>} @llvm.aarch64.sve.fcvtzu.x4.nxv4i32.nxv4f32(<vscale x 4 x float> %zn0, <vscale x 4 x float> %zn1, <vscale x 4 x float> %zn2, <vscale x 4 x float> %zn3)85 ret {<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>} %res86}87 88;89; SCVTF90;91define {<vscale x 4 x float>, <vscale x 4 x float>} @multi_vector_cvt_x2_f32_s32(<vscale x 4 x i32> %unused, <vscale x 4 x i32> %zn0, <vscale x 4 x i32> %zn1) {92; CHECK-LABEL: multi_vector_cvt_x2_f32_s32:93; CHECK: // %bb.0:94; CHECK-NEXT: mov z3.d, z2.d95; CHECK-NEXT: mov z2.d, z1.d96; CHECK-NEXT: scvtf { z0.s, z1.s }, { z2.s, z3.s }97; CHECK-NEXT: ret98 %res = call {<vscale x 4 x float>, <vscale x 4 x float>} @llvm.aarch64.sve.scvtf.x2.nxv4f32.nxv4i32(<vscale x 4 x i32> %zn0, <vscale x 4 x i32> %zn1)99 ret {<vscale x 4 x float>, <vscale x 4 x float>} %res100}101 102define {<vscale x 4 x float>, <vscale x 4 x float>,<vscale x 4 x float>, <vscale x 4 x float>} @multi_vector_cvt_x4_f32_s32(<vscale x 4 x i32> %unused, <vscale x 4 x i32> %zn0, <vscale x 4 x i32> %zn1, <vscale x 4 x i32> %zn2, <vscale x 4 x i32> %zn3) {103; CHECK-LABEL: multi_vector_cvt_x4_f32_s32:104; CHECK: // %bb.0:105; CHECK-NEXT: mov z7.d, z4.d106; CHECK-NEXT: mov z6.d, z3.d107; CHECK-NEXT: mov z5.d, z2.d108; CHECK-NEXT: mov z4.d, z1.d109; CHECK-NEXT: scvtf { z0.s - z3.s }, { z4.s - z7.s }110; CHECK-NEXT: ret111 %res = call {<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>} @llvm.aarch64.sve.scvtf.x4.nxv4f32.nxv4i32(<vscale x 4 x i32> %zn0, <vscale x 4 x i32> %zn1, <vscale x 4 x i32> %zn2, <vscale x 4 x i32> %zn3)112 ret {<vscale x 4 x float>, <vscale x 4 x float>,<vscale x 4 x float>, <vscale x 4 x float>} %res113}114 115;116; UCVTF117;118define {<vscale x 4 x float>, <vscale x 4 x float>} @multi_vector_cvt_x2_f32_u32(<vscale x 4 x i32> %unused, <vscale x 4 x i32> %zn0, <vscale x 4 x i32> %zn1) {119; CHECK-LABEL: multi_vector_cvt_x2_f32_u32:120; CHECK: // %bb.0:121; CHECK-NEXT: mov z3.d, z2.d122; CHECK-NEXT: mov z2.d, z1.d123; CHECK-NEXT: ucvtf { z0.s, z1.s }, { z2.s, z3.s }124; CHECK-NEXT: ret125 %res = call {<vscale x 4 x float>, <vscale x 4 x float>} @llvm.aarch64.sve.ucvtf.x2.nxv4f32.nxv4i32(<vscale x 4 x i32> %zn0, <vscale x 4 x i32> %zn1)126 ret {<vscale x 4 x float>, <vscale x 4 x float>} %res127}128 129define {<vscale x 4 x float>, <vscale x 4 x float>,<vscale x 4 x float>, <vscale x 4 x float>} @multi_vector_cvt_x4_f32_u32(<vscale x 4 x i32> %unused, <vscale x 4 x i32> %zn0, <vscale x 4 x i32> %zn1,<vscale x 4 x i32> %zn2, <vscale x 4 x i32> %zn3) {130; CHECK-LABEL: multi_vector_cvt_x4_f32_u32:131; CHECK: // %bb.0:132; CHECK-NEXT: mov z7.d, z4.d133; CHECK-NEXT: mov z6.d, z3.d134; CHECK-NEXT: mov z5.d, z2.d135; CHECK-NEXT: mov z4.d, z1.d136; CHECK-NEXT: ucvtf { z0.s - z3.s }, { z4.s - z7.s }137; CHECK-NEXT: ret138 %res = call {<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>} @llvm.aarch64.sve.ucvtf.x4.nxv4f32.nxv4i32(<vscale x 4 x i32> %zn0, <vscale x 4 x i32> %zn1, <vscale x 4 x i32> %zn2, <vscale x 4 x i32> %zn3)139 ret {<vscale x 4 x float>, <vscale x 4 x float>,<vscale x 4 x float>, <vscale x 4 x float>} %res140}141 142define {<vscale x 4 x float>, <vscale x 4 x float>} @multi_vector_cvt_widen_x2_f16(<vscale x 8 x half> %zn0) {143; CHECK-LABEL: multi_vector_cvt_widen_x2_f16:144; CHECK: // %bb.0:145; CHECK-NEXT: fcvt { z0.s, z1.s }, z0.h146; CHECK-NEXT: ret147 %res = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.fcvt.widen.x2.nxv4f32(<vscale x 8 x half> %zn0)148 ret {<vscale x 4 x float>, <vscale x 4 x float>} %res149}150 151declare <vscale x 8 x half> @llvm.aarch64.sve.fcvt.x2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>)152declare <vscale x 8 x bfloat> @llvm.aarch64.sve.bfcvt.x2(<vscale x 4 x float>, <vscale x 4 x float>)153declare {<vscale x 4 x i32>, <vscale x 4 x i32>} @llvm.aarch64.sve.fcvtzs.x2.nxv4i32.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>)154declare {<vscale x 4 x i32>, <vscale x 4 x i32>} @llvm.aarch64.sve.fcvtzu.x2.nxv4i32.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>)155declare {<vscale x 4 x float>, <vscale x 4 x float>} @llvm.aarch64.sve.scvtf.x2.nxv4f32.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>)156declare {<vscale x 4 x float>, <vscale x 4 x float>} @llvm.aarch64.sve.ucvtf.x2.nxv4f32.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>)157declare {<vscale x 4 x i32>, <vscale x 4 x i32>,<vscale x 4 x i32>, <vscale x 4 x i32>} @llvm.aarch64.sve.fcvtzs.x4.nxv4i32.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>)158declare {<vscale x 4 x i32>, <vscale x 4 x i32>,<vscale x 4 x i32>, <vscale x 4 x i32>} @llvm.aarch64.sve.fcvtzu.x4.nxv4i32.nxv4f32(<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>,<vscale x 4 x float>)159declare {<vscale x 4 x float>, <vscale x 4 x float>,<vscale x 4 x float>, <vscale x 4 x float>} @llvm.aarch64.sve.scvtf.x4.nxv4f32.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>)160declare {<vscale x 4 x float>, <vscale x 4 x float>,<vscale x 4 x float>, <vscale x 4 x float>} @llvm.aarch64.sve.ucvtf.x4.nxv4f32.nxv4i32(<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>)161