236 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -mattr=+sme2 -mattr=+faminmax -force-streaming -verify-machineinstrs < %s | FileCheck %s3 4; FAMAX (Multi, x2)5 6define { <vscale x 8 x half>, <vscale x 8 x half> } @multi_vec_max_multi_x2_f16(<vscale x 8 x half> %unused, <vscale x 8 x half> %zdn1, <vscale x 8 x half> %zdn2, <vscale x 8 x half> %zm1, <vscale x 8 x half> %zm2) {7; CHECK-LABEL: multi_vec_max_multi_x2_f16:8; CHECK: // %bb.0:9; CHECK-NEXT: mov z7.d, z4.d10; CHECK-NEXT: mov z5.d, z2.d11; CHECK-NEXT: mov z6.d, z3.d12; CHECK-NEXT: mov z4.d, z1.d13; CHECK-NEXT: famax { z4.h, z5.h }, { z4.h, z5.h }, { z6.h, z7.h }14; CHECK-NEXT: mov z0.d, z4.d15; CHECK-NEXT: mov z1.d, z5.d16; CHECK-NEXT: ret17 %res = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.famax.x2.nxv8f16(<vscale x 8 x half> %zdn1, <vscale x 8 x half> %zdn2, <vscale x 8 x half> %zm1, <vscale x 8 x half> %zm2)18 ret { <vscale x 8 x half>, <vscale x 8 x half> } %res19}20 21define { <vscale x 4 x float>, <vscale x 4 x float> } @multi_vec_max_multi_x2_f32(<vscale x 4 x float> %unused, <vscale x 4 x float> %zdn1, <vscale x 4 x float> %zdn2, <vscale x 4 x float> %zm1, <vscale x 4 x float> %zm2) {22; CHECK-LABEL: multi_vec_max_multi_x2_f32:23; CHECK: // %bb.0:24; CHECK-NEXT: mov z7.d, z4.d25; CHECK-NEXT: mov z5.d, z2.d26; CHECK-NEXT: mov z6.d, z3.d27; CHECK-NEXT: mov z4.d, z1.d28; CHECK-NEXT: famax { z4.s, z5.s }, { z4.s, z5.s }, { z6.s, z7.s }29; CHECK-NEXT: mov z0.d, z4.d30; CHECK-NEXT: mov z1.d, z5.d31; CHECK-NEXT: ret32 %res = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sme.famax.x2.nxv4f32(<vscale x 4 x float> %zdn1, <vscale x 4 x float> %zdn2, <vscale x 4 x float> %zm1, <vscale x 4 x float> %zm2)33 ret { <vscale x 4 x float>, <vscale x 4 x float> } %res34}35 36define { <vscale x 2 x double>, <vscale x 2 x double> } @multi_vec_max_multi_x2_f64(<vscale x 2 x double> %unused, <vscale x 2 x double> %zdn1, <vscale x 2 x double> %zdn2, <vscale x 2 x double> %zm1, <vscale x 2 x double> %zm2) {37; CHECK-LABEL: multi_vec_max_multi_x2_f64:38; CHECK: // %bb.0:39; CHECK-NEXT: mov z7.d, z4.d40; CHECK-NEXT: mov z5.d, z2.d41; CHECK-NEXT: mov z6.d, z3.d42; CHECK-NEXT: mov z4.d, z1.d43; CHECK-NEXT: famax { z4.d, z5.d }, { z4.d, z5.d }, { z6.d, z7.d }44; CHECK-NEXT: mov z0.d, z4.d45; CHECK-NEXT: mov z1.d, z5.d46; CHECK-NEXT: ret47 %res = call { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sme.famax.x2.nxv2f64(<vscale x 2 x double> %zdn1, <vscale x 2 x double> %zdn2, <vscale x 2 x double> %zm1, <vscale x 2 x double> %zm2)48 ret { <vscale x 2 x double>, <vscale x 2 x double> } %res49}50 51; FAMAX (Multi, x4)52 53define { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }@multi_vec_max_multi_x4_f16(<vscale x 8 x half> %unused, <vscale x 8 x half> %zdn1, <vscale x 8 x half> %zdn2, <vscale x 8 x half> %zdn3, <vscale x 8 x half> %zdn4, <vscale x 8 x half> %zm1, <vscale x 8 x half> %zm2, <vscale x 8 x half> %zm3, <vscale x 8 x half> %zm4) {54; CHECK-LABEL: multi_vec_max_multi_x4_f16:55; CHECK: // %bb.0:56; CHECK-NEXT: mov z30.d, z7.d57; CHECK-NEXT: mov z27.d, z4.d58; CHECK-NEXT: mov z29.d, z6.d59; CHECK-NEXT: mov z26.d, z3.d60; CHECK-NEXT: mov z28.d, z5.d61; CHECK-NEXT: mov z25.d, z2.d62; CHECK-NEXT: ldr z31, [x0]63; CHECK-NEXT: mov z24.d, z1.d64; CHECK-NEXT: famax { z24.h - z27.h }, { z24.h - z27.h }, { z28.h - z31.h }65; CHECK-NEXT: mov z0.d, z24.d66; CHECK-NEXT: mov z1.d, z25.d67; CHECK-NEXT: mov z2.d, z26.d68; CHECK-NEXT: mov z3.d, z27.d69; CHECK-NEXT: ret70 %res = call { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.famax.x4.nxv8f16(<vscale x 8 x half> %zdn1, <vscale x 8 x half> %zdn2, <vscale x 8 x half> %zdn3, <vscale x 8 x half> %zdn4, <vscale x 8 x half> %zm1, <vscale x 8 x half> %zm2, <vscale x 8 x half> %zm3, <vscale x 8 x half> %zm4)71 ret { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %res72}73 74define { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @multi_vec_max_multi_x4_f32(<vscale x 4 x float> %unused, <vscale x 4 x float> %zdn1, <vscale x 4 x float> %zdn2, <vscale x 4 x float> %zdn3, <vscale x 4 x float> %zdn4, <vscale x 4 x float> %zm1, <vscale x 4 x float> %zm2, <vscale x 4 x float> %zm3, <vscale x 4 x float> %zm4) {75; CHECK-LABEL: multi_vec_max_multi_x4_f32:76; CHECK: // %bb.0:77; CHECK-NEXT: mov z30.d, z7.d78; CHECK-NEXT: mov z27.d, z4.d79; CHECK-NEXT: mov z29.d, z6.d80; CHECK-NEXT: mov z26.d, z3.d81; CHECK-NEXT: mov z28.d, z5.d82; CHECK-NEXT: mov z25.d, z2.d83; CHECK-NEXT: ldr z31, [x0]84; CHECK-NEXT: mov z24.d, z1.d85; CHECK-NEXT: famax { z24.s - z27.s }, { z24.s - z27.s }, { z28.s - z31.s }86; CHECK-NEXT: mov z0.d, z24.d87; CHECK-NEXT: mov z1.d, z25.d88; CHECK-NEXT: mov z2.d, z26.d89; CHECK-NEXT: mov z3.d, z27.d90; CHECK-NEXT: ret91 %res = call { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sme.famax.x4.nxv4f32(<vscale x 4 x float> %zdn1, <vscale x 4 x float> %zdn2, <vscale x 4 x float> %zdn3, <vscale x 4 x float> %zdn4, <vscale x 4 x float> %zm1, <vscale x 4 x float> %zm2, <vscale x 4 x float> %zm3, <vscale x 4 x float> %zm4)92 ret { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %res93}94 95define { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } @multi_vec_max_multi_x4_f64(<vscale x 2 x double> %unused, <vscale x 2 x double> %zdn1, <vscale x 2 x double> %zdn2, <vscale x 2 x double> %zdn3, <vscale x 2 x double> %zdn4, <vscale x 2 x double> %zm1, <vscale x 2 x double> %zm2, <vscale x 2 x double> %zm3, <vscale x 2 x double> %zm4) {96; CHECK-LABEL: multi_vec_max_multi_x4_f64:97; CHECK: // %bb.0:98; CHECK-NEXT: mov z30.d, z7.d99; CHECK-NEXT: mov z27.d, z4.d100; CHECK-NEXT: mov z29.d, z6.d101; CHECK-NEXT: mov z26.d, z3.d102; CHECK-NEXT: mov z28.d, z5.d103; CHECK-NEXT: mov z25.d, z2.d104; CHECK-NEXT: ldr z31, [x0]105; CHECK-NEXT: mov z24.d, z1.d106; CHECK-NEXT: famax { z24.d - z27.d }, { z24.d - z27.d }, { z28.d - z31.d }107; CHECK-NEXT: mov z0.d, z24.d108; CHECK-NEXT: mov z1.d, z25.d109; CHECK-NEXT: mov z2.d, z26.d110; CHECK-NEXT: mov z3.d, z27.d111; CHECK-NEXT: ret112 %res = call { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> }113 @llvm.aarch64.sme.famax.x4.nxv2f64(<vscale x 2 x double> %zdn1, <vscale x 2 x double> %zdn2, <vscale x 2 x double> %zdn3, <vscale x 2 x double> %zdn4,114 <vscale x 2 x double> %zm1, <vscale x 2 x double> %zm2, <vscale x 2 x double> %zm3, <vscale x 2 x double> %zm4)115 ret { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } %res116}117 118 119; FAMIN (Multi, x2)120 121define { <vscale x 8 x half>, <vscale x 8 x half> } @multi_vec_min_multi_x2_f16(<vscale x 8 x half> %unused, <vscale x 8 x half> %zdn1, <vscale x 8 x half> %zdn2, <vscale x 8 x half> %zm1, <vscale x 8 x half> %zm2) {122; CHECK-LABEL: multi_vec_min_multi_x2_f16:123; CHECK: // %bb.0:124; CHECK-NEXT: mov z7.d, z4.d125; CHECK-NEXT: mov z5.d, z2.d126; CHECK-NEXT: mov z6.d, z3.d127; CHECK-NEXT: mov z4.d, z1.d128; CHECK-NEXT: famin { z4.h, z5.h }, { z4.h, z5.h }, { z6.h, z7.h }129; CHECK-NEXT: mov z0.d, z4.d130; CHECK-NEXT: mov z1.d, z5.d131; CHECK-NEXT: ret132 %res = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sme.famin.x2.nxv8f16(<vscale x 8 x half> %zdn1, <vscale x 8 x half> %zdn2, <vscale x 8 x half> %zm1, <vscale x 8 x half> %zm2)133 ret { <vscale x 8 x half>, <vscale x 8 x half> } %res134}135 136define { <vscale x 4 x float>, <vscale x 4 x float> } @multi_vec_min_multi_x2_f32(<vscale x 4 x float> %unused, <vscale x 4 x float> %zdn1, <vscale x 4 x float> %zdn2, <vscale x 4 x float> %zm1, <vscale x 4 x float> %zm2) {137; CHECK-LABEL: multi_vec_min_multi_x2_f32:138; CHECK: // %bb.0:139; CHECK-NEXT: mov z7.d, z4.d140; CHECK-NEXT: mov z5.d, z2.d141; CHECK-NEXT: mov z6.d, z3.d142; CHECK-NEXT: mov z4.d, z1.d143; CHECK-NEXT: famin { z4.s, z5.s }, { z4.s, z5.s }, { z6.s, z7.s }144; CHECK-NEXT: mov z0.d, z4.d145; CHECK-NEXT: mov z1.d, z5.d146; CHECK-NEXT: ret147 %res = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sme.famin.x2.nxv4f32(<vscale x 4 x float> %zdn1, <vscale x 4 x float> %zdn2, <vscale x 4 x float> %zm1, <vscale x 4 x float> %zm2)148 ret { <vscale x 4 x float>, <vscale x 4 x float> } %res149}150 151define { <vscale x 2 x double>, <vscale x 2 x double> } @multi_vec_main_multi_x2_f64(<vscale x 2 x double> %unused, <vscale x 2 x double> %zdn1, <vscale x 2 x double> %zdn2, <vscale x 2 x double> %zm1, <vscale x 2 x double> %zm2) {152; CHECK-LABEL: multi_vec_main_multi_x2_f64:153; CHECK: // %bb.0:154; CHECK-NEXT: mov z7.d, z4.d155; CHECK-NEXT: mov z5.d, z2.d156; CHECK-NEXT: mov z6.d, z3.d157; CHECK-NEXT: mov z4.d, z1.d158; CHECK-NEXT: famin { z4.d, z5.d }, { z4.d, z5.d }, { z6.d, z7.d }159; CHECK-NEXT: mov z0.d, z4.d160; CHECK-NEXT: mov z1.d, z5.d161; CHECK-NEXT: ret162 %res = call { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sme.famin.x2.nxv2f64(<vscale x 2 x double> %zdn1, <vscale x 2 x double> %zdn2, <vscale x 2 x double> %zm1, <vscale x 2 x double> %zm2)163 ret { <vscale x 2 x double>, <vscale x 2 x double> } %res164}165 166; FAMIN (Multi, x4)167 168define { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @multi_vec_min_multi_x4_f16(<vscale x 8 x half> %unused, <vscale x 8 x half> %zdn1, <vscale x 8 x half> %zdn2, <vscale x 8 x half> %zdn3, <vscale x 8 x half> %zdn4, <vscale x 8 x half> %zm1, <vscale x 8 x half> %zm2, <vscale x 8 x half> %zm3, <vscale x 8 x half> %zm4) {169; CHECK-LABEL: multi_vec_min_multi_x4_f16:170; CHECK: // %bb.0:171; CHECK-NEXT: mov z30.d, z7.d172; CHECK-NEXT: mov z27.d, z4.d173; CHECK-NEXT: mov z29.d, z6.d174; CHECK-NEXT: mov z26.d, z3.d175; CHECK-NEXT: mov z28.d, z5.d176; CHECK-NEXT: mov z25.d, z2.d177; CHECK-NEXT: ldr z31, [x0]178; CHECK-NEXT: mov z24.d, z1.d179; CHECK-NEXT: famin { z24.h - z27.h }, { z24.h - z27.h }, { z28.h - z31.h }180; CHECK-NEXT: mov z0.d, z24.d181; CHECK-NEXT: mov z1.d, z25.d182; CHECK-NEXT: mov z2.d, z26.d183; CHECK-NEXT: mov z3.d, z27.d184; CHECK-NEXT: ret185 %res = call { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }186 @llvm.aarch64.sme.famin.x4.nxv8f16(<vscale x 8 x half> %zdn1, <vscale x 8 x half> %zdn2, <vscale x 8 x half> %zdn3, <vscale x 8 x half> %zdn4,187 <vscale x 8 x half> %zm1, <vscale x 8 x half> %zm2, <vscale x 8 x half> %zm3, <vscale x 8 x half> %zm4)188 ret { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %res189}190 191define { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @multi_vec_min_multi_x4_f32(<vscale x 4 x float> %unused, <vscale x 4 x float> %zdn1, <vscale x 4 x float> %zdn2, <vscale x 4 x float> %zdn3, <vscale x 4 x float> %zdn4, <vscale x 4 x float> %zm1, <vscale x 4 x float> %zm2, <vscale x 4 x float> %zm3, <vscale x 4 x float> %zm4) {192; CHECK-LABEL: multi_vec_min_multi_x4_f32:193; CHECK: // %bb.0:194; CHECK-NEXT: mov z30.d, z7.d195; CHECK-NEXT: mov z27.d, z4.d196; CHECK-NEXT: mov z29.d, z6.d197; CHECK-NEXT: mov z26.d, z3.d198; CHECK-NEXT: mov z28.d, z5.d199; CHECK-NEXT: mov z25.d, z2.d200; CHECK-NEXT: ldr z31, [x0]201; CHECK-NEXT: mov z24.d, z1.d202; CHECK-NEXT: famin { z24.s - z27.s }, { z24.s - z27.s }, { z28.s - z31.s }203; CHECK-NEXT: mov z0.d, z24.d204; CHECK-NEXT: mov z1.d, z25.d205; CHECK-NEXT: mov z2.d, z26.d206; CHECK-NEXT: mov z3.d, z27.d207; CHECK-NEXT: ret208 %res = call { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }209 @llvm.aarch64.sme.famin.x4.nxv4f32(<vscale x 4 x float> %zdn1, <vscale x 4 x float> %zdn2, <vscale x 4 x float> %zdn3, <vscale x 4 x float> %zdn4,210 <vscale x 4 x float> %zm1, <vscale x 4 x float> %zm2, <vscale x 4 x float> %zm3, <vscale x 4 x float> %zm4)211 ret { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %res212}213 214define { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } @multi_vec_min_multi_x4_f64(<vscale x 2 x double> %unused, <vscale x 2 x double> %zdn1, <vscale x 2 x double> %zdn2, <vscale x 2 x double> %zdn3, <vscale x 2 x double> %zdn4, <vscale x 2 x double> %zm1, <vscale x 2 x double> %zm2, <vscale x 2 x double> %zm3, <vscale x 2 x double> %zm4) {215; CHECK-LABEL: multi_vec_min_multi_x4_f64:216; CHECK: // %bb.0:217; CHECK-NEXT: mov z30.d, z7.d218; CHECK-NEXT: mov z27.d, z4.d219; CHECK-NEXT: mov z29.d, z6.d220; CHECK-NEXT: mov z26.d, z3.d221; CHECK-NEXT: mov z28.d, z5.d222; CHECK-NEXT: mov z25.d, z2.d223; CHECK-NEXT: ldr z31, [x0]224; CHECK-NEXT: mov z24.d, z1.d225; CHECK-NEXT: famin { z24.d - z27.d }, { z24.d - z27.d }, { z28.d - z31.d }226; CHECK-NEXT: mov z0.d, z24.d227; CHECK-NEXT: mov z1.d, z25.d228; CHECK-NEXT: mov z2.d, z26.d229; CHECK-NEXT: mov z3.d, z27.d230; CHECK-NEXT: ret231 %res = call { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> }232 @llvm.aarch64.sme.famin.x4.nxv2f64(<vscale x 2 x double> %zdn1, <vscale x 2 x double> %zdn2, <vscale x 2 x double> %zdn3, <vscale x 2 x double> %zdn4,233 <vscale x 2 x double> %zm1, <vscale x 2 x double> %zm2, <vscale x 2 x double> %zm3, <vscale x 2 x double> %zm4)234 ret { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } %res235}236