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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --filter-out "// kill:.*$" --version 42; RUN: llc -force-streaming -verify-machineinstrs < %s | FileCheck %s3 4target triple = "aarch64-linux"5 6define void @test_fmla_f16_vg2_single(i32 %slice, <vscale x 8 x half> %a0, <vscale x 8 x half> %a1, <vscale x 8 x half> %b) #0 {7; CHECK-LABEL: test_fmla_f16_vg2_single:8; CHECK: // %bb.0:9; CHECK: mov w8, w010; CHECK: fmla za.h[w8, 0, vgx2], { z0.h, z1.h }, z2.h11; CHECK: fmla za.h[w8, 7, vgx2], { z0.h, z1.h }, z2.h12; CHECK: ret13 call void @llvm.aarch64.sme.fmla.single.vg1x2.nxv8f16(i32 %slice, <vscale x 8 x half> %a0, <vscale x 8 x half> %a1, <vscale x 8 x half> %b)14 %slice.7 = add i32 %slice, 715 call void @llvm.aarch64.sme.fmla.single.vg1x2.nxv8f16(i32 %slice.7, <vscale x 8 x half> %a0, <vscale x 8 x half> %a1, <vscale x 8 x half> %b)16 ret void17}18 19define void @test_fmla_f16_vg4_single(i32 %slice, <vscale x 8 x half> %a0, <vscale x 8 x half> %a1,20; CHECK-LABEL: test_fmla_f16_vg4_single:21; CHECK: // %bb.0:22; CHECK: mov w8, w023; CHECK: fmla za.h[w8, 0, vgx4], { z0.h - z3.h }, z4.h24; CHECK: fmla za.h[w8, 7, vgx4], { z0.h - z3.h }, z4.h25; CHECK: ret26 <vscale x 8 x half> %a2, <vscale x 8 x half> %a3, <vscale x 8 x half> %b) #0 {27 call void @llvm.aarch64.sme.fmla.single.vg1x4.nxv8f16(i32 %slice, <vscale x 8 x half> %a0, <vscale x 8 x half> %a1,28 <vscale x 8 x half> %a2, <vscale x 8 x half> %a3, <vscale x 8 x half> %b)29 %slice.7 = add i32 %slice, 730 call void @llvm.aarch64.sme.fmla.single.vg1x4.nxv8f16(i32 %slice.7, <vscale x 8 x half> %a0, <vscale x 8 x half> %a1,31 <vscale x 8 x half> %a2, <vscale x 8 x half> %a3, <vscale x 8 x half> %b)32 ret void33}34 35define void @test_fmls_f16_vg2_single(i32 %slice, <vscale x 8 x half> %a0, <vscale x 8 x half> %a1, <vscale x 8 x half> %b) #0 {36; CHECK-LABEL: test_fmls_f16_vg2_single:37; CHECK: // %bb.0:38; CHECK: mov w8, w039; CHECK: fmls za.h[w8, 0, vgx2], { z0.h, z1.h }, z2.h40; CHECK: fmls za.h[w8, 7, vgx2], { z0.h, z1.h }, z2.h41; CHECK: ret42 call void @llvm.aarch64.sme.fmls.single.vg1x2.nxv8f16(i32 %slice, <vscale x 8 x half> %a0, <vscale x 8 x half> %a1, <vscale x 8 x half> %b)43 %slice.7 = add i32 %slice, 744 call void @llvm.aarch64.sme.fmls.single.vg1x2.nxv8f16(i32 %slice.7, <vscale x 8 x half> %a0, <vscale x 8 x half> %a1, <vscale x 8 x half> %b)45 ret void46}47 48define void @test_fmls_f16_vg4_single(i32 %slice, <vscale x 8 x half> %a0, <vscale x 8 x half> %a1,49; CHECK-LABEL: test_fmls_f16_vg4_single:50; CHECK: // %bb.0:51; CHECK: mov w8, w052; CHECK: fmls za.h[w8, 0, vgx4], { z0.h - z3.h }, z4.h53; CHECK: fmls za.h[w8, 7, vgx4], { z0.h - z3.h }, z4.h54; CHECK: ret55 <vscale x 8 x half> %a2, <vscale x 8 x half> %a3, <vscale x 8 x half> %b) #0 {56 call void @llvm.aarch64.sme.fmls.single.vg1x4.nxv8f16(i32 %slice, <vscale x 8 x half> %a0, <vscale x 8 x half> %a1,57 <vscale x 8 x half> %a2, <vscale x 8 x half> %a3, <vscale x 8 x half> %b)58 %slice.7 = add i32 %slice, 759 call void @llvm.aarch64.sme.fmls.single.vg1x4.nxv8f16(i32 %slice.7, <vscale x 8 x half> %a0, <vscale x 8 x half> %a1,60 <vscale x 8 x half> %a2, <vscale x 8 x half> %a3, <vscale x 8 x half> %b)61 ret void62}63 64define void @test_fmla_f16_vg2_multi(i32 %slice,65; CHECK-LABEL: test_fmla_f16_vg2_multi:66; CHECK: // %bb.0:67; CHECK: mov w8, w068; CHECK: fmla za.h[w8, 0, vgx2], { z0.h, z1.h }, { z2.h, z3.h }69; CHECK: fmla za.h[w8, 7, vgx2], { z0.h, z1.h }, { z2.h, z3.h }70; CHECK: ret71 <vscale x 8 x half> %a0, <vscale x 8 x half> %a1,72 <vscale x 8 x half> %b0, <vscale x 8 x half> %b1) #0 {73 call void @llvm.aarch64.sme.fmla.vg1x2.nxv8f16(i32 %slice,74 <vscale x 8 x half> %a0, <vscale x 8 x half> %a1,75 <vscale x 8 x half> %b0, <vscale x 8 x half> %b1)76 %slice.7 = add i32 %slice, 777 call void @llvm.aarch64.sme.fmla.vg1x2.nxv8f16(i32 %slice.7,78 <vscale x 8 x half> %a0, <vscale x 8 x half> %a1,79 <vscale x 8 x half> %b0, <vscale x 8 x half> %b1)80 ret void81}82 83define void @test_fmla_f16_vg4_multi(i32 %slice,84; CHECK-LABEL: test_fmla_f16_vg4_multi:85; CHECK: // %bb.0:86; CHECK: mov w8, w087; CHECK: fmla za.h[w8, 0, vgx4], { z0.h - z3.h }, { z4.h - z7.h }88; CHECK: fmla za.h[w8, 7, vgx4], { z0.h - z3.h }, { z4.h - z7.h }89; CHECK: ret90 <vscale x 8 x half> %a0, <vscale x 8 x half> %a1,91 <vscale x 8 x half> %a2, <vscale x 8 x half> %a3,92 <vscale x 8 x half> %b0, <vscale x 8 x half> %b1,93 <vscale x 8 x half> %b2, <vscale x 8 x half> %b3) #0 {94 call void @llvm.aarch64.sme.fmla.vg1x4.nxv8f16(i32 %slice,95 <vscale x 8 x half> %a0, <vscale x 8 x half> %a1,96 <vscale x 8 x half> %a2, <vscale x 8 x half> %a3,97 <vscale x 8 x half> %b0, <vscale x 8 x half> %b1,98 <vscale x 8 x half> %b2, <vscale x 8 x half> %b3)99 %slice.7 = add i32 %slice, 7100 call void @llvm.aarch64.sme.fmla.vg1x4.nxv8f16(i32 %slice.7,101 <vscale x 8 x half> %a0, <vscale x 8 x half> %a1,102 <vscale x 8 x half> %a2, <vscale x 8 x half> %a3,103 <vscale x 8 x half> %b0, <vscale x 8 x half> %b1,104 <vscale x 8 x half> %b2, <vscale x 8 x half> %b3)105 ret void106}107 108define void @test_fmls_f16_vg2_multi(i32 %slice,109; CHECK-LABEL: test_fmls_f16_vg2_multi:110; CHECK: // %bb.0:111; CHECK: mov w8, w0112; CHECK: fmls za.h[w8, 0, vgx2], { z0.h, z1.h }, { z2.h, z3.h }113; CHECK: fmls za.h[w8, 7, vgx2], { z0.h, z1.h }, { z2.h, z3.h }114; CHECK: ret115 <vscale x 8 x half> %a0, <vscale x 8 x half> %a1,116 <vscale x 8 x half> %b0, <vscale x 8 x half> %b1) #0 {117 call void @llvm.aarch64.sme.fmls.vg1x2.nxv8f16(i32 %slice,118 <vscale x 8 x half> %a0, <vscale x 8 x half> %a1,119 <vscale x 8 x half> %b0, <vscale x 8 x half> %b1)120 %slice.7 = add i32 %slice, 7121 call void @llvm.aarch64.sme.fmls.vg1x2.nxv8f16(i32 %slice.7,122 <vscale x 8 x half> %a0, <vscale x 8 x half> %a1,123 <vscale x 8 x half> %b0, <vscale x 8 x half> %b1)124 ret void125}126 127define void @test_fmls_f16_vg4_multi(i32 %slice,128; CHECK-LABEL: test_fmls_f16_vg4_multi:129; CHECK: // %bb.0:130; CHECK: mov w8, w0131; CHECK: fmls za.h[w8, 0, vgx4], { z0.h - z3.h }, { z4.h - z7.h }132; CHECK: fmls za.h[w8, 7, vgx4], { z0.h - z3.h }, { z4.h - z7.h }133; CHECK: ret134 <vscale x 8 x half> %a0, <vscale x 8 x half> %a1,135 <vscale x 8 x half> %a2, <vscale x 8 x half> %a3,136 <vscale x 8 x half> %b0, <vscale x 8 x half> %b1,137 <vscale x 8 x half> %b2, <vscale x 8 x half> %b3) #0 {138 call void @llvm.aarch64.sme.fmls.vg1x4.nxv8f16(i32 %slice,139 <vscale x 8 x half> %a0, <vscale x 8 x half> %a1,140 <vscale x 8 x half> %a2, <vscale x 8 x half> %a3,141 <vscale x 8 x half> %b0, <vscale x 8 x half> %b1,142 <vscale x 8 x half> %b2, <vscale x 8 x half> %b3)143 %slice.7 = add i32 %slice, 7144 call void @llvm.aarch64.sme.fmls.vg1x4.nxv8f16(i32 %slice.7,145 <vscale x 8 x half> %a0, <vscale x 8 x half> %a1,146 <vscale x 8 x half> %a2, <vscale x 8 x half> %a3,147 <vscale x 8 x half> %b0, <vscale x 8 x half> %b1,148 <vscale x 8 x half> %b2, <vscale x 8 x half> %b3)149 ret void150}151 152define void @test_fmla_f16_vg2_index(i32 %slice,153; CHECK-LABEL: test_fmla_f16_vg2_index:154; CHECK: // %bb.0:155; CHECK: mov w8, w0156; CHECK: fmla za.h[w8, 0, vgx2], { z0.h, z1.h }, z2.h[7]157; CHECK: fmla za.h[w8, 7, vgx2], { z0.h, z1.h }, z2.h[7]158; CHECK: ret159 <vscale x 8 x half> %a0, <vscale x 8 x half> %a1,160 <vscale x 8 x half> %b) #0 {161 call void @llvm.aarch64.sme.fmla.lane.vg1x2.nxv8f16(i32 %slice,162 <vscale x 8 x half> %a0, <vscale x 8 x half> %a1,163 <vscale x 8 x half> %b, i32 7);164 %slice.7 = add i32 %slice, 7165 call void @llvm.aarch64.sme.fmla.lane.vg1x2.nxv8f16(i32 %slice.7,166 <vscale x 8 x half> %a0, <vscale x 8 x half> %a1,167 <vscale x 8 x half> %b, i32 7);168 ret void169}170 171define void @test_fmla_f16_vg4_index(i32 %slice,172; CHECK-LABEL: test_fmla_f16_vg4_index:173; CHECK: // %bb.0:174; CHECK: mov w8, w0175; CHECK: fmla za.h[w8, 0, vgx4], { z0.h - z3.h }, z4.h[7]176; CHECK: fmla za.h[w8, 0, vgx4], { z0.h - z3.h }, z4.h[7]177; CHECK: ret178 <vscale x 8 x half> %a0, <vscale x 8 x half> %a1,179 <vscale x 8 x half> %a2, <vscale x 8 x half> %a3,180 <vscale x 8 x half> %b) #0 {181 call void @llvm.aarch64.sme.fmla.lane.vg1x4.nxv8f16(i32 %slice,182 <vscale x 8 x half> %a0, <vscale x 8 x half> %a1,183 <vscale x 8 x half> %a2, <vscale x 8 x half> %a3,184 <vscale x 8 x half> %b, i32 7);185 %slice.7 = add i32 %slice, 7186 call void @llvm.aarch64.sme.fmla.lane.vg1x4.nxv8f16(i32 %slice,187 <vscale x 8 x half> %a0, <vscale x 8 x half> %a1,188 <vscale x 8 x half> %a2, <vscale x 8 x half> %a3,189 <vscale x 8 x half> %b, i32 7);190 ret void191}192 193define void @test_fmls_f16_vg2_index(i32 %slice,194; CHECK-LABEL: test_fmls_f16_vg2_index:195; CHECK: // %bb.0:196; CHECK: mov w8, w0197; CHECK: fmls za.h[w8, 0, vgx2], { z0.h, z1.h }, z2.h[7]198; CHECK: fmls za.h[w8, 7, vgx2], { z0.h, z1.h }, z2.h[7]199; CHECK: ret200 <vscale x 8 x half> %a0, <vscale x 8 x half> %a1,201 <vscale x 8 x half> %b) #0 {202 call void @llvm.aarch64.sme.fmls.lane.vg1x2.nxv8f16(i32 %slice,203 <vscale x 8 x half> %a0, <vscale x 8 x half> %a1,204 <vscale x 8 x half> %b, i32 7);205 %slice.7 = add i32 %slice, 7206 call void @llvm.aarch64.sme.fmls.lane.vg1x2.nxv8f16(i32 %slice.7,207 <vscale x 8 x half> %a0, <vscale x 8 x half> %a1,208 <vscale x 8 x half> %b, i32 7);209 ret void210}211 212define void @test_fmls_f16_vg4_index(i32 %slice,213; CHECK-LABEL: test_fmls_f16_vg4_index:214; CHECK: // %bb.0:215; CHECK: mov w8, w0216; CHECK: fmls za.h[w8, 0, vgx4], { z0.h - z3.h }, z4.h[7]217; CHECK: fmls za.h[w8, 0, vgx4], { z0.h - z3.h }, z4.h[7]218; CHECK: ret219 <vscale x 8 x half> %a0, <vscale x 8 x half> %a1,220 <vscale x 8 x half> %a2, <vscale x 8 x half> %a3,221 <vscale x 8 x half> %b) #0 {222 call void @llvm.aarch64.sme.fmls.lane.vg1x4.nxv8f16(i32 %slice,223 <vscale x 8 x half> %a0, <vscale x 8 x half> %a1,224 <vscale x 8 x half> %a2, <vscale x 8 x half> %a3,225 <vscale x 8 x half> %b, i32 7);226 %slice.7 = add i32 %slice, 7227 call void @llvm.aarch64.sme.fmls.lane.vg1x4.nxv8f16(i32 %slice,228 <vscale x 8 x half> %a0, <vscale x 8 x half> %a1,229 <vscale x 8 x half> %a2, <vscale x 8 x half> %a3,230 <vscale x 8 x half> %b, i32 7);231 ret void232}233 234define void @test_fmla_bf16_vg2_single(i32 %slice, <vscale x 8 x bfloat> %a0, <vscale x 8 x bfloat> %a1, <vscale x 8 x bfloat> %b) #0 {235; CHECK-LABEL: test_fmla_bf16_vg2_single:236; CHECK: // %bb.0:237; CHECK: mov w8, w0238; CHECK: bfmla za.h[w8, 0, vgx2], { z0.h, z1.h }, z2.h239; CHECK: bfmla za.h[w8, 7, vgx2], { z0.h, z1.h }, z2.h240; CHECK: ret241 call void @llvm.aarch64.sme.fmla.single.vg1x2.nxv8bf16(i32 %slice, <vscale x 8 x bfloat> %a0, <vscale x 8 x bfloat> %a1, <vscale x 8 x bfloat> %b)242 %slice.7 = add i32 %slice, 7243 call void @llvm.aarch64.sme.fmla.single.vg1x2.nxv8bf16(i32 %slice.7, <vscale x 8 x bfloat> %a0, <vscale x 8 x bfloat> %a1, <vscale x 8 x bfloat> %b)244 ret void245}246 247define void @test_fmla_bf16_vg4_single(i32 %slice, <vscale x 8 x bfloat> %a0, <vscale x 8 x bfloat> %a1,248; CHECK-LABEL: test_fmla_bf16_vg4_single:249; CHECK: // %bb.0:250; CHECK: mov w8, w0251; CHECK: bfmla za.h[w8, 0, vgx4], { z0.h - z3.h }, z4.h252; CHECK: bfmla za.h[w8, 7, vgx4], { z0.h - z3.h }, z4.h253; CHECK: ret254 <vscale x 8 x bfloat> %a2, <vscale x 8 x bfloat> %a3, <vscale x 8 x bfloat> %b) #0 {255 call void @llvm.aarch64.sme.fmla.single.vg1x4.nxv8bf16(i32 %slice, <vscale x 8 x bfloat> %a0, <vscale x 8 x bfloat> %a1,256 <vscale x 8 x bfloat> %a2, <vscale x 8 x bfloat> %a3, <vscale x 8 x bfloat> %b)257 %slice.7 = add i32 %slice, 7258 call void @llvm.aarch64.sme.fmla.single.vg1x4.nxv8bf16(i32 %slice.7, <vscale x 8 x bfloat> %a0, <vscale x 8 x bfloat> %a1,259 <vscale x 8 x bfloat> %a2, <vscale x 8 x bfloat> %a3, <vscale x 8 x bfloat> %b)260 ret void261}262 263define void @test_fmls_bf16_vg2_single(i32 %slice, <vscale x 8 x bfloat> %a0, <vscale x 8 x bfloat> %a1, <vscale x 8 x bfloat> %b) #0 {264; CHECK-LABEL: test_fmls_bf16_vg2_single:265; CHECK: // %bb.0:266; CHECK: mov w8, w0267; CHECK: bfmls za.h[w8, 0, vgx2], { z0.h, z1.h }, z2.h268; CHECK: bfmls za.h[w8, 7, vgx2], { z0.h, z1.h }, z2.h269; CHECK: ret270 call void @llvm.aarch64.sme.fmls.single.vg1x2.nxv8bf16(i32 %slice, <vscale x 8 x bfloat> %a0, <vscale x 8 x bfloat> %a1, <vscale x 8 x bfloat> %b)271 %slice.7 = add i32 %slice, 7272 call void @llvm.aarch64.sme.fmls.single.vg1x2.nxv8bf16(i32 %slice.7, <vscale x 8 x bfloat> %a0, <vscale x 8 x bfloat> %a1, <vscale x 8 x bfloat> %b)273 ret void274}275 276define void @test_fmls_bf16_vg4_single(i32 %slice, <vscale x 8 x bfloat> %a0, <vscale x 8 x bfloat> %a1,277; CHECK-LABEL: test_fmls_bf16_vg4_single:278; CHECK: // %bb.0:279; CHECK: mov w8, w0280; CHECK: bfmls za.h[w8, 0, vgx4], { z0.h - z3.h }, z4.h281; CHECK: bfmls za.h[w8, 7, vgx4], { z0.h - z3.h }, z4.h282; CHECK: ret283 <vscale x 8 x bfloat> %a2, <vscale x 8 x bfloat> %a3, <vscale x 8 x bfloat> %b) #0 {284 call void @llvm.aarch64.sme.fmls.single.vg1x4.nxv8bf16(i32 %slice, <vscale x 8 x bfloat> %a0, <vscale x 8 x bfloat> %a1,285 <vscale x 8 x bfloat> %a2, <vscale x 8 x bfloat> %a3, <vscale x 8 x bfloat> %b)286 %slice.7 = add i32 %slice, 7287 call void @llvm.aarch64.sme.fmls.single.vg1x4.nxv8bf16(i32 %slice.7, <vscale x 8 x bfloat> %a0, <vscale x 8 x bfloat> %a1,288 <vscale x 8 x bfloat> %a2, <vscale x 8 x bfloat> %a3, <vscale x 8 x bfloat> %b)289 ret void290}291 292define void @test_fmla_bf16_vg2_multi(i32 %slice,293; CHECK-LABEL: test_fmla_bf16_vg2_multi:294; CHECK: // %bb.0:295; CHECK: mov w8, w0296; CHECK: bfmla za.h[w8, 0, vgx2], { z0.h, z1.h }, { z2.h, z3.h }297; CHECK: bfmla za.h[w8, 7, vgx2], { z0.h, z1.h }, { z2.h, z3.h }298; CHECK: ret299 <vscale x 8 x bfloat> %a0, <vscale x 8 x bfloat> %a1,300 <vscale x 8 x bfloat> %b0, <vscale x 8 x bfloat> %b1) #0 {301 call void @llvm.aarch64.sme.fmla.vg1x2.nxv8bf16(i32 %slice,302 <vscale x 8 x bfloat> %a0, <vscale x 8 x bfloat> %a1,303 <vscale x 8 x bfloat> %b0, <vscale x 8 x bfloat> %b1)304 %slice.7 = add i32 %slice, 7305 call void @llvm.aarch64.sme.fmla.vg1x2.nxv8bf16(i32 %slice.7,306 <vscale x 8 x bfloat> %a0, <vscale x 8 x bfloat> %a1,307 <vscale x 8 x bfloat> %b0, <vscale x 8 x bfloat> %b1)308 ret void309}310 311define void @test_fmla_bf16_vg4_multi(i32 %slice,312; CHECK-LABEL: test_fmla_bf16_vg4_multi:313; CHECK: // %bb.0:314; CHECK: mov w8, w0315; CHECK: bfmla za.h[w8, 0, vgx4], { z0.h - z3.h }, { z4.h - z7.h }316; CHECK: bfmla za.h[w8, 7, vgx4], { z0.h - z3.h }, { z4.h - z7.h }317; CHECK: ret318 <vscale x 8 x bfloat> %a0, <vscale x 8 x bfloat> %a1,319 <vscale x 8 x bfloat> %a2, <vscale x 8 x bfloat> %a3,320 <vscale x 8 x bfloat> %b0, <vscale x 8 x bfloat> %b1,321 <vscale x 8 x bfloat> %b2, <vscale x 8 x bfloat> %b3) #0 {322 call void @llvm.aarch64.sme.fmla.vg1x4.nxv8bf16(i32 %slice,323 <vscale x 8 x bfloat> %a0, <vscale x 8 x bfloat> %a1,324 <vscale x 8 x bfloat> %a2, <vscale x 8 x bfloat> %a3,325 <vscale x 8 x bfloat> %b0, <vscale x 8 x bfloat> %b1,326 <vscale x 8 x bfloat> %b2, <vscale x 8 x bfloat> %b3)327 %slice.7 = add i32 %slice, 7328 call void @llvm.aarch64.sme.fmla.vg1x4.nxv8bf16(i32 %slice.7,329 <vscale x 8 x bfloat> %a0, <vscale x 8 x bfloat> %a1,330 <vscale x 8 x bfloat> %a2, <vscale x 8 x bfloat> %a3,331 <vscale x 8 x bfloat> %b0, <vscale x 8 x bfloat> %b1,332 <vscale x 8 x bfloat> %b2, <vscale x 8 x bfloat> %b3)333 ret void334}335 336define void @test_fmls_bf16_vg2_multi(i32 %slice,337; CHECK-LABEL: test_fmls_bf16_vg2_multi:338; CHECK: // %bb.0:339; CHECK: mov w8, w0340; CHECK: bfmls za.h[w8, 0, vgx2], { z0.h, z1.h }, { z2.h, z3.h }341; CHECK: bfmls za.h[w8, 7, vgx2], { z0.h, z1.h }, { z2.h, z3.h }342; CHECK: ret343 <vscale x 8 x bfloat> %a0, <vscale x 8 x bfloat> %a1,344 <vscale x 8 x bfloat> %b0, <vscale x 8 x bfloat> %b1) #0 {345 call void @llvm.aarch64.sme.fmls.vg1x2.nxv8bf16(i32 %slice,346 <vscale x 8 x bfloat> %a0, <vscale x 8 x bfloat> %a1,347 <vscale x 8 x bfloat> %b0, <vscale x 8 x bfloat> %b1)348 %slice.7 = add i32 %slice, 7349 call void @llvm.aarch64.sme.fmls.vg1x2.nxv8bf16(i32 %slice.7,350 <vscale x 8 x bfloat> %a0, <vscale x 8 x bfloat> %a1,351 <vscale x 8 x bfloat> %b0, <vscale x 8 x bfloat> %b1)352 ret void353}354 355define void @test_fmls_bf16_vg4_multi(i32 %slice,356; CHECK-LABEL: test_fmls_bf16_vg4_multi:357; CHECK: // %bb.0:358; CHECK: mov w8, w0359; CHECK: bfmls za.h[w8, 0, vgx4], { z0.h - z3.h }, { z4.h - z7.h }360; CHECK: bfmls za.h[w8, 7, vgx4], { z0.h - z3.h }, { z4.h - z7.h }361; CHECK: ret362 <vscale x 8 x bfloat> %a0, <vscale x 8 x bfloat> %a1,363 <vscale x 8 x bfloat> %a2, <vscale x 8 x bfloat> %a3,364 <vscale x 8 x bfloat> %b0, <vscale x 8 x bfloat> %b1,365 <vscale x 8 x bfloat> %b2, <vscale x 8 x bfloat> %b3) #0 {366 call void @llvm.aarch64.sme.fmls.vg1x4.nxv8bf16(i32 %slice,367 <vscale x 8 x bfloat> %a0, <vscale x 8 x bfloat> %a1,368 <vscale x 8 x bfloat> %a2, <vscale x 8 x bfloat> %a3,369 <vscale x 8 x bfloat> %b0, <vscale x 8 x bfloat> %b1,370 <vscale x 8 x bfloat> %b2, <vscale x 8 x bfloat> %b3)371 %slice.7 = add i32 %slice, 7372 call void @llvm.aarch64.sme.fmls.vg1x4.nxv8bf16(i32 %slice.7,373 <vscale x 8 x bfloat> %a0, <vscale x 8 x bfloat> %a1,374 <vscale x 8 x bfloat> %a2, <vscale x 8 x bfloat> %a3,375 <vscale x 8 x bfloat> %b0, <vscale x 8 x bfloat> %b1,376 <vscale x 8 x bfloat> %b2, <vscale x 8 x bfloat> %b3)377 ret void378}379 380define void @test_fmla_bf16_vg2_index(i32 %slice,381; CHECK-LABEL: test_fmla_bf16_vg2_index:382; CHECK: // %bb.0:383; CHECK: mov w8, w0384; CHECK: bfmla za.h[w8, 0, vgx2], { z0.h, z1.h }, z2.h[7]385; CHECK: bfmla za.h[w8, 7, vgx2], { z0.h, z1.h }, z2.h[7]386; CHECK: ret387 <vscale x 8 x bfloat> %a0, <vscale x 8 x bfloat> %a1,388 <vscale x 8 x bfloat> %b) #0 {389 call void @llvm.aarch64.sme.fmla.lane.vg1x2.nxv8bf16(i32 %slice,390 <vscale x 8 x bfloat> %a0, <vscale x 8 x bfloat> %a1,391 <vscale x 8 x bfloat> %b, i32 7);392 %slice.7 = add i32 %slice, 7393 call void @llvm.aarch64.sme.fmla.lane.vg1x2.nxv8bf16(i32 %slice.7,394 <vscale x 8 x bfloat> %a0, <vscale x 8 x bfloat> %a1,395 <vscale x 8 x bfloat> %b, i32 7);396 ret void397}398 399define void @test_fmla_bf16_vg4_index(i32 %slice,400; CHECK-LABEL: test_fmla_bf16_vg4_index:401; CHECK: // %bb.0:402; CHECK: mov w8, w0403; CHECK: bfmla za.h[w8, 0, vgx4], { z0.h - z3.h }, z4.h[7]404; CHECK: bfmla za.h[w8, 0, vgx4], { z0.h - z3.h }, z4.h[7]405; CHECK: ret406 <vscale x 8 x bfloat> %a0, <vscale x 8 x bfloat> %a1,407 <vscale x 8 x bfloat> %a2, <vscale x 8 x bfloat> %a3,408 <vscale x 8 x bfloat> %b) #0 {409 call void @llvm.aarch64.sme.fmla.lane.vg1x4.nxv8bf16(i32 %slice,410 <vscale x 8 x bfloat> %a0, <vscale x 8 x bfloat> %a1,411 <vscale x 8 x bfloat> %a2, <vscale x 8 x bfloat> %a3,412 <vscale x 8 x bfloat> %b, i32 7);413 %slice.7 = add i32 %slice, 7414 call void @llvm.aarch64.sme.fmla.lane.vg1x4.nxv8bf16(i32 %slice,415 <vscale x 8 x bfloat> %a0, <vscale x 8 x bfloat> %a1,416 <vscale x 8 x bfloat> %a2, <vscale x 8 x bfloat> %a3,417 <vscale x 8 x bfloat> %b, i32 7);418 ret void419}420 421define void @test_fmls_bf16_vg2_index(i32 %slice,422; CHECK-LABEL: test_fmls_bf16_vg2_index:423; CHECK: // %bb.0:424; CHECK: mov w8, w0425; CHECK: bfmls za.h[w8, 0, vgx2], { z0.h, z1.h }, z2.h[7]426; CHECK: bfmls za.h[w8, 7, vgx2], { z0.h, z1.h }, z2.h[7]427; CHECK: ret428 <vscale x 8 x bfloat> %a0, <vscale x 8 x bfloat> %a1,429 <vscale x 8 x bfloat> %b) #0 {430 call void @llvm.aarch64.sme.fmls.lane.vg1x2.nxv8bf16(i32 %slice,431 <vscale x 8 x bfloat> %a0, <vscale x 8 x bfloat> %a1,432 <vscale x 8 x bfloat> %b, i32 7);433 %slice.7 = add i32 %slice, 7434 call void @llvm.aarch64.sme.fmls.lane.vg1x2.nxv8bf16(i32 %slice.7,435 <vscale x 8 x bfloat> %a0, <vscale x 8 x bfloat> %a1,436 <vscale x 8 x bfloat> %b, i32 7);437 ret void438}439 440define void @test_fmls_bf16_vg4_index(i32 %slice,441; CHECK-LABEL: test_fmls_bf16_vg4_index:442; CHECK: // %bb.0:443; CHECK: mov w8, w0444; CHECK: bfmls za.h[w8, 0, vgx4], { z0.h - z3.h }, z4.h[7]445; CHECK: bfmls za.h[w8, 0, vgx4], { z0.h - z3.h }, z4.h[7]446; CHECK: ret447 <vscale x 8 x bfloat> %a0, <vscale x 8 x bfloat> %a1,448 <vscale x 8 x bfloat> %a2, <vscale x 8 x bfloat> %a3,449 <vscale x 8 x bfloat> %b) #0 {450 call void @llvm.aarch64.sme.fmls.lane.vg1x4.nxv8bf16(i32 %slice,451 <vscale x 8 x bfloat> %a0, <vscale x 8 x bfloat> %a1,452 <vscale x 8 x bfloat> %a2, <vscale x 8 x bfloat> %a3,453 <vscale x 8 x bfloat> %b, i32 7);454 %slice.7 = add i32 %slice, 7455 call void @llvm.aarch64.sme.fmls.lane.vg1x4.nxv8bf16(i32 %slice,456 <vscale x 8 x bfloat> %a0, <vscale x 8 x bfloat> %a1,457 <vscale x 8 x bfloat> %a2, <vscale x 8 x bfloat> %a3,458 <vscale x 8 x bfloat> %b, i32 7);459 ret void460}461 462attributes #0 = { nounwind "target-features"="+sme2p1,+sme-f16f16,+sme-b16b16" }463