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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --filter-out "^[ \t]*//.*$" --version 42; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme2,+sme-f8f16,+sme-f8f32 -verify-machineinstrs -force-streaming < %s | FileCheck %s3 4target triple = "aarch64-linux"5 6define void @test_fdot16_1x2_indexed(i32 %slice.0, <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zm) #0 {7; CHECK-LABEL: test_fdot16_1x2_indexed:8; CHECK: mov w8, w09; CHECK: fdot za.h[w8, 7, vgx2], { z0.b, z1.b }, z2.b[1]10; CHECK: ret11 %slice = add i32 %slice.0, 712 call void @llvm.aarch64.sme.fp8.fdot.lane.za16.vg1x2(i32 %slice,13 <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2,14 <vscale x 16 x i8> %zm, i32 1)15 ret void16}17 18define void @test_fdot16_1x4_indexed(i32 %slice.0, <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zn3, <vscale x 16 x i8> %zn4,19; CHECK-LABEL: test_fdot16_1x4_indexed:20; CHECK: mov w8, w021; CHECK: fdot za.h[w8, 7, vgx4], { z0.b - z3.b }, z4.b[1]22; CHECK: ret23 <vscale x 16 x i8> %zm) #0 {24 %slice = add i32 %slice.0, 725 call void @llvm.aarch64.sme.fp8.fdot.lane.za16.vg1x4(i32 %slice,26 <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zn3, <vscale x 16 x i8> %zn4,27 <vscale x 16 x i8> %zm, i32 1)28 ret void29}30 31define void @test_fdot32_1x2_indexed(i32 %slice.0,32; CHECK-LABEL: test_fdot32_1x2_indexed:33; CHECK: mov w8, w034; CHECK: fdot za.s[w8, 7, vgx2], { z0.b, z1.b }, z2.b[1]35; CHECK: ret36 <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2,37 <vscale x 16 x i8> %zm) #0 {38 %slice = add i32 %slice.0, 739 call void @llvm.aarch64.sme.fp8.fdot.lane.za32.vg1x2(i32 %slice,40 <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2,41 <vscale x 16 x i8> %zm, i32 1)42 ret void43}44 45define void @test_fdot32_1x4_indexed(i32 %slice.0,46; CHECK-LABEL: test_fdot32_1x4_indexed:47; CHECK: mov w8, w048; CHECK: fdot za.s[w8, 7, vgx4], { z0.b - z3.b }, z4.b[1]49; CHECK: ret50 <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zn3, <vscale x 16 x i8> %zn4,51 <vscale x 16 x i8> %zm) #0 {52 %slice = add i32 %slice.0, 753 call void @llvm.aarch64.sme.fp8.fdot.lane.za32.vg1x4(i32 %slice,54 <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zn3, <vscale x 16 x i8> %zn4,55 <vscale x 16 x i8> %zm, i32 1)56 ret void57}58 59define void @test_fdot32_1x2_single(i32 %slice.0,60; CHECK-LABEL: test_fdot32_1x2_single:61; CHECK: mov w8, w062; CHECK: fdot za.s[w8, 7, vgx2], { z0.b, z1.b }, z2.b63; CHECK: ret64 <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2,65 <vscale x 16 x i8> %zm) #0 {66 %slice = add i32 %slice.0, 767 call void @llvm.aarch64.sme.fp8.fdot.single.za32.vg1x2(i32 %slice,68 <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2,69 <vscale x 16 x i8> %zm)70 ret void71}72 73define void @test_fdot32_1x4_single(i32 %slice.0,74; CHECK-LABEL: test_fdot32_1x4_single:75; CHECK: mov w8, w076; CHECK: fdot za.s[w8, 7, vgx4], { z0.b - z3.b }, z4.b77; CHECK: ret78 <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zn3, <vscale x 16 x i8> %zn4,79 <vscale x 16 x i8> %zm) #0 {80 %slice = add i32 %slice.0, 781 call void @llvm.aarch64.sme.fp8.fdot.single.za32.vg1x4(i32 %slice,82 <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zn3, <vscale x 16 x i8> %zn4,83 <vscale x 16 x i8> %zm)84 ret void85}86 87define void @test_fdot32_1x2_multi(i32 %slice.0,88; CHECK-LABEL: test_fdot32_1x2_multi:89; CHECK: mov w8, w090; CHECK: fdot za.s[w8, 7, vgx2], { z0.b, z1.b }, { z2.b, z3.b }91; CHECK: ret92 <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2,93 <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2) #0 {94 %slice = add i32 %slice.0, 795 call void @llvm.aarch64.sme.fp8.fdot.multi.za32.vg1x2(i32 %slice,96 <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2,97 <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2)98 ret void99}100 101define void @test_fdot32_1x4_multi(i32 %slice.0,102; CHECK-LABEL: test_fdot32_1x4_multi:103; CHECK: mov w8, w0104; CHECK: fdot za.s[w8, 7, vgx4], { z0.b - z3.b }, { z4.b - z7.b }105; CHECK: ret106 <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zn3, <vscale x 16 x i8> %zn4,107 <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2, <vscale x 16 x i8> %zm3, <vscale x 16 x i8> %zm4) #0 {108 %slice = add i32 %slice.0, 7109 call void @llvm.aarch64.sme.fp8.fdot.multi.za32.vg1x4(i32 %slice,110 <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zn3, <vscale x 16 x i8> %zn4,111 <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2, <vscale x 16 x i8> %zm3, <vscale x 16 x i8> %zm4)112 ret void113}114 115define void @test_fdot16_1x2_single(i32 %slice.0,116; CHECK-LABEL: test_fdot16_1x2_single:117; CHECK: mov w8, w0118; CHECK: fdot za.h[w8, 7, vgx2], { z0.b, z1.b }, z2.b119; CHECK: ret120 <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2,121 <vscale x 16 x i8> %zm) #0 {122 %slice = add i32 %slice.0, 7123 call void @llvm.aarch64.sme.fp8.fdot.single.za16.vg1x2(i32 %slice,124 <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2,125 <vscale x 16 x i8> %zm)126 ret void127}128 129define void @test_fdot16_1x4_single(i32 %slice.0,130; CHECK-LABEL: test_fdot16_1x4_single:131; CHECK: mov w8, w0132; CHECK: fdot za.h[w8, 7, vgx4], { z0.b - z3.b }, z4.b133; CHECK: ret134 <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zn3, <vscale x 16 x i8> %zn4,135 <vscale x 16 x i8> %zm) #0 {136 %slice = add i32 %slice.0, 7137 call void @llvm.aarch64.sme.fp8.fdot.single.za16.vg1x4(i32 %slice,138 <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zn3, <vscale x 16 x i8> %zn4,139 <vscale x 16 x i8> %zm)140 ret void141}142 143define void @test_fdot16_1x2_multi(i32 %slice.0,144; CHECK-LABEL: test_fdot16_1x2_multi:145; CHECK: mov w8, w0146; CHECK: fdot za.h[w8, 7, vgx2], { z0.b, z1.b }, { z2.b, z3.b }147; CHECK: ret148 <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2,149 <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2) #0 {150 %slice = add i32 %slice.0, 7151 call void @llvm.aarch64.sme.fp8.fdot.multi.za16.vg1x2(i32 %slice,152 <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2,153 <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2)154 ret void155}156 157define void @test_fdot16_1x4_multi(i32 %slice.0,158; CHECK-LABEL: test_fdot16_1x4_multi:159; CHECK: mov w8, w0160; CHECK: fdot za.h[w8, 7, vgx4], { z0.b - z3.b }, { z4.b - z7.b }161; CHECK: ret162 <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zn3, <vscale x 16 x i8> %zn4,163 <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2, <vscale x 16 x i8> %zm3, <vscale x 16 x i8> %zm4) #0 {164 %slice = add i32 %slice.0, 7165 call void @llvm.aarch64.sme.fp8.fdot.multi.za16.vg1x4(i32 %slice,166 <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zn3, <vscale x 16 x i8> %zn4,167 <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2, <vscale x 16 x i8> %zm3, <vscale x 16 x i8> %zm4)168 ret void169}170 171attributes #0 = { "target-features" = "+sme,+sme-f8f32,+sme-f8f16" }172