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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --filter-out "// kill:" --version 42; RUN: llc -force-streaming < %s | FileCheck %s3target triple = "aarch64-linux"4 5define void @test_fvdot16_1x2_indexed(i32 %slice.0,6; CHECK-LABEL: test_fvdot16_1x2_indexed:7; CHECK: // %bb.0:8; CHECK: mov w8, w09; CHECK: fvdot za.h[w8, 7, vgx2], { z0.b, z1.b }, z2.b[3]10; CHECK: ret11 <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2,12 <vscale x 16 x i8> %zm) #0 {13 %slice = add i32 %slice.0, 714 call void @llvm.aarch64.sme.fp8.fvdot.lane.za16.vg1x2(i32 %slice,15 <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2,16 <vscale x 16 x i8> %zm, i32 3)17 ret void18}19 20define void @test_fvdot32_bottom_1x4_indexed(i32 %slice.0,21; CHECK-LABEL: test_fvdot32_bottom_1x4_indexed:22; CHECK: // %bb.0:23; CHECK: mov w8, w024; CHECK: fvdotb za.s[w8, 7, vgx4], { z0.b, z1.b }, z2.b[3]25; CHECK: ret26 <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2,27 <vscale x 16 x i8> %zm) #0 {28 %slice = add i32 %slice.0, 729 call void @llvm.aarch64.sme.fp8.fvdotb.lane.za32.vg1x4(i32 %slice,30 <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2,31 <vscale x 16 x i8> %zm, i32 3)32 ret void33}34 35define void @test_fvdot32_top_1x4_indexed(i32 %slice.0,36; CHECK-LABEL: test_fvdot32_top_1x4_indexed:37; CHECK: // %bb.0:38; CHECK: mov w8, w039; CHECK: fvdott za.s[w8, 7, vgx4], { z0.b, z1.b }, z2.b[3]40; CHECK: ret41 <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2,42 <vscale x 16 x i8> %zm) #0 {43 %slice = add i32 %slice.0, 744 call void @llvm.aarch64.sme.fp8.fvdott.lane.za32.vg1x4(i32 %slice,45 <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2,46 <vscale x 16 x i8> %zm, i32 3)47 ret void48}49 50attributes #0 = { "target-features" = "+sme-f8f32,+sme-f8f16" }51