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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -verify-machineinstrs -force-streaming < %s | FileCheck %s3 4target triple = "aarch64-linux"5 6define {<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>} @test_luti4_zt_i8(<vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1) #0 {7; CHECK-LABEL: test_luti4_zt_i8:8; CHECK: // %bb.0:9; CHECK-NEXT: // kill: def $z1 killed $z1 killed $z0_z1 def $z0_z110; CHECK-NEXT: // kill: def $z0 killed $z0 killed $z0_z1 def $z0_z111; CHECK-NEXT: luti4 { z0.b - z3.b }, zt0, { z0, z1 }12; CHECK-NEXT: ret13 %res = call {<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>} @llvm.aarch64.sme.luti4.zt.x4.nxv16i8(i32 0, <vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1)14 ret {<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>} %res15}16 17; Tests multiple identical luti4 intrinsics with ZT0 loads interspersed, are not CSD'd.18define void @test_multiple_luti4_zt_i8(ptr %ptrA, ptr %ptrB, <vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1) #0 {19; CHECK-LABEL: test_multiple_luti4_zt_i8:20; CHECK: // %bb.0:21; CHECK-NEXT: ldr zt0, [x0]22; CHECK-NEXT: // kill: def $z1 killed $z1 killed $z0_z1 def $z0_z123; CHECK-NEXT: // kill: def $z0 killed $z0 killed $z0_z1 def $z0_z124; CHECK-NEXT: luti4 { z4.b - z7.b }, zt0, { z0, z1 }25; CHECK-NEXT: // fake_use: $z4 $z4_z5_z6_z726; CHECK-NEXT: ldr zt0, [x1]27; CHECK-NEXT: luti4 { z0.b - z3.b }, zt0, { z0, z1 }28; CHECK-NEXT: // fake_use: $z0 $z0_z1_z2_z329; CHECK-NEXT: ret30 tail call void @llvm.aarch64.sme.ldr.zt(i32 0, ptr %ptrA)31 %res1 = call {<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>} @llvm.aarch64.sme.luti4.zt.x4.nxv16i8(i32 0, <vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1)32 tail call void @llvm.aarch64.sme.ldr.zt(i32 0, ptr %ptrB)33 %res2 = call {<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>} @llvm.aarch64.sme.luti4.zt.x4.nxv16i8(i32 0, <vscale x 16 x i8> %v0, <vscale x 16 x i8> %v1)34 35 call void (...) @llvm.fake.use({ <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %res1)36 call void (...) @llvm.fake.use({ <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %res2)37 ret void38}39 40attributes #0 = { "target-features"="+sme2,+sme-lutv2"}41