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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 42; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme2 -mattr=+sve-b16b16 -force-streaming -verify-machineinstrs < %s | FileCheck %s3 4; SMIN (Single, x2)5 6define { <vscale x 16 x i8>, <vscale x 16 x i8> } @multi_vec_min_single_x2_s8(<vscale x 16 x i8> %unused, <vscale x 16 x i8> %zdn1, <vscale x 16 x i8> %zdn2, <vscale x 16 x i8> %zm) {7; CHECK-LABEL: multi_vec_min_single_x2_s8:8; CHECK: // %bb.0:9; CHECK-NEXT: mov z5.d, z2.d10; CHECK-NEXT: mov z4.d, z1.d11; CHECK-NEXT: smin { z4.b, z5.b }, { z4.b, z5.b }, z3.b12; CHECK-NEXT: mov z0.d, z4.d13; CHECK-NEXT: mov z1.d, z5.d14; CHECK-NEXT: ret15 %res = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.smin.single.x2.nxv16i8(<vscale x 16 x i8> %zdn1, <vscale x 16 x i8> %zdn2, <vscale x 16 x i8> %zm)16 ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %res17}18 19define { <vscale x 8 x i16>, <vscale x 8 x i16> } @multi_vec_min_single_x2_s16(<vscale x 8 x i16> %unused, <vscale x 8 x i16> %zdn1, <vscale x 8 x i16> %zdn2, <vscale x 8 x i16> %zm) {20; CHECK-LABEL: multi_vec_min_single_x2_s16:21; CHECK: // %bb.0:22; CHECK-NEXT: mov z5.d, z2.d23; CHECK-NEXT: mov z4.d, z1.d24; CHECK-NEXT: smin { z4.h, z5.h }, { z4.h, z5.h }, z3.h25; CHECK-NEXT: mov z0.d, z4.d26; CHECK-NEXT: mov z1.d, z5.d27; CHECK-NEXT: ret28 %res = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.smin.single.x2.nxv8i16(<vscale x 8 x i16> %zdn1, <vscale x 8 x i16> %zdn2, <vscale x 8 x i16> %zm)29 ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %res30}31 32define { <vscale x 4 x i32>, <vscale x 4 x i32> } @multi_vec_min_single_x2_s32(<vscale x 4 x i32> %unused, <vscale x 4 x i32> %zdn1, <vscale x 4 x i32> %zdn2, <vscale x 4 x i32> %zm) {33; CHECK-LABEL: multi_vec_min_single_x2_s32:34; CHECK: // %bb.0:35; CHECK-NEXT: mov z5.d, z2.d36; CHECK-NEXT: mov z4.d, z1.d37; CHECK-NEXT: smin { z4.s, z5.s }, { z4.s, z5.s }, z3.s38; CHECK-NEXT: mov z0.d, z4.d39; CHECK-NEXT: mov z1.d, z5.d40; CHECK-NEXT: ret41 %res = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.smin.single.x2.nxv4i32(<vscale x 4 x i32> %zdn1, <vscale x 4 x i32> %zdn2, <vscale x 4 x i32> %zm)42 ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %res43}44 45define { <vscale x 2 x i64>, <vscale x 2 x i64> } @multi_vec_min_single_x2_s64(<vscale x 2 x i64> %unused, <vscale x 2 x i64> %zdn1, <vscale x 2 x i64> %zdn2, <vscale x 2 x i64> %zm) {46; CHECK-LABEL: multi_vec_min_single_x2_s64:47; CHECK: // %bb.0:48; CHECK-NEXT: mov z5.d, z2.d49; CHECK-NEXT: mov z4.d, z1.d50; CHECK-NEXT: smin { z4.d, z5.d }, { z4.d, z5.d }, z3.d51; CHECK-NEXT: mov z0.d, z4.d52; CHECK-NEXT: mov z1.d, z5.d53; CHECK-NEXT: ret54 %res = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.smin.single.x2.nxv2i64(<vscale x 2 x i64> %zdn1, <vscale x 2 x i64> %zdn2, <vscale x 2 x i64> %zm)55 ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %res56}57 58; UMIN (Single, x2)59 60define { <vscale x 16 x i8>, <vscale x 16 x i8> } @multi_vec_min_single_x2_u8(<vscale x 16 x i8> %unused, <vscale x 16 x i8> %zdn1, <vscale x 16 x i8> %zdn2, <vscale x 16 x i8> %zm) {61; CHECK-LABEL: multi_vec_min_single_x2_u8:62; CHECK: // %bb.0:63; CHECK-NEXT: mov z5.d, z2.d64; CHECK-NEXT: mov z4.d, z1.d65; CHECK-NEXT: umin { z4.b, z5.b }, { z4.b, z5.b }, z3.b66; CHECK-NEXT: mov z0.d, z4.d67; CHECK-NEXT: mov z1.d, z5.d68; CHECK-NEXT: ret69 %res = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.umin.single.x2.nxv16i8(<vscale x 16 x i8> %zdn1, <vscale x 16 x i8> %zdn2, <vscale x 16 x i8> %zm)70 ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %res71}72 73define { <vscale x 8 x i16>, <vscale x 8 x i16> } @multi_vec_min_single_x2_u16(<vscale x 8 x i16> %unused, <vscale x 8 x i16> %zdn1, <vscale x 8 x i16> %zdn2, <vscale x 8 x i16> %zm) {74; CHECK-LABEL: multi_vec_min_single_x2_u16:75; CHECK: // %bb.0:76; CHECK-NEXT: mov z5.d, z2.d77; CHECK-NEXT: mov z4.d, z1.d78; CHECK-NEXT: umin { z4.h, z5.h }, { z4.h, z5.h }, z3.h79; CHECK-NEXT: mov z0.d, z4.d80; CHECK-NEXT: mov z1.d, z5.d81; CHECK-NEXT: ret82 %res = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.umin.single.x2.nxv8i16(<vscale x 8 x i16> %zdn1, <vscale x 8 x i16> %zdn2, <vscale x 8 x i16> %zm)83 ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %res84}85 86define { <vscale x 4 x i32>, <vscale x 4 x i32> } @multi_vec_min_single_x2_u32(<vscale x 4 x i32> %unused, <vscale x 4 x i32> %zdn1, <vscale x 4 x i32> %zdn2, <vscale x 4 x i32> %zm) {87; CHECK-LABEL: multi_vec_min_single_x2_u32:88; CHECK: // %bb.0:89; CHECK-NEXT: mov z5.d, z2.d90; CHECK-NEXT: mov z4.d, z1.d91; CHECK-NEXT: umin { z4.s, z5.s }, { z4.s, z5.s }, z3.s92; CHECK-NEXT: mov z0.d, z4.d93; CHECK-NEXT: mov z1.d, z5.d94; CHECK-NEXT: ret95 %res = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.umin.single.x2.nxv4i32(<vscale x 4 x i32> %zdn1, <vscale x 4 x i32> %zdn2, <vscale x 4 x i32> %zm)96 ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %res97}98 99define { <vscale x 2 x i64>, <vscale x 2 x i64> } @multi_vec_min_single_x2_u64(<vscale x 2 x i64> %unused, <vscale x 2 x i64> %zdn1, <vscale x 2 x i64> %zdn2, <vscale x 2 x i64> %zm) {100; CHECK-LABEL: multi_vec_min_single_x2_u64:101; CHECK: // %bb.0:102; CHECK-NEXT: mov z5.d, z2.d103; CHECK-NEXT: mov z4.d, z1.d104; CHECK-NEXT: umin { z4.d, z5.d }, { z4.d, z5.d }, z3.d105; CHECK-NEXT: mov z0.d, z4.d106; CHECK-NEXT: mov z1.d, z5.d107; CHECK-NEXT: ret108 %res = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.umin.single.x2.nxv2i64(<vscale x 2 x i64> %zdn1, <vscale x 2 x i64> %zdn2, <vscale x 2 x i64> %zm)109 ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %res110}111 112; BFMIN (Single, x2)113 114define { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @multi_vec_min_single_x2_bf16(<vscale x 8 x bfloat> %zdn1, <vscale x 8 x bfloat> %zdn2, <vscale x 8 x bfloat> %zm) {115; CHECK-LABEL: multi_vec_min_single_x2_bf16:116; CHECK: // %bb.0:117; CHECK-NEXT: // kill: def $z1 killed $z1 killed $z0_z1 def $z0_z1118; CHECK-NEXT: // kill: def $z0 killed $z0 killed $z0_z1 def $z0_z1119; CHECK-NEXT: bfmin { z0.h, z1.h }, { z0.h, z1.h }, z2.h120; CHECK-NEXT: ret121 %res = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fmin.single.x2.nxv8bf16(<vscale x 8 x bfloat> %zdn1, <vscale x 8 x bfloat> %zdn2, <vscale x 8 x bfloat> %zm)122 ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %res123}124 125; FMIN (Single, x2)126 127define { <vscale x 8 x half>, <vscale x 8 x half> } @multi_vec_min_single_x2_f16(<vscale x 8 x half> %unused, <vscale x 8 x half> %zdn1, <vscale x 8 x half> %zdn2, <vscale x 8 x half> %zm) {128; CHECK-LABEL: multi_vec_min_single_x2_f16:129; CHECK: // %bb.0:130; CHECK-NEXT: mov z5.d, z2.d131; CHECK-NEXT: mov z4.d, z1.d132; CHECK-NEXT: fmin { z4.h, z5.h }, { z4.h, z5.h }, z3.h133; CHECK-NEXT: mov z0.d, z4.d134; CHECK-NEXT: mov z1.d, z5.d135; CHECK-NEXT: ret136 %res = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.fmin.single.x2.nxv8f16(<vscale x 8 x half> %zdn1, <vscale x 8 x half> %zdn2, <vscale x 8 x half> %zm)137 ret { <vscale x 8 x half>, <vscale x 8 x half> } %res138}139 140define { <vscale x 4 x float>, <vscale x 4 x float> } @multi_vec_min_single_x2_f32(<vscale x 4 x float> %unused, <vscale x 4 x float> %zdn1, <vscale x 4 x float> %zdn2, <vscale x 4 x float> %zm) {141; CHECK-LABEL: multi_vec_min_single_x2_f32:142; CHECK: // %bb.0:143; CHECK-NEXT: mov z5.d, z2.d144; CHECK-NEXT: mov z4.d, z1.d145; CHECK-NEXT: fmin { z4.s, z5.s }, { z4.s, z5.s }, z3.s146; CHECK-NEXT: mov z0.d, z4.d147; CHECK-NEXT: mov z1.d, z5.d148; CHECK-NEXT: ret149 %res = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.fmin.single.x2.nxv4f32(<vscale x 4 x float> %zdn1, <vscale x 4 x float> %zdn2, <vscale x 4 x float> %zm)150 ret { <vscale x 4 x float>, <vscale x 4 x float> } %res151}152 153define { <vscale x 2 x double>, <vscale x 2 x double> } @multi_vec_min_single_x2_f64(<vscale x 2 x double> %unused, <vscale x 2 x double> %zdn1, <vscale x 2 x double> %zdn2, <vscale x 2 x double> %zm) {154; CHECK-LABEL: multi_vec_min_single_x2_f64:155; CHECK: // %bb.0:156; CHECK-NEXT: mov z5.d, z2.d157; CHECK-NEXT: mov z4.d, z1.d158; CHECK-NEXT: fmin { z4.d, z5.d }, { z4.d, z5.d }, z3.d159; CHECK-NEXT: mov z0.d, z4.d160; CHECK-NEXT: mov z1.d, z5.d161; CHECK-NEXT: ret162 %res = call { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sve.fmin.single.x2.nxv2f64(<vscale x 2 x double> %zdn1, <vscale x 2 x double> %zdn2, <vscale x 2 x double> %zm)163 ret { <vscale x 2 x double>, <vscale x 2 x double> } %res164}165 166; SMIN (Single, x4)167 168define { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @multi_vec_min_single_x4_s8(<vscale x 16 x i8> %unused, <vscale x 16 x i8> %zdn1, <vscale x 16 x i8> %zdn2, <vscale x 16 x i8> %zdn3, <vscale x 16 x i8> %zdn4, <vscale x 16 x i8> %zm) {169; CHECK-LABEL: multi_vec_min_single_x4_s8:170; CHECK: // %bb.0:171; CHECK-NEXT: mov z27.d, z4.d172; CHECK-NEXT: mov z26.d, z3.d173; CHECK-NEXT: mov z25.d, z2.d174; CHECK-NEXT: mov z24.d, z1.d175; CHECK-NEXT: smin { z24.b - z27.b }, { z24.b - z27.b }, z5.b176; CHECK-NEXT: mov z0.d, z24.d177; CHECK-NEXT: mov z1.d, z25.d178; CHECK-NEXT: mov z2.d, z26.d179; CHECK-NEXT: mov z3.d, z27.d180; CHECK-NEXT: ret181 %res = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }182 @llvm.aarch64.sve.smin.single.x4.nxv16i8(<vscale x 16 x i8> %zdn1, <vscale x 16 x i8> %zdn2, <vscale x 16 x i8> %zdn3, <vscale x 16 x i8> %zdn4, <vscale x 16 x i8> %zm)183 ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %res184}185 186define { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @multi_vec_min_single_x4_s16(<vscale x 8 x i16> %unused, <vscale x 8 x i16> %zdn1, <vscale x 8 x i16> %zdn2, <vscale x 8 x i16> %zdn3, <vscale x 8 x i16> %zdn4, <vscale x 8 x i16> %zm) {187; CHECK-LABEL: multi_vec_min_single_x4_s16:188; CHECK: // %bb.0:189; CHECK-NEXT: mov z27.d, z4.d190; CHECK-NEXT: mov z26.d, z3.d191; CHECK-NEXT: mov z25.d, z2.d192; CHECK-NEXT: mov z24.d, z1.d193; CHECK-NEXT: smin { z24.h - z27.h }, { z24.h - z27.h }, z5.h194; CHECK-NEXT: mov z0.d, z24.d195; CHECK-NEXT: mov z1.d, z25.d196; CHECK-NEXT: mov z2.d, z26.d197; CHECK-NEXT: mov z3.d, z27.d198; CHECK-NEXT: ret199 %res = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }200 @llvm.aarch64.sve.smin.single.x4.nxv8i16(<vscale x 8 x i16> %zdn1, <vscale x 8 x i16> %zdn2, <vscale x 8 x i16> %zdn3, <vscale x 8 x i16> %zdn4, <vscale x 8 x i16> %zm)201 ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %res202}203 204define { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @multi_vec_min_single_x4_s32(<vscale x 4 x i32> %unused, <vscale x 4 x i32> %zdn1, <vscale x 4 x i32> %zdn2, <vscale x 4 x i32> %zdn3, <vscale x 4 x i32> %zdn4, <vscale x 4 x i32> %zm) {205; CHECK-LABEL: multi_vec_min_single_x4_s32:206; CHECK: // %bb.0:207; CHECK-NEXT: mov z27.d, z4.d208; CHECK-NEXT: mov z26.d, z3.d209; CHECK-NEXT: mov z25.d, z2.d210; CHECK-NEXT: mov z24.d, z1.d211; CHECK-NEXT: smin { z24.s - z27.s }, { z24.s - z27.s }, z5.s212; CHECK-NEXT: mov z0.d, z24.d213; CHECK-NEXT: mov z1.d, z25.d214; CHECK-NEXT: mov z2.d, z26.d215; CHECK-NEXT: mov z3.d, z27.d216; CHECK-NEXT: ret217 %res = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }218 @llvm.aarch64.sve.smin.single.x4.nxv4i32(<vscale x 4 x i32> %zdn1, <vscale x 4 x i32> %zdn2, <vscale x 4 x i32> %zdn3, <vscale x 4 x i32> %zdn4, <vscale x 4 x i32> %zm)219 ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %res220}221 222define { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @multi_vec_min_single_x4_s64(<vscale x 2 x i64> %unused, <vscale x 2 x i64> %zdn1, <vscale x 2 x i64> %zdn2, <vscale x 2 x i64> %zdn3, <vscale x 2 x i64> %zdn4, <vscale x 2 x i64> %zm) {223; CHECK-LABEL: multi_vec_min_single_x4_s64:224; CHECK: // %bb.0:225; CHECK-NEXT: mov z27.d, z4.d226; CHECK-NEXT: mov z26.d, z3.d227; CHECK-NEXT: mov z25.d, z2.d228; CHECK-NEXT: mov z24.d, z1.d229; CHECK-NEXT: smin { z24.d - z27.d }, { z24.d - z27.d }, z5.d230; CHECK-NEXT: mov z0.d, z24.d231; CHECK-NEXT: mov z1.d, z25.d232; CHECK-NEXT: mov z2.d, z26.d233; CHECK-NEXT: mov z3.d, z27.d234; CHECK-NEXT: ret235 %res = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }236 @llvm.aarch64.sve.smin.single.x4.nxv2i64(<vscale x 2 x i64> %zdn1, <vscale x 2 x i64> %zdn2, <vscale x 2 x i64> %zdn3, <vscale x 2 x i64> %zdn4, <vscale x 2 x i64> %zm)237 ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %res238}239 240; UMIN (Single, x4)241 242define { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @multi_vec_min_single_x4_u8(<vscale x 16 x i8> %unused, <vscale x 16 x i8> %zdn1, <vscale x 16 x i8> %zdn2, <vscale x 16 x i8> %zdn3, <vscale x 16 x i8> %zdn4, <vscale x 16 x i8> %zm) {243; CHECK-LABEL: multi_vec_min_single_x4_u8:244; CHECK: // %bb.0:245; CHECK-NEXT: mov z27.d, z4.d246; CHECK-NEXT: mov z26.d, z3.d247; CHECK-NEXT: mov z25.d, z2.d248; CHECK-NEXT: mov z24.d, z1.d249; CHECK-NEXT: umin { z24.b - z27.b }, { z24.b - z27.b }, z5.b250; CHECK-NEXT: mov z0.d, z24.d251; CHECK-NEXT: mov z1.d, z25.d252; CHECK-NEXT: mov z2.d, z26.d253; CHECK-NEXT: mov z3.d, z27.d254; CHECK-NEXT: ret255 %res = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }256 @llvm.aarch64.sve.umin.single.x4.nxv16i8(<vscale x 16 x i8> %zdn1, <vscale x 16 x i8> %zdn2, <vscale x 16 x i8> %zdn3, <vscale x 16 x i8> %zdn4, <vscale x 16 x i8> %zm)257 ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %res258}259 260define { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @multi_vec_min_single_x4_u16(<vscale x 8 x i16> %unused, <vscale x 8 x i16> %zdn1, <vscale x 8 x i16> %zdn2, <vscale x 8 x i16> %zdn3, <vscale x 8 x i16> %zdn4, <vscale x 8 x i16> %zm) {261; CHECK-LABEL: multi_vec_min_single_x4_u16:262; CHECK: // %bb.0:263; CHECK-NEXT: mov z27.d, z4.d264; CHECK-NEXT: mov z26.d, z3.d265; CHECK-NEXT: mov z25.d, z2.d266; CHECK-NEXT: mov z24.d, z1.d267; CHECK-NEXT: umin { z24.h - z27.h }, { z24.h - z27.h }, z5.h268; CHECK-NEXT: mov z0.d, z24.d269; CHECK-NEXT: mov z1.d, z25.d270; CHECK-NEXT: mov z2.d, z26.d271; CHECK-NEXT: mov z3.d, z27.d272; CHECK-NEXT: ret273 %res = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }274 @llvm.aarch64.sve.umin.single.x4.nxv8i16(<vscale x 8 x i16> %zdn1, <vscale x 8 x i16> %zdn2, <vscale x 8 x i16> %zdn3, <vscale x 8 x i16> %zdn4, <vscale x 8 x i16> %zm)275 ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %res276}277 278define { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @multi_vec_min_single_x4_u32(<vscale x 4 x i32> %unused, <vscale x 4 x i32> %zdn1, <vscale x 4 x i32> %zdn2, <vscale x 4 x i32> %zdn3, <vscale x 4 x i32> %zdn4, <vscale x 4 x i32> %zm) {279; CHECK-LABEL: multi_vec_min_single_x4_u32:280; CHECK: // %bb.0:281; CHECK-NEXT: mov z27.d, z4.d282; CHECK-NEXT: mov z26.d, z3.d283; CHECK-NEXT: mov z25.d, z2.d284; CHECK-NEXT: mov z24.d, z1.d285; CHECK-NEXT: umin { z24.s - z27.s }, { z24.s - z27.s }, z5.s286; CHECK-NEXT: mov z0.d, z24.d287; CHECK-NEXT: mov z1.d, z25.d288; CHECK-NEXT: mov z2.d, z26.d289; CHECK-NEXT: mov z3.d, z27.d290; CHECK-NEXT: ret291 %res = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }292 @llvm.aarch64.sve.umin.single.x4.nxv4i32(<vscale x 4 x i32> %zdn1, <vscale x 4 x i32> %zdn2, <vscale x 4 x i32> %zdn3, <vscale x 4 x i32> %zdn4, <vscale x 4 x i32> %zm)293 ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %res294}295 296define { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @multi_vec_min_single_x4_u64(<vscale x 2 x i64> %unused, <vscale x 2 x i64> %zdn1, <vscale x 2 x i64> %zdn2, <vscale x 2 x i64> %zdn3, <vscale x 2 x i64> %zdn4, <vscale x 2 x i64> %zm) {297; CHECK-LABEL: multi_vec_min_single_x4_u64:298; CHECK: // %bb.0:299; CHECK-NEXT: mov z27.d, z4.d300; CHECK-NEXT: mov z26.d, z3.d301; CHECK-NEXT: mov z25.d, z2.d302; CHECK-NEXT: mov z24.d, z1.d303; CHECK-NEXT: umin { z24.d - z27.d }, { z24.d - z27.d }, z5.d304; CHECK-NEXT: mov z0.d, z24.d305; CHECK-NEXT: mov z1.d, z25.d306; CHECK-NEXT: mov z2.d, z26.d307; CHECK-NEXT: mov z3.d, z27.d308; CHECK-NEXT: ret309 %res = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }310 @llvm.aarch64.sve.umin.single.x4.nxv2i64(<vscale x 2 x i64> %zdn1, <vscale x 2 x i64> %zdn2, <vscale x 2 x i64> %zdn3, <vscale x 2 x i64> %zdn4, <vscale x 2 x i64> %zm)311 ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %res312}313 314; BFMIN (Single, x4)315 316define { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @multi_vec_min_single_x4_bf16(<vscale x 8 x bfloat> %zdn1, <vscale x 8 x bfloat> %zdn2, <vscale x 8 x bfloat> %zdn3, <vscale x 8 x bfloat> %zdn4, <vscale x 8 x bfloat> %zm) {317; CHECK-LABEL: multi_vec_min_single_x4_bf16:318; CHECK: // %bb.0:319; CHECK-NEXT: // kill: def $z3 killed $z3 killed $z0_z1_z2_z3 def $z0_z1_z2_z3320; CHECK-NEXT: // kill: def $z2 killed $z2 killed $z0_z1_z2_z3 def $z0_z1_z2_z3321; CHECK-NEXT: // kill: def $z1 killed $z1 killed $z0_z1_z2_z3 def $z0_z1_z2_z3322; CHECK-NEXT: // kill: def $z0 killed $z0 killed $z0_z1_z2_z3 def $z0_z1_z2_z3323; CHECK-NEXT: bfmin { z0.h - z3.h }, { z0.h - z3.h }, z4.h324; CHECK-NEXT: ret325 %res = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fmin.single.x4.nxv8bf16(<vscale x 8 x bfloat> %zdn1, <vscale x 8 x bfloat> %zdn2, <vscale x 8 x bfloat> %zdn3, <vscale x 8 x bfloat> %zdn4, <vscale x 8 x bfloat> %zm)326 ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %res327}328 329; FMIN (SINGLE, x4)330 331define { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @multi_vec_min_single_x4_f16(<vscale x 8 x half> %unused, <vscale x 8 x half> %zdn1, <vscale x 8 x half> %zdn2, <vscale x 8 x half> %zdn3, <vscale x 8 x half> %zdn4, <vscale x 8 x half> %zm) {332; CHECK-LABEL: multi_vec_min_single_x4_f16:333; CHECK: // %bb.0:334; CHECK-NEXT: mov z27.d, z4.d335; CHECK-NEXT: mov z26.d, z3.d336; CHECK-NEXT: mov z25.d, z2.d337; CHECK-NEXT: mov z24.d, z1.d338; CHECK-NEXT: fmin { z24.h - z27.h }, { z24.h - z27.h }, z5.h339; CHECK-NEXT: mov z0.d, z24.d340; CHECK-NEXT: mov z1.d, z25.d341; CHECK-NEXT: mov z2.d, z26.d342; CHECK-NEXT: mov z3.d, z27.d343; CHECK-NEXT: ret344 %res = call { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }345 @llvm.aarch64.sve.fmin.single.x4.nxv8f16(<vscale x 8 x half> %zdn1, <vscale x 8 x half> %zdn2, <vscale x 8 x half> %zdn3, <vscale x 8 x half> %zdn4, <vscale x 8 x half> %zm)346 ret { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %res347}348 349define { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @multi_vec_min_single_x4_f32(<vscale x 4 x float> %unused, <vscale x 4 x float> %zdn1, <vscale x 4 x float> %zdn2, <vscale x 4 x float> %zdn3, <vscale x 4 x float> %zdn4, <vscale x 4 x float> %zm) {350; CHECK-LABEL: multi_vec_min_single_x4_f32:351; CHECK: // %bb.0:352; CHECK-NEXT: mov z27.d, z4.d353; CHECK-NEXT: mov z26.d, z3.d354; CHECK-NEXT: mov z25.d, z2.d355; CHECK-NEXT: mov z24.d, z1.d356; CHECK-NEXT: fmin { z24.s - z27.s }, { z24.s - z27.s }, z5.s357; CHECK-NEXT: mov z0.d, z24.d358; CHECK-NEXT: mov z1.d, z25.d359; CHECK-NEXT: mov z2.d, z26.d360; CHECK-NEXT: mov z3.d, z27.d361; CHECK-NEXT: ret362 %res = call { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }363 @llvm.aarch64.sve.fmin.single.x4.nxv4f32(<vscale x 4 x float> %zdn1, <vscale x 4 x float> %zdn2, <vscale x 4 x float> %zdn3, <vscale x 4 x float> %zdn4, <vscale x 4 x float> %zm)364 ret { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %res365}366 367define { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } @multi_vec_min_single_x4_f64(<vscale x 2 x double> %unused, <vscale x 2 x double> %zdn1, <vscale x 2 x double> %zdn2, <vscale x 2 x double> %zdn3, <vscale x 2 x double> %zdn4, <vscale x 2 x double> %zm) {368; CHECK-LABEL: multi_vec_min_single_x4_f64:369; CHECK: // %bb.0:370; CHECK-NEXT: mov z27.d, z4.d371; CHECK-NEXT: mov z26.d, z3.d372; CHECK-NEXT: mov z25.d, z2.d373; CHECK-NEXT: mov z24.d, z1.d374; CHECK-NEXT: fmin { z24.d - z27.d }, { z24.d - z27.d }, z5.d375; CHECK-NEXT: mov z0.d, z24.d376; CHECK-NEXT: mov z1.d, z25.d377; CHECK-NEXT: mov z2.d, z26.d378; CHECK-NEXT: mov z3.d, z27.d379; CHECK-NEXT: ret380 %res = call { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> }381 @llvm.aarch64.sve.fmin.single.x4.nxv2f64(<vscale x 2 x double> %zdn1, <vscale x 2 x double> %zdn2, <vscale x 2 x double> %zdn3, <vscale x 2 x double> %zdn4, <vscale x 2 x double> %zm)382 ret { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } %res383}384 385; SMIN (Multi, x2)386 387define { <vscale x 16 x i8>, <vscale x 16 x i8> } @multi_vec_min_multi_x2_s8(<vscale x 16 x i8> %unused, <vscale x 16 x i8> %zdn1, <vscale x 16 x i8> %zdn2, <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2) {388; CHECK-LABEL: multi_vec_min_multi_x2_s8:389; CHECK: // %bb.0:390; CHECK-NEXT: mov z7.d, z4.d391; CHECK-NEXT: mov z5.d, z2.d392; CHECK-NEXT: mov z6.d, z3.d393; CHECK-NEXT: mov z4.d, z1.d394; CHECK-NEXT: smin { z4.b, z5.b }, { z4.b, z5.b }, { z6.b, z7.b }395; CHECK-NEXT: mov z0.d, z4.d396; CHECK-NEXT: mov z1.d, z5.d397; CHECK-NEXT: ret398 %res = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.smin.x2.nxv16i8(<vscale x 16 x i8> %zdn1, <vscale x 16 x i8> %zdn2, <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2)399 ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %res400}401 402define { <vscale x 8 x i16>, <vscale x 8 x i16> } @multi_vec_min_multi_x2_s16(<vscale x 8 x i16> %unused, <vscale x 8 x i16> %zdn1, <vscale x 8 x i16> %zdn2, <vscale x 8 x i16> %zm1, <vscale x 8 x i16> %zm2) {403; CHECK-LABEL: multi_vec_min_multi_x2_s16:404; CHECK: // %bb.0:405; CHECK-NEXT: mov z7.d, z4.d406; CHECK-NEXT: mov z5.d, z2.d407; CHECK-NEXT: mov z6.d, z3.d408; CHECK-NEXT: mov z4.d, z1.d409; CHECK-NEXT: smin { z4.h, z5.h }, { z4.h, z5.h }, { z6.h, z7.h }410; CHECK-NEXT: mov z0.d, z4.d411; CHECK-NEXT: mov z1.d, z5.d412; CHECK-NEXT: ret413 %res = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.smin.x2.nxv8i16(<vscale x 8 x i16> %zdn1, <vscale x 8 x i16> %zdn2, <vscale x 8 x i16> %zm1, <vscale x 8 x i16> %zm2)414 ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %res415}416 417define { <vscale x 4 x i32>, <vscale x 4 x i32> } @multi_vec_min_multi_x2_s32(<vscale x 4 x i32> %unused, <vscale x 4 x i32> %zdn1, <vscale x 4 x i32> %zdn2, <vscale x 4 x i32> %zm1, <vscale x 4 x i32> %zm2) {418; CHECK-LABEL: multi_vec_min_multi_x2_s32:419; CHECK: // %bb.0:420; CHECK-NEXT: mov z7.d, z4.d421; CHECK-NEXT: mov z5.d, z2.d422; CHECK-NEXT: mov z6.d, z3.d423; CHECK-NEXT: mov z4.d, z1.d424; CHECK-NEXT: smin { z4.s, z5.s }, { z4.s, z5.s }, { z6.s, z7.s }425; CHECK-NEXT: mov z0.d, z4.d426; CHECK-NEXT: mov z1.d, z5.d427; CHECK-NEXT: ret428 %res = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.smin.x2.nxv4i32(<vscale x 4 x i32> %zdn1, <vscale x 4 x i32> %zdn2, <vscale x 4 x i32> %zm1, <vscale x 4 x i32> %zm2)429 ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %res430}431 432define { <vscale x 2 x i64>, <vscale x 2 x i64> } @multi_vec_min_multi_x2_s64(<vscale x 2 x i64> %unused, <vscale x 2 x i64> %zdn1, <vscale x 2 x i64> %zdn2, <vscale x 2 x i64> %zm1, <vscale x 2 x i64> %zm2) {433; CHECK-LABEL: multi_vec_min_multi_x2_s64:434; CHECK: // %bb.0:435; CHECK-NEXT: mov z7.d, z4.d436; CHECK-NEXT: mov z5.d, z2.d437; CHECK-NEXT: mov z6.d, z3.d438; CHECK-NEXT: mov z4.d, z1.d439; CHECK-NEXT: smin { z4.d, z5.d }, { z4.d, z5.d }, { z6.d, z7.d }440; CHECK-NEXT: mov z0.d, z4.d441; CHECK-NEXT: mov z1.d, z5.d442; CHECK-NEXT: ret443 %res = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.smin.x2.nxv2i64(<vscale x 2 x i64> %zdn1, <vscale x 2 x i64> %zdn2, <vscale x 2 x i64> %zm1, <vscale x 2 x i64> %zm2)444 ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %res445}446 447; UMIN (Multi, x2)448 449define { <vscale x 16 x i8>, <vscale x 16 x i8> } @multi_vec_min_multi_x2_u8(<vscale x 16 x i8> %unused, <vscale x 16 x i8> %zdn1, <vscale x 16 x i8> %zdn2, <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2) {450; CHECK-LABEL: multi_vec_min_multi_x2_u8:451; CHECK: // %bb.0:452; CHECK-NEXT: mov z7.d, z4.d453; CHECK-NEXT: mov z5.d, z2.d454; CHECK-NEXT: mov z6.d, z3.d455; CHECK-NEXT: mov z4.d, z1.d456; CHECK-NEXT: umin { z4.b, z5.b }, { z4.b, z5.b }, { z6.b, z7.b }457; CHECK-NEXT: mov z0.d, z4.d458; CHECK-NEXT: mov z1.d, z5.d459; CHECK-NEXT: ret460 %res = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.umin.x2.nxv16i8(<vscale x 16 x i8> %zdn1, <vscale x 16 x i8> %zdn2, <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2)461 ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %res462}463 464define { <vscale x 8 x i16>, <vscale x 8 x i16> } @multi_vec_min_multi_x2_u16(<vscale x 8 x i16> %unused, <vscale x 8 x i16> %zdn1, <vscale x 8 x i16> %zdn2, <vscale x 8 x i16> %zm1, <vscale x 8 x i16> %zm2) {465; CHECK-LABEL: multi_vec_min_multi_x2_u16:466; CHECK: // %bb.0:467; CHECK-NEXT: mov z7.d, z4.d468; CHECK-NEXT: mov z5.d, z2.d469; CHECK-NEXT: mov z6.d, z3.d470; CHECK-NEXT: mov z4.d, z1.d471; CHECK-NEXT: umin { z4.h, z5.h }, { z4.h, z5.h }, { z6.h, z7.h }472; CHECK-NEXT: mov z0.d, z4.d473; CHECK-NEXT: mov z1.d, z5.d474; CHECK-NEXT: ret475 %res = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.umin.x2.nxv8i16(<vscale x 8 x i16> %zdn1, <vscale x 8 x i16> %zdn2, <vscale x 8 x i16> %zm1, <vscale x 8 x i16> %zm2)476 ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %res477}478 479define { <vscale x 4 x i32>, <vscale x 4 x i32> } @multi_vec_min_multi_x2_u32(<vscale x 4 x i32> %unused, <vscale x 4 x i32> %zdn1, <vscale x 4 x i32> %zdn2, <vscale x 4 x i32> %zm1, <vscale x 4 x i32> %zm2) {480; CHECK-LABEL: multi_vec_min_multi_x2_u32:481; CHECK: // %bb.0:482; CHECK-NEXT: mov z7.d, z4.d483; CHECK-NEXT: mov z5.d, z2.d484; CHECK-NEXT: mov z6.d, z3.d485; CHECK-NEXT: mov z4.d, z1.d486; CHECK-NEXT: umin { z4.s, z5.s }, { z4.s, z5.s }, { z6.s, z7.s }487; CHECK-NEXT: mov z0.d, z4.d488; CHECK-NEXT: mov z1.d, z5.d489; CHECK-NEXT: ret490 %res = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.umin.x2.nxv4i32(<vscale x 4 x i32> %zdn1, <vscale x 4 x i32> %zdn2, <vscale x 4 x i32> %zm1, <vscale x 4 x i32> %zm2)491 ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %res492}493 494define { <vscale x 2 x i64>, <vscale x 2 x i64> } @multi_vec_min_multi_x2_u64(<vscale x 2 x i64> %unused, <vscale x 2 x i64> %zdn1, <vscale x 2 x i64> %zdn2, <vscale x 2 x i64> %zm1, <vscale x 2 x i64> %zm2) {495; CHECK-LABEL: multi_vec_min_multi_x2_u64:496; CHECK: // %bb.0:497; CHECK-NEXT: mov z7.d, z4.d498; CHECK-NEXT: mov z5.d, z2.d499; CHECK-NEXT: mov z6.d, z3.d500; CHECK-NEXT: mov z4.d, z1.d501; CHECK-NEXT: umin { z4.d, z5.d }, { z4.d, z5.d }, { z6.d, z7.d }502; CHECK-NEXT: mov z0.d, z4.d503; CHECK-NEXT: mov z1.d, z5.d504; CHECK-NEXT: ret505 %res = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.umin.x2.nxv2i64(<vscale x 2 x i64> %zdn1, <vscale x 2 x i64> %zdn2, <vscale x 2 x i64> %zm1, <vscale x 2 x i64> %zm2)506 ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %res507}508 509; BFMIN (Multi, x2)510 511define { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @multi_vec_min_x2_bf16(<vscale x 8 x bfloat> %zdn1, <vscale x 8 x bfloat> %zdn2, <vscale x 8 x bfloat> %zm1, <vscale x 8 x bfloat> %zm2) {512; CHECK-LABEL: multi_vec_min_x2_bf16:513; CHECK: // %bb.0:514; CHECK-NEXT: // kill: def $z1 killed $z1 killed $z0_z1 def $z0_z1515; CHECK-NEXT: // kill: def $z3 killed $z3 killed $z2_z3 def $z2_z3516; CHECK-NEXT: // kill: def $z0 killed $z0 killed $z0_z1 def $z0_z1517; CHECK-NEXT: // kill: def $z2 killed $z2 killed $z2_z3 def $z2_z3518; CHECK-NEXT: bfmin { z0.h, z1.h }, { z0.h, z1.h }, { z2.h, z3.h }519; CHECK-NEXT: ret520 %res = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fmin.x2.nxv8bf16(<vscale x 8 x bfloat> %zdn1, <vscale x 8 x bfloat> %zdn2, <vscale x 8 x bfloat> %zm1, <vscale x 8 x bfloat> %zm2)521 ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %res522}523 524; FMIN (Multi, x2)525 526define { <vscale x 8 x half>, <vscale x 8 x half> } @multi_vec_min_multi_x2_f16(<vscale x 8 x half> %unused, <vscale x 8 x half> %zdn1, <vscale x 8 x half> %zdn2, <vscale x 8 x half> %zm1, <vscale x 8 x half> %zm2) {527; CHECK-LABEL: multi_vec_min_multi_x2_f16:528; CHECK: // %bb.0:529; CHECK-NEXT: mov z7.d, z4.d530; CHECK-NEXT: mov z5.d, z2.d531; CHECK-NEXT: mov z6.d, z3.d532; CHECK-NEXT: mov z4.d, z1.d533; CHECK-NEXT: fmin { z4.h, z5.h }, { z4.h, z5.h }, { z6.h, z7.h }534; CHECK-NEXT: mov z0.d, z4.d535; CHECK-NEXT: mov z1.d, z5.d536; CHECK-NEXT: ret537 %res = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.fmin.x2.nxv8f16(<vscale x 8 x half> %zdn1, <vscale x 8 x half> %zdn2, <vscale x 8 x half> %zm1, <vscale x 8 x half> %zm2)538 ret { <vscale x 8 x half>, <vscale x 8 x half> } %res539}540 541define { <vscale x 4 x float>, <vscale x 4 x float> } @multi_vec_min_multi_x2_f32(<vscale x 4 x float> %unused, <vscale x 4 x float> %zdn1, <vscale x 4 x float> %zdn2, <vscale x 4 x float> %zm1, <vscale x 4 x float> %zm2) {542; CHECK-LABEL: multi_vec_min_multi_x2_f32:543; CHECK: // %bb.0:544; CHECK-NEXT: mov z7.d, z4.d545; CHECK-NEXT: mov z5.d, z2.d546; CHECK-NEXT: mov z6.d, z3.d547; CHECK-NEXT: mov z4.d, z1.d548; CHECK-NEXT: fmin { z4.s, z5.s }, { z4.s, z5.s }, { z6.s, z7.s }549; CHECK-NEXT: mov z0.d, z4.d550; CHECK-NEXT: mov z1.d, z5.d551; CHECK-NEXT: ret552 %res = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.fmin.x2.nxv4f32(<vscale x 4 x float> %zdn1, <vscale x 4 x float> %zdn2, <vscale x 4 x float> %zm1, <vscale x 4 x float> %zm2)553 ret { <vscale x 4 x float>, <vscale x 4 x float> } %res554}555 556define { <vscale x 2 x double>, <vscale x 2 x double> } @multi_vec_min_multi_x2_f64(<vscale x 2 x double> %unused, <vscale x 2 x double> %zdn1, <vscale x 2 x double> %zdn2, <vscale x 2 x double> %zm1, <vscale x 2 x double> %zm2) {557; CHECK-LABEL: multi_vec_min_multi_x2_f64:558; CHECK: // %bb.0:559; CHECK-NEXT: mov z7.d, z4.d560; CHECK-NEXT: mov z5.d, z2.d561; CHECK-NEXT: mov z6.d, z3.d562; CHECK-NEXT: mov z4.d, z1.d563; CHECK-NEXT: fmin { z4.d, z5.d }, { z4.d, z5.d }, { z6.d, z7.d }564; CHECK-NEXT: mov z0.d, z4.d565; CHECK-NEXT: mov z1.d, z5.d566; CHECK-NEXT: ret567 %res = call { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sve.fmin.x2.nxv2f64(<vscale x 2 x double> %zdn1, <vscale x 2 x double> %zdn2, <vscale x 2 x double> %zm1, <vscale x 2 x double> %zm2)568 ret { <vscale x 2 x double>, <vscale x 2 x double> } %res569}570 571; SMIN (Multi, x4)572 573define { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @multi_vec_min_multi_x4_s8(<vscale x 16 x i8> %unused, <vscale x 16 x i8> %zdn1, <vscale x 16 x i8> %zdn2, <vscale x 16 x i8> %zdn3, <vscale x 16 x i8> %zdn4,574; CHECK-LABEL: multi_vec_min_multi_x4_s8:575; CHECK: // %bb.0:576; CHECK-NEXT: mov z30.d, z7.d577; CHECK-NEXT: mov z27.d, z4.d578; CHECK-NEXT: mov z29.d, z6.d579; CHECK-NEXT: mov z26.d, z3.d580; CHECK-NEXT: mov z28.d, z5.d581; CHECK-NEXT: mov z25.d, z2.d582; CHECK-NEXT: ldr z31, [x0]583; CHECK-NEXT: mov z24.d, z1.d584; CHECK-NEXT: smin { z24.b - z27.b }, { z24.b - z27.b }, { z28.b - z31.b }585; CHECK-NEXT: mov z0.d, z24.d586; CHECK-NEXT: mov z1.d, z25.d587; CHECK-NEXT: mov z2.d, z26.d588; CHECK-NEXT: mov z3.d, z27.d589; CHECK-NEXT: ret590 <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2, <vscale x 16 x i8> %zm3, <vscale x 16 x i8> %zm4) {591 %res = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }592 @llvm.aarch64.sve.smin.x4.nxv16i8(<vscale x 16 x i8> %zdn1, <vscale x 16 x i8> %zdn2, <vscale x 16 x i8> %zdn3, <vscale x 16 x i8> %zdn4,593 <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2, <vscale x 16 x i8> %zm3, <vscale x 16 x i8> %zm4)594 ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %res595}596 597define { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @multi_vec_min_multi_x4_s16(<vscale x 8 x i16> %unused, <vscale x 8 x i16> %zdn1, <vscale x 8 x i16> %zdn2, <vscale x 8 x i16> %zdn3, <vscale x 8 x i16> %zdn4,598; CHECK-LABEL: multi_vec_min_multi_x4_s16:599; CHECK: // %bb.0:600; CHECK-NEXT: mov z30.d, z7.d601; CHECK-NEXT: mov z27.d, z4.d602; CHECK-NEXT: mov z29.d, z6.d603; CHECK-NEXT: mov z26.d, z3.d604; CHECK-NEXT: mov z28.d, z5.d605; CHECK-NEXT: mov z25.d, z2.d606; CHECK-NEXT: ldr z31, [x0]607; CHECK-NEXT: mov z24.d, z1.d608; CHECK-NEXT: smin { z24.h - z27.h }, { z24.h - z27.h }, { z28.h - z31.h }609; CHECK-NEXT: mov z0.d, z24.d610; CHECK-NEXT: mov z1.d, z25.d611; CHECK-NEXT: mov z2.d, z26.d612; CHECK-NEXT: mov z3.d, z27.d613; CHECK-NEXT: ret614 <vscale x 8 x i16> %zm1, <vscale x 8 x i16> %zm2, <vscale x 8 x i16> %zm3, <vscale x 8 x i16> %zm4) {615 %res = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }616 @llvm.aarch64.sve.smin.x4.nxv8i16(<vscale x 8 x i16> %zdn1, <vscale x 8 x i16> %zdn2, <vscale x 8 x i16> %zdn3, <vscale x 8 x i16> %zdn4,617 <vscale x 8 x i16> %zm1, <vscale x 8 x i16> %zm2, <vscale x 8 x i16> %zm3, <vscale x 8 x i16> %zm4)618 ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %res619}620 621define { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @multi_vec_min_multi_x4_s32(<vscale x 4 x i32> %unused, <vscale x 4 x i32> %zdn1, <vscale x 4 x i32> %zdn2, <vscale x 4 x i32> %zdn3, <vscale x 4 x i32> %zdn4,622; CHECK-LABEL: multi_vec_min_multi_x4_s32:623; CHECK: // %bb.0:624; CHECK-NEXT: mov z30.d, z7.d625; CHECK-NEXT: mov z27.d, z4.d626; CHECK-NEXT: mov z29.d, z6.d627; CHECK-NEXT: mov z26.d, z3.d628; CHECK-NEXT: mov z28.d, z5.d629; CHECK-NEXT: mov z25.d, z2.d630; CHECK-NEXT: ldr z31, [x0]631; CHECK-NEXT: mov z24.d, z1.d632; CHECK-NEXT: smin { z24.s - z27.s }, { z24.s - z27.s }, { z28.s - z31.s }633; CHECK-NEXT: mov z0.d, z24.d634; CHECK-NEXT: mov z1.d, z25.d635; CHECK-NEXT: mov z2.d, z26.d636; CHECK-NEXT: mov z3.d, z27.d637; CHECK-NEXT: ret638 <vscale x 4 x i32> %zm1, <vscale x 4 x i32> %zm2, <vscale x 4 x i32> %zm3, <vscale x 4 x i32> %zm4) {639 %res = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }640 @llvm.aarch64.sve.smin.x4.nxv4i32(<vscale x 4 x i32> %zdn1, <vscale x 4 x i32> %zdn2, <vscale x 4 x i32> %zdn3, <vscale x 4 x i32> %zdn4,641 <vscale x 4 x i32> %zm1, <vscale x 4 x i32> %zm2, <vscale x 4 x i32> %zm3, <vscale x 4 x i32> %zm4)642 ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %res643}644 645define { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @multi_vec_min_multi_x4_s64(<vscale x 2 x i64> %unused, <vscale x 2 x i64> %zdn1, <vscale x 2 x i64> %zdn2, <vscale x 2 x i64> %zdn3, <vscale x 2 x i64> %zdn4,646; CHECK-LABEL: multi_vec_min_multi_x4_s64:647; CHECK: // %bb.0:648; CHECK-NEXT: mov z30.d, z7.d649; CHECK-NEXT: mov z27.d, z4.d650; CHECK-NEXT: mov z29.d, z6.d651; CHECK-NEXT: mov z26.d, z3.d652; CHECK-NEXT: mov z28.d, z5.d653; CHECK-NEXT: mov z25.d, z2.d654; CHECK-NEXT: ldr z31, [x0]655; CHECK-NEXT: mov z24.d, z1.d656; CHECK-NEXT: smin { z24.d - z27.d }, { z24.d - z27.d }, { z28.d - z31.d }657; CHECK-NEXT: mov z0.d, z24.d658; CHECK-NEXT: mov z1.d, z25.d659; CHECK-NEXT: mov z2.d, z26.d660; CHECK-NEXT: mov z3.d, z27.d661; CHECK-NEXT: ret662 <vscale x 2 x i64> %zm1, <vscale x 2 x i64> %zm2, <vscale x 2 x i64> %zm3, <vscale x 2 x i64> %zm4) {663 %res = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }664 @llvm.aarch64.sve.smin.x4.nxv2i64(<vscale x 2 x i64> %zdn1, <vscale x 2 x i64> %zdn2, <vscale x 2 x i64> %zdn3, <vscale x 2 x i64> %zdn4,665 <vscale x 2 x i64> %zm1, <vscale x 2 x i64> %zm2, <vscale x 2 x i64> %zm3, <vscale x 2 x i64> %zm4)666 ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %res667}668 669; UMIN (Multi, x4)670 671define { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @multi_vec_min_multi_x4_u8(<vscale x 16 x i8> %unused, <vscale x 16 x i8> %zdn1, <vscale x 16 x i8> %zdn2, <vscale x 16 x i8> %zdn3, <vscale x 16 x i8> %zdn4,672; CHECK-LABEL: multi_vec_min_multi_x4_u8:673; CHECK: // %bb.0:674; CHECK-NEXT: mov z30.d, z7.d675; CHECK-NEXT: mov z27.d, z4.d676; CHECK-NEXT: mov z29.d, z6.d677; CHECK-NEXT: mov z26.d, z3.d678; CHECK-NEXT: mov z28.d, z5.d679; CHECK-NEXT: mov z25.d, z2.d680; CHECK-NEXT: ldr z31, [x0]681; CHECK-NEXT: mov z24.d, z1.d682; CHECK-NEXT: umin { z24.b - z27.b }, { z24.b - z27.b }, { z28.b - z31.b }683; CHECK-NEXT: mov z0.d, z24.d684; CHECK-NEXT: mov z1.d, z25.d685; CHECK-NEXT: mov z2.d, z26.d686; CHECK-NEXT: mov z3.d, z27.d687; CHECK-NEXT: ret688 <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2, <vscale x 16 x i8> %zm3, <vscale x 16 x i8> %zm4) {689 %res = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }690 @llvm.aarch64.sve.umin.x4.nxv16i8(<vscale x 16 x i8> %zdn1, <vscale x 16 x i8> %zdn2, <vscale x 16 x i8> %zdn3, <vscale x 16 x i8> %zdn4,691 <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2, <vscale x 16 x i8> %zm3, <vscale x 16 x i8> %zm4)692 ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %res693}694 695define { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @multi_vec_min_multi_x4_u16(<vscale x 8 x i16> %unused, <vscale x 8 x i16> %zdn1, <vscale x 8 x i16> %zdn2, <vscale x 8 x i16> %zdn3, <vscale x 8 x i16> %zdn4,696; CHECK-LABEL: multi_vec_min_multi_x4_u16:697; CHECK: // %bb.0:698; CHECK-NEXT: mov z30.d, z7.d699; CHECK-NEXT: mov z27.d, z4.d700; CHECK-NEXT: mov z29.d, z6.d701; CHECK-NEXT: mov z26.d, z3.d702; CHECK-NEXT: mov z28.d, z5.d703; CHECK-NEXT: mov z25.d, z2.d704; CHECK-NEXT: ldr z31, [x0]705; CHECK-NEXT: mov z24.d, z1.d706; CHECK-NEXT: umin { z24.h - z27.h }, { z24.h - z27.h }, { z28.h - z31.h }707; CHECK-NEXT: mov z0.d, z24.d708; CHECK-NEXT: mov z1.d, z25.d709; CHECK-NEXT: mov z2.d, z26.d710; CHECK-NEXT: mov z3.d, z27.d711; CHECK-NEXT: ret712 <vscale x 8 x i16> %zm1, <vscale x 8 x i16> %zm2, <vscale x 8 x i16> %zm3, <vscale x 8 x i16> %zm4) {713 %res = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }714 @llvm.aarch64.sve.umin.x4.nxv8i16(<vscale x 8 x i16> %zdn1, <vscale x 8 x i16> %zdn2, <vscale x 8 x i16> %zdn3, <vscale x 8 x i16> %zdn4,715 <vscale x 8 x i16> %zm1, <vscale x 8 x i16> %zm2, <vscale x 8 x i16> %zm3, <vscale x 8 x i16> %zm4)716 ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %res717}718 719define { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @multi_vec_min_multi_x4_u32(<vscale x 4 x i32> %unused, <vscale x 4 x i32> %zdn1, <vscale x 4 x i32> %zdn2, <vscale x 4 x i32> %zdn3, <vscale x 4 x i32> %zdn4,720; CHECK-LABEL: multi_vec_min_multi_x4_u32:721; CHECK: // %bb.0:722; CHECK-NEXT: mov z30.d, z7.d723; CHECK-NEXT: mov z27.d, z4.d724; CHECK-NEXT: mov z29.d, z6.d725; CHECK-NEXT: mov z26.d, z3.d726; CHECK-NEXT: mov z28.d, z5.d727; CHECK-NEXT: mov z25.d, z2.d728; CHECK-NEXT: ldr z31, [x0]729; CHECK-NEXT: mov z24.d, z1.d730; CHECK-NEXT: umin { z24.s - z27.s }, { z24.s - z27.s }, { z28.s - z31.s }731; CHECK-NEXT: mov z0.d, z24.d732; CHECK-NEXT: mov z1.d, z25.d733; CHECK-NEXT: mov z2.d, z26.d734; CHECK-NEXT: mov z3.d, z27.d735; CHECK-NEXT: ret736 <vscale x 4 x i32> %zm1, <vscale x 4 x i32> %zm2, <vscale x 4 x i32> %zm3, <vscale x 4 x i32> %zm4) {737 %res = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }738 @llvm.aarch64.sve.umin.x4.nxv4i32(<vscale x 4 x i32> %zdn1, <vscale x 4 x i32> %zdn2, <vscale x 4 x i32> %zdn3, <vscale x 4 x i32> %zdn4,739 <vscale x 4 x i32> %zm1, <vscale x 4 x i32> %zm2, <vscale x 4 x i32> %zm3, <vscale x 4 x i32> %zm4)740 ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %res741}742 743define { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @multi_vec_min_multi_x4_u64(<vscale x 2 x i64> %unused, <vscale x 2 x i64> %zdn1, <vscale x 2 x i64> %zdn2, <vscale x 2 x i64> %zdn3, <vscale x 2 x i64> %zdn4,744; CHECK-LABEL: multi_vec_min_multi_x4_u64:745; CHECK: // %bb.0:746; CHECK-NEXT: mov z30.d, z7.d747; CHECK-NEXT: mov z27.d, z4.d748; CHECK-NEXT: mov z29.d, z6.d749; CHECK-NEXT: mov z26.d, z3.d750; CHECK-NEXT: mov z28.d, z5.d751; CHECK-NEXT: mov z25.d, z2.d752; CHECK-NEXT: ldr z31, [x0]753; CHECK-NEXT: mov z24.d, z1.d754; CHECK-NEXT: umin { z24.d - z27.d }, { z24.d - z27.d }, { z28.d - z31.d }755; CHECK-NEXT: mov z0.d, z24.d756; CHECK-NEXT: mov z1.d, z25.d757; CHECK-NEXT: mov z2.d, z26.d758; CHECK-NEXT: mov z3.d, z27.d759; CHECK-NEXT: ret760 <vscale x 2 x i64> %zm1, <vscale x 2 x i64> %zm2, <vscale x 2 x i64> %zm3, <vscale x 2 x i64> %zm4) {761 %res = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }762 @llvm.aarch64.sve.umin.x4.nxv2i64(<vscale x 2 x i64> %zdn1, <vscale x 2 x i64> %zdn2, <vscale x 2 x i64> %zdn3, <vscale x 2 x i64> %zdn4,763 <vscale x 2 x i64> %zm1, <vscale x 2 x i64> %zm2, <vscale x 2 x i64> %zm3, <vscale x 2 x i64> %zm4)764 ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %res765}766 767 768; BFMIN (Multi, x4)769 770define { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @multi_vec_min_x4_bf16(<vscale x 8 x bfloat> %zdn1, <vscale x 8 x bfloat> %zdn2, <vscale x 8 x bfloat> %zdn3, <vscale x 8 x bfloat> %zdn4, <vscale x 8 x bfloat> %zm1, <vscale x 8 x bfloat> %zm2, <vscale x 8 x bfloat> %zm3, <vscale x 8 x bfloat> %zm4) {771; CHECK-LABEL: multi_vec_min_x4_bf16:772; CHECK: // %bb.0:773; CHECK-NEXT: // kill: def $z3 killed $z3 killed $z0_z1_z2_z3 def $z0_z1_z2_z3774; CHECK-NEXT: // kill: def $z7 killed $z7 killed $z4_z5_z6_z7 def $z4_z5_z6_z7775; CHECK-NEXT: // kill: def $z2 killed $z2 killed $z0_z1_z2_z3 def $z0_z1_z2_z3776; CHECK-NEXT: // kill: def $z6 killed $z6 killed $z4_z5_z6_z7 def $z4_z5_z6_z7777; CHECK-NEXT: // kill: def $z1 killed $z1 killed $z0_z1_z2_z3 def $z0_z1_z2_z3778; CHECK-NEXT: // kill: def $z5 killed $z5 killed $z4_z5_z6_z7 def $z4_z5_z6_z7779; CHECK-NEXT: // kill: def $z0 killed $z0 killed $z0_z1_z2_z3 def $z0_z1_z2_z3780; CHECK-NEXT: // kill: def $z4 killed $z4 killed $z4_z5_z6_z7 def $z4_z5_z6_z7781; CHECK-NEXT: bfmin { z0.h - z3.h }, { z0.h - z3.h }, { z4.h - z7.h }782; CHECK-NEXT: ret783 %res = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fmin.x4.nxv8bf16(<vscale x 8 x bfloat> %zdn1, <vscale x 8 x bfloat> %zdn2, <vscale x 8 x bfloat> %zdn3, <vscale x 8 x bfloat> %zdn4, <vscale x 8 x bfloat> %zm1, <vscale x 8 x bfloat> %zm2, <vscale x 8 x bfloat> %zm3, <vscale x 8 x bfloat> %zm4)784 ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %res785}786 787; FMIN (Multi, x4)788 789define { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @multi_vec_min_multi_x4_f16(<vscale x 8 x half> %unused, <vscale x 8 x half> %zdn1, <vscale x 8 x half> %zdn2, <vscale x 8 x half> %zdn3, <vscale x 8 x half> %zdn4,790; CHECK-LABEL: multi_vec_min_multi_x4_f16:791; CHECK: // %bb.0:792; CHECK-NEXT: mov z30.d, z7.d793; CHECK-NEXT: mov z27.d, z4.d794; CHECK-NEXT: mov z29.d, z6.d795; CHECK-NEXT: mov z26.d, z3.d796; CHECK-NEXT: mov z28.d, z5.d797; CHECK-NEXT: mov z25.d, z2.d798; CHECK-NEXT: ldr z31, [x0]799; CHECK-NEXT: mov z24.d, z1.d800; CHECK-NEXT: fmin { z24.h - z27.h }, { z24.h - z27.h }, { z28.h - z31.h }801; CHECK-NEXT: mov z0.d, z24.d802; CHECK-NEXT: mov z1.d, z25.d803; CHECK-NEXT: mov z2.d, z26.d804; CHECK-NEXT: mov z3.d, z27.d805; CHECK-NEXT: ret806 <vscale x 8 x half> %zm1, <vscale x 8 x half> %zm2, <vscale x 8 x half> %zm3, <vscale x 8 x half> %zm4) {807 %res = call { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }808 @llvm.aarch64.sve.fmin.x4.nxv8f16(<vscale x 8 x half> %zdn1, <vscale x 8 x half> %zdn2, <vscale x 8 x half> %zdn3, <vscale x 8 x half> %zdn4,809 <vscale x 8 x half> %zm1, <vscale x 8 x half> %zm2, <vscale x 8 x half> %zm3, <vscale x 8 x half> %zm4)810 ret { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %res811}812 813define { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @multi_vec_min_multi_x4_f32(<vscale x 4 x float> %unused, <vscale x 4 x float> %zdn1, <vscale x 4 x float> %zdn2, <vscale x 4 x float> %zdn3, <vscale x 4 x float> %zdn4,814; CHECK-LABEL: multi_vec_min_multi_x4_f32:815; CHECK: // %bb.0:816; CHECK-NEXT: mov z30.d, z7.d817; CHECK-NEXT: mov z27.d, z4.d818; CHECK-NEXT: mov z29.d, z6.d819; CHECK-NEXT: mov z26.d, z3.d820; CHECK-NEXT: mov z28.d, z5.d821; CHECK-NEXT: mov z25.d, z2.d822; CHECK-NEXT: ldr z31, [x0]823; CHECK-NEXT: mov z24.d, z1.d824; CHECK-NEXT: fmin { z24.s - z27.s }, { z24.s - z27.s }, { z28.s - z31.s }825; CHECK-NEXT: mov z0.d, z24.d826; CHECK-NEXT: mov z1.d, z25.d827; CHECK-NEXT: mov z2.d, z26.d828; CHECK-NEXT: mov z3.d, z27.d829; CHECK-NEXT: ret830 <vscale x 4 x float> %zm1, <vscale x 4 x float> %zm2, <vscale x 4 x float> %zm3, <vscale x 4 x float> %zm4) {831 %res = call { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }832 @llvm.aarch64.sve.fmin.x4.nxv4f32(<vscale x 4 x float> %zdn1, <vscale x 4 x float> %zdn2, <vscale x 4 x float> %zdn3, <vscale x 4 x float> %zdn4,833 <vscale x 4 x float> %zm1, <vscale x 4 x float> %zm2, <vscale x 4 x float> %zm3, <vscale x 4 x float> %zm4)834 ret { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %res835}836 837define { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } @multi_vec_min_multi_x4_f64(<vscale x 2 x double> %unused, <vscale x 2 x double> %zdn1, <vscale x 2 x double> %zdn2, <vscale x 2 x double> %zdn3, <vscale x 2 x double> %zdn4,838; CHECK-LABEL: multi_vec_min_multi_x4_f64:839; CHECK: // %bb.0:840; CHECK-NEXT: mov z30.d, z7.d841; CHECK-NEXT: mov z27.d, z4.d842; CHECK-NEXT: mov z29.d, z6.d843; CHECK-NEXT: mov z26.d, z3.d844; CHECK-NEXT: mov z28.d, z5.d845; CHECK-NEXT: mov z25.d, z2.d846; CHECK-NEXT: ldr z31, [x0]847; CHECK-NEXT: mov z24.d, z1.d848; CHECK-NEXT: fmin { z24.d - z27.d }, { z24.d - z27.d }, { z28.d - z31.d }849; CHECK-NEXT: mov z0.d, z24.d850; CHECK-NEXT: mov z1.d, z25.d851; CHECK-NEXT: mov z2.d, z26.d852; CHECK-NEXT: mov z3.d, z27.d853; CHECK-NEXT: ret854 <vscale x 2 x double> %zm1, <vscale x 2 x double> %zm2, <vscale x 2 x double> %zm3, <vscale x 2 x double> %zm4) {855 %res = call { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> }856 @llvm.aarch64.sve.fmin.x4.nxv2f64(<vscale x 2 x double> %zdn1, <vscale x 2 x double> %zdn2, <vscale x 2 x double> %zdn3, <vscale x 2 x double> %zdn4,857 <vscale x 2 x double> %zm1, <vscale x 2 x double> %zm2, <vscale x 2 x double> %zm3, <vscale x 2 x double> %zm4)858 ret { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } %res859}860 861; BFMINNM (Single, x2)862 863define { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @multi_vec_minnm_single_x2_bf16(<vscale x 8 x bfloat> %zdn1, <vscale x 8 x bfloat> %zdn2, <vscale x 8 x bfloat> %zm) {864; CHECK-LABEL: multi_vec_minnm_single_x2_bf16:865; CHECK: // %bb.0:866; CHECK-NEXT: // kill: def $z1 killed $z1 killed $z0_z1 def $z0_z1867; CHECK-NEXT: // kill: def $z0 killed $z0 killed $z0_z1 def $z0_z1868; CHECK-NEXT: bfminnm { z0.h, z1.h }, { z0.h, z1.h }, z2.h869; CHECK-NEXT: ret870 %res = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fminnm.single.x2.nxv8bf16(<vscale x 8 x bfloat> %zdn1, <vscale x 8 x bfloat> %zdn2, <vscale x 8 x bfloat> %zm)871 ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %res872}873 874; FMINNM (Single, x2)875 876define { <vscale x 8 x half>, <vscale x 8 x half> } @multi_vec_minnm_single_x2_f16(<vscale x 8 x half> %dummy, <vscale x 8 x half> %zdn1, <vscale x 8 x half> %zdn2, <vscale x 8 x half> %zm) {877; CHECK-LABEL: multi_vec_minnm_single_x2_f16:878; CHECK: // %bb.0:879; CHECK-NEXT: mov z5.d, z2.d880; CHECK-NEXT: mov z4.d, z1.d881; CHECK-NEXT: fminnm { z4.h, z5.h }, { z4.h, z5.h }, z3.h882; CHECK-NEXT: mov z0.d, z4.d883; CHECK-NEXT: mov z1.d, z5.d884; CHECK-NEXT: ret885 %res = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.fminnm.single.x2.nxv8f16(<vscale x 8 x half> %zdn1, <vscale x 8 x half> %zdn2, <vscale x 8 x half> %zm)886 ret { <vscale x 8 x half>, <vscale x 8 x half> } %res887}888 889define { <vscale x 4 x float>, <vscale x 4 x float> } @multi_vec_minnm_single_x2_f32(<vscale x 8 x half> %dummy, <vscale x 4 x float> %zdn1, <vscale x 4 x float> %zdn2, <vscale x 4 x float> %zm) {890; CHECK-LABEL: multi_vec_minnm_single_x2_f32:891; CHECK: // %bb.0:892; CHECK-NEXT: mov z5.d, z2.d893; CHECK-NEXT: mov z4.d, z1.d894; CHECK-NEXT: fminnm { z4.s, z5.s }, { z4.s, z5.s }, z3.s895; CHECK-NEXT: mov z0.d, z4.d896; CHECK-NEXT: mov z1.d, z5.d897; CHECK-NEXT: ret898 %res = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.fminnm.single.x2.nxv4f32(<vscale x 4 x float> %zdn1, <vscale x 4 x float> %zdn2, <vscale x 4 x float> %zm)899 ret { <vscale x 4 x float>, <vscale x 4 x float> } %res900}901 902define { <vscale x 2 x double>, <vscale x 2 x double> } @multi_vec_minnm_single_x2_f64(<vscale x 8 x half> %dummy, <vscale x 2 x double> %zdn1, <vscale x 2 x double> %zdn2, <vscale x 2 x double> %zm) {903; CHECK-LABEL: multi_vec_minnm_single_x2_f64:904; CHECK: // %bb.0:905; CHECK-NEXT: mov z5.d, z2.d906; CHECK-NEXT: mov z4.d, z1.d907; CHECK-NEXT: fminnm { z4.d, z5.d }, { z4.d, z5.d }, z3.d908; CHECK-NEXT: mov z0.d, z4.d909; CHECK-NEXT: mov z1.d, z5.d910; CHECK-NEXT: ret911 %res = call { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sve.fminnm.single.x2.nxv2f64(<vscale x 2 x double> %zdn1, <vscale x 2 x double> %zdn2, <vscale x 2 x double> %zm)912 ret { <vscale x 2 x double>, <vscale x 2 x double> } %res913}914 915; BFMINNM (Single, x4)916 917define { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @multi_vec_minnm_single_x4_bf16(<vscale x 8 x bfloat> %zdn1, <vscale x 8 x bfloat> %zdn2, <vscale x 8 x bfloat> %zdn3, <vscale x 8 x bfloat> %zdn4, <vscale x 8 x bfloat> %zm) {918; CHECK-LABEL: multi_vec_minnm_single_x4_bf16:919; CHECK: // %bb.0:920; CHECK-NEXT: // kill: def $z3 killed $z3 killed $z0_z1_z2_z3 def $z0_z1_z2_z3921; CHECK-NEXT: // kill: def $z2 killed $z2 killed $z0_z1_z2_z3 def $z0_z1_z2_z3922; CHECK-NEXT: // kill: def $z1 killed $z1 killed $z0_z1_z2_z3 def $z0_z1_z2_z3923; CHECK-NEXT: // kill: def $z0 killed $z0 killed $z0_z1_z2_z3 def $z0_z1_z2_z3924; CHECK-NEXT: bfminnm { z0.h - z3.h }, { z0.h - z3.h }, z4.h925; CHECK-NEXT: ret926 %res = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fminnm.single.x4.nxv8bf16(<vscale x 8 x bfloat> %zdn1, <vscale x 8 x bfloat> %zdn2, <vscale x 8 x bfloat> %zdn3, <vscale x 8 x bfloat> %zdn4, <vscale x 8 x bfloat> %zm)927 ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %res928}929 930; FMINNM (Single, x4)931 932define { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @multi_vec_minnm_single_x4_f16(<vscale x 8 x half> %dummy, <vscale x 8 x half> %zdn1, <vscale x 8 x half> %zdn2, <vscale x 8 x half> %zdn3, <vscale x 8 x half> %zdn4, <vscale x 8 x half> %zm) {933; CHECK-LABEL: multi_vec_minnm_single_x4_f16:934; CHECK: // %bb.0:935; CHECK-NEXT: mov z27.d, z4.d936; CHECK-NEXT: mov z26.d, z3.d937; CHECK-NEXT: mov z25.d, z2.d938; CHECK-NEXT: mov z24.d, z1.d939; CHECK-NEXT: fminnm { z24.h - z27.h }, { z24.h - z27.h }, z5.h940; CHECK-NEXT: mov z0.d, z24.d941; CHECK-NEXT: mov z1.d, z25.d942; CHECK-NEXT: mov z2.d, z26.d943; CHECK-NEXT: mov z3.d, z27.d944; CHECK-NEXT: ret945 %res = call { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }946 @llvm.aarch64.sve.fminnm.single.x4.nxv8f16(<vscale x 8 x half> %zdn1, <vscale x 8 x half> %zdn2, <vscale x 8 x half> %zdn3, <vscale x 8 x half> %zdn4, <vscale x 8 x half> %zm)947 ret { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %res948}949 950define { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @multi_vec_minnm_single_x4_f32(<vscale x 8 x half> %dummy, <vscale x 4 x float> %zdn1, <vscale x 4 x float> %zdn2, <vscale x 4 x float> %zdn3, <vscale x 4 x float> %zdn4, <vscale x 4 x float> %zm) {951; CHECK-LABEL: multi_vec_minnm_single_x4_f32:952; CHECK: // %bb.0:953; CHECK-NEXT: mov z27.d, z4.d954; CHECK-NEXT: mov z26.d, z3.d955; CHECK-NEXT: mov z25.d, z2.d956; CHECK-NEXT: mov z24.d, z1.d957; CHECK-NEXT: fminnm { z24.s - z27.s }, { z24.s - z27.s }, z5.s958; CHECK-NEXT: mov z0.d, z24.d959; CHECK-NEXT: mov z1.d, z25.d960; CHECK-NEXT: mov z2.d, z26.d961; CHECK-NEXT: mov z3.d, z27.d962; CHECK-NEXT: ret963 %res = call { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }964 @llvm.aarch64.sve.fminnm.single.x4.nxv4f32(<vscale x 4 x float> %zdn1, <vscale x 4 x float> %zdn2, <vscale x 4 x float> %zdn3, <vscale x 4 x float> %zdn4, <vscale x 4 x float> %zm)965 ret { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %res966}967 968define { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } @multi_vec_minnm_single_x4_f64(<vscale x 8 x half> %dummy, <vscale x 2 x double> %zdn1, <vscale x 2 x double> %zdn2, <vscale x 2 x double> %zdn3, <vscale x 2 x double> %zdn4, <vscale x 2 x double> %zm) {969; CHECK-LABEL: multi_vec_minnm_single_x4_f64:970; CHECK: // %bb.0:971; CHECK-NEXT: mov z27.d, z4.d972; CHECK-NEXT: mov z26.d, z3.d973; CHECK-NEXT: mov z25.d, z2.d974; CHECK-NEXT: mov z24.d, z1.d975; CHECK-NEXT: fminnm { z24.d - z27.d }, { z24.d - z27.d }, z5.d976; CHECK-NEXT: mov z0.d, z24.d977; CHECK-NEXT: mov z1.d, z25.d978; CHECK-NEXT: mov z2.d, z26.d979; CHECK-NEXT: mov z3.d, z27.d980; CHECK-NEXT: ret981 %res = call { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> }982 @llvm.aarch64.sve.fminnm.single.x4.nxv2f64(<vscale x 2 x double> %zdn1, <vscale x 2 x double> %zdn2, <vscale x 2 x double> %zdn3, <vscale x 2 x double> %zdn4, <vscale x 2 x double> %zm)983 ret { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } %res984}985 986; BFMINNM (Multi, x2)987 988define { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @multi_vec_minnm_x2_bf16(<vscale x 8 x bfloat> %zdn1, <vscale x 8 x bfloat> %zdn2, <vscale x 8 x bfloat> %zm1, <vscale x 8 x bfloat> %zm2) {989; CHECK-LABEL: multi_vec_minnm_x2_bf16:990; CHECK: // %bb.0:991; CHECK-NEXT: // kill: def $z1 killed $z1 killed $z0_z1 def $z0_z1992; CHECK-NEXT: // kill: def $z3 killed $z3 killed $z2_z3 def $z2_z3993; CHECK-NEXT: // kill: def $z0 killed $z0 killed $z0_z1 def $z0_z1994; CHECK-NEXT: // kill: def $z2 killed $z2 killed $z2_z3 def $z2_z3995; CHECK-NEXT: bfminnm { z0.h, z1.h }, { z0.h, z1.h }, { z2.h, z3.h }996; CHECK-NEXT: ret997 %res = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fminnm.x2.nxv8bf16(<vscale x 8 x bfloat> %zdn1, <vscale x 8 x bfloat> %zdn2, <vscale x 8 x bfloat> %zm1, <vscale x 8 x bfloat> %zm2)998 ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %res999}1000 1001; FMINNM (Multi, x2)1002 1003define { <vscale x 8 x half>, <vscale x 8 x half> } @multi_vec_minnm_x2_f16(<vscale x 8 x half> %dummy, <vscale x 8 x half> %zdn1, <vscale x 8 x half> %zdn2, <vscale x 8 x half> %zm1, <vscale x 8 x half> %zm2) {1004; CHECK-LABEL: multi_vec_minnm_x2_f16:1005; CHECK: // %bb.0:1006; CHECK-NEXT: mov z7.d, z4.d1007; CHECK-NEXT: mov z5.d, z2.d1008; CHECK-NEXT: mov z6.d, z3.d1009; CHECK-NEXT: mov z4.d, z1.d1010; CHECK-NEXT: fminnm { z4.h, z5.h }, { z4.h, z5.h }, { z6.h, z7.h }1011; CHECK-NEXT: mov z0.d, z4.d1012; CHECK-NEXT: mov z1.d, z5.d1013; CHECK-NEXT: ret1014 %res = call { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.fminnm.x2.nxv8f16(<vscale x 8 x half> %zdn1, <vscale x 8 x half> %zdn2, <vscale x 8 x half> %zm1, <vscale x 8 x half> %zm2)1015 ret { <vscale x 8 x half>, <vscale x 8 x half> } %res1016}1017 1018define { <vscale x 4 x float>, <vscale x 4 x float> } @multi_vec_minnm_x2_f32(<vscale x 8 x half> %dummy, <vscale x 4 x float> %zdn1, <vscale x 4 x float> %zdn2, <vscale x 4 x float> %zm1, <vscale x 4 x float> %zm2) {1019; CHECK-LABEL: multi_vec_minnm_x2_f32:1020; CHECK: // %bb.0:1021; CHECK-NEXT: mov z7.d, z4.d1022; CHECK-NEXT: mov z5.d, z2.d1023; CHECK-NEXT: mov z6.d, z3.d1024; CHECK-NEXT: mov z4.d, z1.d1025; CHECK-NEXT: fminnm { z4.s, z5.s }, { z4.s, z5.s }, { z6.s, z7.s }1026; CHECK-NEXT: mov z0.d, z4.d1027; CHECK-NEXT: mov z1.d, z5.d1028; CHECK-NEXT: ret1029 %res = call { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.fminnm.x2.nxv4f32(<vscale x 4 x float> %zdn1, <vscale x 4 x float> %zdn2, <vscale x 4 x float> %zm1, <vscale x 4 x float> %zm2)1030 ret { <vscale x 4 x float>, <vscale x 4 x float> } %res1031}1032 1033define { <vscale x 2 x double>, <vscale x 2 x double> } @multi_vec_minnm_x2_f64(<vscale x 8 x half> %dummy, <vscale x 2 x double> %zdn1, <vscale x 2 x double> %zdn2, <vscale x 2 x double> %zm1, <vscale x 2 x double> %zm2) {1034; CHECK-LABEL: multi_vec_minnm_x2_f64:1035; CHECK: // %bb.0:1036; CHECK-NEXT: mov z7.d, z4.d1037; CHECK-NEXT: mov z5.d, z2.d1038; CHECK-NEXT: mov z6.d, z3.d1039; CHECK-NEXT: mov z4.d, z1.d1040; CHECK-NEXT: fminnm { z4.d, z5.d }, { z4.d, z5.d }, { z6.d, z7.d }1041; CHECK-NEXT: mov z0.d, z4.d1042; CHECK-NEXT: mov z1.d, z5.d1043; CHECK-NEXT: ret1044 %res = call { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sve.fminnm.x2.nxv2f64(<vscale x 2 x double> %zdn1, <vscale x 2 x double> %zdn2, <vscale x 2 x double> %zm1, <vscale x 2 x double> %zm2)1045 ret { <vscale x 2 x double>, <vscale x 2 x double> } %res1046}1047 1048; BFMINNM (Multi, x4)1049 1050define { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @multi_vec_minnm_x4_bf16(<vscale x 8 x bfloat> %zdn1, <vscale x 8 x bfloat> %zdn2, <vscale x 8 x bfloat> %zdn3, <vscale x 8 x bfloat> %zdn4, <vscale x 8 x bfloat> %zm1, <vscale x 8 x bfloat> %zm2, <vscale x 8 x bfloat> %zm3, <vscale x 8 x bfloat> %zm4) {1051; CHECK-LABEL: multi_vec_minnm_x4_bf16:1052; CHECK: // %bb.0:1053; CHECK-NEXT: // kill: def $z3 killed $z3 killed $z0_z1_z2_z3 def $z0_z1_z2_z31054; CHECK-NEXT: // kill: def $z7 killed $z7 killed $z4_z5_z6_z7 def $z4_z5_z6_z71055; CHECK-NEXT: // kill: def $z2 killed $z2 killed $z0_z1_z2_z3 def $z0_z1_z2_z31056; CHECK-NEXT: // kill: def $z6 killed $z6 killed $z4_z5_z6_z7 def $z4_z5_z6_z71057; CHECK-NEXT: // kill: def $z1 killed $z1 killed $z0_z1_z2_z3 def $z0_z1_z2_z31058; CHECK-NEXT: // kill: def $z5 killed $z5 killed $z4_z5_z6_z7 def $z4_z5_z6_z71059; CHECK-NEXT: // kill: def $z0 killed $z0 killed $z0_z1_z2_z3 def $z0_z1_z2_z31060; CHECK-NEXT: // kill: def $z4 killed $z4 killed $z4_z5_z6_z7 def $z4_z5_z6_z71061; CHECK-NEXT: bfminnm { z0.h - z3.h }, { z0.h - z3.h }, { z4.h - z7.h }1062; CHECK-NEXT: ret1063 %res = call { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } @llvm.aarch64.sve.fminnm.x4.nxv8bf16(<vscale x 8 x bfloat> %zdn1, <vscale x 8 x bfloat> %zdn2, <vscale x 8 x bfloat> %zdn3, <vscale x 8 x bfloat> %zdn4, <vscale x 8 x bfloat> %zm1, <vscale x 8 x bfloat> %zm2, <vscale x 8 x bfloat> %zm3, <vscale x 8 x bfloat> %zm4)1064 ret { <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat> } %res1065}1066 1067; FMINNM (Multi, x4)1068 1069define { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } @multi_vec_minnm_x4_f16(<vscale x 8 x half> %dummy, <vscale x 8 x half> %zdn1, <vscale x 8 x half> %zdn2, <vscale x 8 x half> %zdn3, <vscale x 8 x half> %zdn4, <vscale x 8 x half> %zm1, <vscale x 8 x half> %zm2, <vscale x 8 x half> %zm3, <vscale x 8 x half> %zm4) {1070; CHECK-LABEL: multi_vec_minnm_x4_f16:1071; CHECK: // %bb.0:1072; CHECK-NEXT: mov z30.d, z7.d1073; CHECK-NEXT: mov z27.d, z4.d1074; CHECK-NEXT: mov z29.d, z6.d1075; CHECK-NEXT: mov z26.d, z3.d1076; CHECK-NEXT: mov z28.d, z5.d1077; CHECK-NEXT: mov z25.d, z2.d1078; CHECK-NEXT: ldr z31, [x0]1079; CHECK-NEXT: mov z24.d, z1.d1080; CHECK-NEXT: fminnm { z24.h - z27.h }, { z24.h - z27.h }, { z28.h - z31.h }1081; CHECK-NEXT: mov z0.d, z24.d1082; CHECK-NEXT: mov z1.d, z25.d1083; CHECK-NEXT: mov z2.d, z26.d1084; CHECK-NEXT: mov z3.d, z27.d1085; CHECK-NEXT: ret1086 %res = call { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }1087 @llvm.aarch64.sve.fminnm.x4.nxv8f16(<vscale x 8 x half> %zdn1, <vscale x 8 x half> %zdn2, <vscale x 8 x half> %zdn3, <vscale x 8 x half> %zdn4,1088 <vscale x 8 x half> %zm1, <vscale x 8 x half> %zm2, <vscale x 8 x half> %zm3, <vscale x 8 x half> %zm4)1089 ret { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> } %res1090}1091 1092define { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } @multi_vec_minnm_x4_f32(<vscale x 8 x half> %dummy, <vscale x 4 x float> %zdn1, <vscale x 4 x float> %zdn2, <vscale x 4 x float> %zdn3, <vscale x 4 x float> %zdn4, <vscale x 4 x float> %zm1, <vscale x 4 x float> %zm2, <vscale x 4 x float> %zm3, <vscale x 4 x float> %zm4) {1093; CHECK-LABEL: multi_vec_minnm_x4_f32:1094; CHECK: // %bb.0:1095; CHECK-NEXT: mov z30.d, z7.d1096; CHECK-NEXT: mov z27.d, z4.d1097; CHECK-NEXT: mov z29.d, z6.d1098; CHECK-NEXT: mov z26.d, z3.d1099; CHECK-NEXT: mov z28.d, z5.d1100; CHECK-NEXT: mov z25.d, z2.d1101; CHECK-NEXT: ldr z31, [x0]1102; CHECK-NEXT: mov z24.d, z1.d1103; CHECK-NEXT: fminnm { z24.s - z27.s }, { z24.s - z27.s }, { z28.s - z31.s }1104; CHECK-NEXT: mov z0.d, z24.d1105; CHECK-NEXT: mov z1.d, z25.d1106; CHECK-NEXT: mov z2.d, z26.d1107; CHECK-NEXT: mov z3.d, z27.d1108; CHECK-NEXT: ret1109 %res = call { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }1110 @llvm.aarch64.sve.fminnm.x4.nxv4f32(<vscale x 4 x float> %zdn1, <vscale x 4 x float> %zdn2, <vscale x 4 x float> %zdn3, <vscale x 4 x float> %zdn4,1111 <vscale x 4 x float> %zm1, <vscale x 4 x float> %zm2, <vscale x 4 x float> %zm3, <vscale x 4 x float> %zm4)1112 ret { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> } %res1113}1114 1115define { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } @multi_vec_minnm_x4_f64(<vscale x 8 x half> %dummy, <vscale x 2 x double> %zdn1, <vscale x 2 x double> %zdn2, <vscale x 2 x double> %zdn3, <vscale x 2 x double> %zdn4, <vscale x 2 x double> %zm1, <vscale x 2 x double> %zm2, <vscale x 2 x double> %zm3, <vscale x 2 x double> %zm4) {1116; CHECK-LABEL: multi_vec_minnm_x4_f64:1117; CHECK: // %bb.0:1118; CHECK-NEXT: mov z30.d, z7.d1119; CHECK-NEXT: mov z27.d, z4.d1120; CHECK-NEXT: mov z29.d, z6.d1121; CHECK-NEXT: mov z26.d, z3.d1122; CHECK-NEXT: mov z28.d, z5.d1123; CHECK-NEXT: mov z25.d, z2.d1124; CHECK-NEXT: ldr z31, [x0]1125; CHECK-NEXT: mov z24.d, z1.d1126; CHECK-NEXT: fminnm { z24.d - z27.d }, { z24.d - z27.d }, { z28.d - z31.d }1127; CHECK-NEXT: mov z0.d, z24.d1128; CHECK-NEXT: mov z1.d, z25.d1129; CHECK-NEXT: mov z2.d, z26.d1130; CHECK-NEXT: mov z3.d, z27.d1131; CHECK-NEXT: ret1132 %res = call { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> }1133 @llvm.aarch64.sve.fminnm.x4.nxv2f64(<vscale x 2 x double> %zdn1, <vscale x 2 x double> %zdn2, <vscale x 2 x double> %zdn3, <vscale x 2 x double> %zdn4,1134 <vscale x 2 x double> %zm1, <vscale x 2 x double> %zm2, <vscale x 2 x double> %zm3, <vscale x 2 x double> %zm4)1135 ret { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> } %res1136}1137 1138declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.smin.single.x2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>)1139declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.smin.single.x2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>)1140declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.smin.single.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>)1141declare { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.smin.single.x2.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>)1142 1143declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.umin.single.x2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>)1144declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.umin.single.x2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>)1145declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.umin.single.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>)1146declare { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.umin.single.x2.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>)1147 1148declare { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.fmin.single.x2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>)1149declare { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.fmin.single.x2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>)1150declare { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sve.fmin.single.x2.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>)1151 1152declare { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.smin.single.x4.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>)1153declare { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.smin.single.x4.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>)1154declare { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.smin.single.x4.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>)1155declare { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.smin.single.x4.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>)1156 1157declare { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.umin.single.x4.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>)1158declare { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.umin.single.x4.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>)1159declare { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.umin.single.x4.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>)1160declare { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.umin.single.x4.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>)1161 1162declare { <vscale x 8 x half>, <vscale x 8 x half> , <vscale x 8 x half>, <vscale x 8 x half> }1163 @llvm.aarch64.sve.fmin.single.x4.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>)1164declare { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }1165 @llvm.aarch64.sve.fmin.single.x4.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>)1166declare { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> }1167 @llvm.aarch64.sve.fmin.single.x4.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>)1168 1169declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.smin.x2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>)1170declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.smin.x2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> )1171declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.smin.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>)1172declare { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.smin.x2.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>)1173 1174declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.umin.x2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>)1175declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.umin.x2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> )1176declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.umin.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>)1177declare { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.umin.x2.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>)1178 1179declare { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.fmin.x2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>)1180declare { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.fmin.x2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>)1181declare { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sve.fmin.x2.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>)1182 1183declare { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }1184 @llvm.aarch64.sve.smin.x4.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>)1185declare { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }1186 @llvm.aarch64.sve.smin.x4.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>)1187declare { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }1188 @llvm.aarch64.sve.smin.x4.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>)1189declare { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }1190 @llvm.aarch64.sve.smin.x4.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>)1191 1192declare { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }1193 @llvm.aarch64.sve.umin.x4.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>)1194declare { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }1195 @llvm.aarch64.sve.umin.x4.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>)1196declare { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }1197 @llvm.aarch64.sve.umin.x4.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>)1198declare { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }1199 @llvm.aarch64.sve.umin.x4.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>)1200 1201declare { <vscale x 8 x half>, <vscale x 8 x half> , <vscale x 8 x half>, <vscale x 8 x half> }1202 @llvm.aarch64.sve.fmin.x4.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>)1203declare { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }1204 @llvm.aarch64.sve.fmin.x4.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>)1205declare { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> }1206 @llvm.aarch64.sve.fmin.x4.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>)1207 1208declare { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.fminnm.single.x2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>)1209declare { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.fminnm.single.x2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>)1210declare { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sve.fminnm.single.x2.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>)1211 1212declare { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }1213 @llvm.aarch64.sve.fminnm.single.x4.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>)1214declare { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }1215 @llvm.aarch64.sve.fminnm.single.x4.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>)1216declare { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> }1217 @llvm.aarch64.sve.fminnm.single.x4.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>)1218 1219declare { <vscale x 8 x half>, <vscale x 8 x half> } @llvm.aarch64.sve.fminnm.x2.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>)1220declare { <vscale x 4 x float>, <vscale x 4 x float> } @llvm.aarch64.sve.fminnm.x2.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>)1221declare { <vscale x 2 x double>, <vscale x 2 x double> } @llvm.aarch64.sve.fminnm.x2.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>)1222 1223declare { <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half> }1224 @llvm.aarch64.sve.fminnm.x4.nxv8f16(<vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>, <vscale x 8 x half>)1225declare { <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float> }1226 @llvm.aarch64.sve.fminnm.x4.nxv4f32(<vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>, <vscale x 4 x float>)1227declare { <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double> }1228 @llvm.aarch64.sve.fminnm.x4.nxv2f64(<vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>, <vscale x 2 x double>)1229