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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -force-streaming -verify-machineinstrs < %s | FileCheck %s3 4target triple = "aarch64-linux"5 6define void @mop4a_za16_fp8_1x1(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {7; CHECK-LABEL: mop4a_za16_fp8_1x1:8; CHECK: // %bb.0:9; CHECK-NEXT: mov z24.d, z1.d10; CHECK-NEXT: fmop4a za0.h, z0.b, z24.b11; CHECK-NEXT: ret12 call void @llvm.aarch64.sme.fp8.fmop4a.za16.1x1(i32 0, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm)13 ret void14}15 16define void @mop4a_za16_fp8_1x2(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2) #0 {17; CHECK-LABEL: mop4a_za16_fp8_1x2:18; CHECK: // %bb.0:19; CHECK-NEXT: mov z25.d, z2.d20; CHECK-NEXT: mov z24.d, z1.d21; CHECK-NEXT: fmop4a za0.h, z0.b, { z24.b, z25.b }22; CHECK-NEXT: ret23 call void @llvm.aarch64.sme.fp8.fmop4a.za16.1x2(i32 0, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2)24 ret void25}26 27define void @mop4a_za16_fp8_2x1(<vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zm) #0 {28; CHECK-LABEL: mop4a_za16_fp8_2x1:29; CHECK: // %bb.0:30; CHECK-NEXT: mov z24.d, z2.d31; CHECK-NEXT: // kill: def $z1 killed $z1 killed $z0_z1 def $z0_z132; CHECK-NEXT: // kill: def $z0 killed $z0 killed $z0_z1 def $z0_z133; CHECK-NEXT: fmop4a za0.h, { z0.b, z1.b }, z24.b34; CHECK-NEXT: ret35 call void @llvm.aarch64.sme.fp8.fmop4a.za16.2x1(i32 0, <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zm)36 ret void37}38 39define void @mop4a_za16_fp8_2x2(<vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2) #0 {40; CHECK-LABEL: mop4a_za16_fp8_2x2:41; CHECK: // %bb.0:42; CHECK-NEXT: mov z25.d, z3.d43; CHECK-NEXT: // kill: def $z1 killed $z1 killed $z0_z1 def $z0_z144; CHECK-NEXT: mov z24.d, z2.d45; CHECK-NEXT: // kill: def $z0 killed $z0 killed $z0_z1 def $z0_z146; CHECK-NEXT: fmop4a za0.h, { z0.b, z1.b }, { z24.b, z25.b }47; CHECK-NEXT: ret48 call void @llvm.aarch64.sme.fp8.fmop4a.za16.2x2(i32 0, <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2)49 ret void50}51 52define void @mop4a_za32_fp8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {53; CHECK-LABEL: mop4a_za32_fp8:54; CHECK: // %bb.0:55; CHECK-NEXT: mov z24.d, z1.d56; CHECK-NEXT: fmop4a za0.s, z0.b, z24.b57; CHECK-NEXT: ret58 call void @llvm.aarch64.sme.fp8.fmop4a.za32.1x1(i32 0, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm)59 ret void60}61 62define void @mop4a_za32_fp8_1x2(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2) #0 {63; CHECK-LABEL: mop4a_za32_fp8_1x2:64; CHECK: // %bb.0:65; CHECK-NEXT: mov z25.d, z2.d66; CHECK-NEXT: mov z24.d, z1.d67; CHECK-NEXT: fmop4a za0.s, z0.b, { z24.b, z25.b }68; CHECK-NEXT: ret69 call void @llvm.aarch64.sme.fp8.fmop4a.za32.1x2(i32 0, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2)70 ret void71}72 73define void @mop4a_za32_fp8_2x1(<vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zm) #0 {74; CHECK-LABEL: mop4a_za32_fp8_2x1:75; CHECK: // %bb.0:76; CHECK-NEXT: mov z24.d, z2.d77; CHECK-NEXT: // kill: def $z1 killed $z1 killed $z0_z1 def $z0_z178; CHECK-NEXT: // kill: def $z0 killed $z0 killed $z0_z1 def $z0_z179; CHECK-NEXT: fmop4a za0.s, { z0.b, z1.b }, z24.b80; CHECK-NEXT: ret81 call void @llvm.aarch64.sme.fp8.fmop4a.za32.2x1(i32 0, <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zm)82 ret void83}84 85define void @mop4a_za32_fp8_2x2(<vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2) #0 {86; CHECK-LABEL: mop4a_za32_fp8_2x2:87; CHECK: // %bb.0:88; CHECK-NEXT: mov z25.d, z3.d89; CHECK-NEXT: // kill: def $z1 killed $z1 killed $z0_z1 def $z0_z190; CHECK-NEXT: mov z24.d, z2.d91; CHECK-NEXT: // kill: def $z0 killed $z0 killed $z0_z1 def $z0_z192; CHECK-NEXT: fmop4a za0.s, { z0.b, z1.b }, { z24.b, z25.b }93; CHECK-NEXT: ret94 call void @llvm.aarch64.sme.fp8.fmop4a.za32.2x2(i32 0, <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2)95 ret void96}97 98attributes #0 = {nounwind "target-features" = "+sme-f8f16,+sme-f8f32,+sme2p1,+sme-mop4" }99