420 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 42; RUN: llc -force-streaming -verify-machineinstrs < %s | FileCheck %s3 4target triple = "aarch64-linux"5 6; Widening7define void @mop4a_za32_s8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {8; CHECK-LABEL: mop4a_za32_s8:9; CHECK: // %bb.0:10; CHECK-NEXT: mov z24.d, z1.d11; CHECK-NEXT: smop4a za0.s, z0.b, z24.b12; CHECK-NEXT: ret13 call void @llvm.aarch64.sme.smop4a.wide.1x1.nxv16i8(i32 0, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm)14 ret void15}16 17define void @mop4s_za32_s8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {18; CHECK-LABEL: mop4s_za32_s8:19; CHECK: // %bb.0:20; CHECK-NEXT: mov z24.d, z1.d21; CHECK-NEXT: smop4s za0.s, z0.b, z24.b22; CHECK-NEXT: ret23 call void @llvm.aarch64.sme.smop4s.wide.1x1.nxv16i8(i32 0, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm)24 ret void25}26 27define void @mop4a_za32_u8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {28; CHECK-LABEL: mop4a_za32_u8:29; CHECK: // %bb.0:30; CHECK-NEXT: mov z24.d, z1.d31; CHECK-NEXT: umop4a za0.s, z0.b, z24.b32; CHECK-NEXT: ret33 call void @llvm.aarch64.sme.umop4a.wide.1x1.nxv16i8(i32 0, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm)34 ret void35}36 37define void @mop4s_za32_u8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {38; CHECK-LABEL: mop4s_za32_u8:39; CHECK: // %bb.0:40; CHECK-NEXT: mov z24.d, z1.d41; CHECK-NEXT: umop4s za0.s, z0.b, z24.b42; CHECK-NEXT: ret43 call void @llvm.aarch64.sme.umop4s.wide.1x1.nxv16i8(i32 0, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm)44 ret void45}46 47define void @mop4a_za32_s8_u8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {48; CHECK-LABEL: mop4a_za32_s8_u8:49; CHECK: // %bb.0:50; CHECK-NEXT: mov z24.d, z1.d51; CHECK-NEXT: sumop4a za0.s, z0.b, z24.b52; CHECK-NEXT: ret53 call void @llvm.aarch64.sme.sumop4a.wide.1x1.nxv16i8(i32 0, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm)54 ret void55}56 57define void @mop4s_za32_s8_u8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {58; CHECK-LABEL: mop4s_za32_s8_u8:59; CHECK: // %bb.0:60; CHECK-NEXT: mov z24.d, z1.d61; CHECK-NEXT: sumop4s za0.s, z0.b, z24.b62; CHECK-NEXT: ret63 call void @llvm.aarch64.sme.sumop4s.wide.1x1.nxv16i8(i32 0, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm)64 ret void65}66 67define void @mop4a_za32_u8_s8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {68; CHECK-LABEL: mop4a_za32_u8_s8:69; CHECK: // %bb.0:70; CHECK-NEXT: mov z24.d, z1.d71; CHECK-NEXT: usmop4a za0.s, z0.b, z24.b72; CHECK-NEXT: ret73 call void @llvm.aarch64.sme.usmop4a.wide.1x1.nxv16i8(i32 0, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm)74 ret void75}76 77define void @mop4s_za32_u8_s8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {78; CHECK-LABEL: mop4s_za32_u8_s8:79; CHECK: // %bb.0:80; CHECK-NEXT: mov z24.d, z1.d81; CHECK-NEXT: usmop4s za0.s, z0.b, z24.b82; CHECK-NEXT: ret83 call void @llvm.aarch64.sme.usmop4s.wide.1x1.nxv16i8(i32 0, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm)84 ret void85}86 87define void @mop4a_za32_s16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {88; CHECK-LABEL: mop4a_za32_s16:89; CHECK: // %bb.0:90; CHECK-NEXT: mov z24.d, z1.d91; CHECK-NEXT: smop4a za0.s, z0.h, z24.h92; CHECK-NEXT: ret93 call void @llvm.aarch64.sme.smop4a.wide.1x1.nxv8i16(i32 0, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm)94 ret void95}96 97define void @mop4s_za32_s16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {98; CHECK-LABEL: mop4s_za32_s16:99; CHECK: // %bb.0:100; CHECK-NEXT: mov z24.d, z1.d101; CHECK-NEXT: smop4s za0.s, z0.h, z24.h102; CHECK-NEXT: ret103 call void @llvm.aarch64.sme.smop4s.wide.1x1.nxv8i16(i32 0, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm)104 ret void105}106 107define void @mop4a_za32_u16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {108; CHECK-LABEL: mop4a_za32_u16:109; CHECK: // %bb.0:110; CHECK-NEXT: mov z24.d, z1.d111; CHECK-NEXT: umop4a za0.s, z0.h, z24.h112; CHECK-NEXT: ret113 call void @llvm.aarch64.sme.umop4a.wide.1x1.nxv8i16(i32 0, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm)114 ret void115}116 117define void @mop4s_za32_u16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {118; CHECK-LABEL: mop4s_za32_u16:119; CHECK: // %bb.0:120; CHECK-NEXT: mov z24.d, z1.d121; CHECK-NEXT: umop4s za0.s, z0.h, z24.h122; CHECK-NEXT: ret123 call void @llvm.aarch64.sme.umop4s.wide.1x1.nxv8i16(i32 0, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm)124 ret void125}126 127define void @mop4a_za32_f16(<vscale x 8 x half> %zn, <vscale x 8 x half> %zm) #0 {128; CHECK-LABEL: mop4a_za32_f16:129; CHECK: // %bb.0:130; CHECK-NEXT: mov z24.d, z1.d131; CHECK-NEXT: fmop4a za0.s, z0.h, z24.h132; CHECK-NEXT: ret133 call void @llvm.aarch64.sme.mop4a.wide.1x1.nxv8f16(i32 0, <vscale x 8 x half> %zn, <vscale x 8 x half> %zm)134 ret void135}136 137define void @mop4s_za32_f16(<vscale x 8 x half> %zn, <vscale x 8 x half> %zm) #0 {138; CHECK-LABEL: mop4s_za32_f16:139; CHECK: // %bb.0:140; CHECK-NEXT: mov z24.d, z1.d141; CHECK-NEXT: fmop4s za0.s, z0.h, z24.h142; CHECK-NEXT: ret143 call void @llvm.aarch64.sme.mop4s.wide.1x1.nxv8f16(i32 0, <vscale x 8 x half> %zn, <vscale x 8 x half> %zm)144 ret void145}146 147define void @mop4a_za32_bf16(<vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm) #0 {148; CHECK-LABEL: mop4a_za32_bf16:149; CHECK: // %bb.0:150; CHECK-NEXT: mov z24.d, z1.d151; CHECK-NEXT: bfmop4a za0.s, z0.h, z24.h152; CHECK-NEXT: ret153 call void @llvm.aarch64.sme.mop4a.wide.1x1.nxv8bf16(i32 0, <vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm)154 ret void155}156 157define void @mop4s_za32_bf16(<vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm) #0 {158; CHECK-LABEL: mop4s_za32_bf16:159; CHECK: // %bb.0:160; CHECK-NEXT: mov z24.d, z1.d161; CHECK-NEXT: bfmop4s za0.s, z0.h, z24.h162; CHECK-NEXT: ret163 call void @llvm.aarch64.sme.mop4s.wide.1x1.nxv8bf16(i32 0, <vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm)164 ret void165}166 167define void @mop4a_za64_s16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {168; CHECK-LABEL: mop4a_za64_s16:169; CHECK: // %bb.0:170; CHECK-NEXT: mov z24.d, z1.d171; CHECK-NEXT: smop4a za0.d, z0.h, z24.h172; CHECK-NEXT: ret173 call void @llvm.aarch64.sme.smop4a.za64.wide.1x1.nxv8i16(i32 0, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm)174 ret void175}176 177define void @mop4s_za64_s16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {178; CHECK-LABEL: mop4s_za64_s16:179; CHECK: // %bb.0:180; CHECK-NEXT: mov z24.d, z1.d181; CHECK-NEXT: smop4s za0.d, z0.h, z24.h182; CHECK-NEXT: ret183 call void @llvm.aarch64.sme.smop4s.za64.wide.1x1.nxv8i16(i32 0, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm)184 ret void185}186 187define void @mop4a_za64_u16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {188; CHECK-LABEL: mop4a_za64_u16:189; CHECK: // %bb.0:190; CHECK-NEXT: mov z24.d, z1.d191; CHECK-NEXT: umop4a za0.d, z0.h, z24.h192; CHECK-NEXT: ret193 call void @llvm.aarch64.sme.umop4a.za64.wide.1x1.nxv8i16(i32 0, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm)194 ret void195}196 197define void @mop4s_za64_u16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {198; CHECK-LABEL: mop4s_za64_u16:199; CHECK: // %bb.0:200; CHECK-NEXT: mov z24.d, z1.d201; CHECK-NEXT: umop4s za0.d, z0.h, z24.h202; CHECK-NEXT: ret203 call void @llvm.aarch64.sme.umop4s.za64.wide.1x1.nxv8i16(i32 0, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm)204 ret void205}206 207define void @mop4a_za64_s16_u16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {208; CHECK-LABEL: mop4a_za64_s16_u16:209; CHECK: // %bb.0:210; CHECK-NEXT: mov z24.d, z1.d211; CHECK-NEXT: sumop4a za0.d, z0.h, z24.h212; CHECK-NEXT: ret213 call void @llvm.aarch64.sme.sumop4a.za64.wide.1x1.nxv8i16(i32 0, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm)214 ret void215}216 217define void @mop4s_za64_s16_u16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {218; CHECK-LABEL: mop4s_za64_s16_u16:219; CHECK: // %bb.0:220; CHECK-NEXT: mov z24.d, z1.d221; CHECK-NEXT: sumop4s za0.d, z0.h, z24.h222; CHECK-NEXT: ret223 call void @llvm.aarch64.sme.sumop4s.za64.wide.1x1.nxv8i16(i32 0, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm)224 ret void225}226 227define void @mop4a_za64_u16_s16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {228; CHECK-LABEL: mop4a_za64_u16_s16:229; CHECK: // %bb.0:230; CHECK-NEXT: mov z24.d, z1.d231; CHECK-NEXT: usmop4a za0.d, z0.h, z24.h232; CHECK-NEXT: ret233 call void @llvm.aarch64.sme.usmop4a.za64.wide.1x1.nxv8i16(i32 0, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm)234 ret void235}236 237define void @mop4s_za64_u16_s16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {238; CHECK-LABEL: mop4s_za64_u16_s16:239; CHECK: // %bb.0:240; CHECK-NEXT: mov z24.d, z1.d241; CHECK-NEXT: usmop4s za0.d, z0.h, z24.h242; CHECK-NEXT: ret243 call void @llvm.aarch64.sme.usmop4s.za64.wide.1x1.nxv8i16(i32 0, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm)244 ret void245}246 247; Non-widening248define void @mop4a_za16_f16(<vscale x 8 x half> %zn, <vscale x 8 x half> %zm) #0 {249; CHECK-LABEL: mop4a_za16_f16:250; CHECK: // %bb.0:251; CHECK-NEXT: mov z24.d, z1.d252; CHECK-NEXT: fmop4a za0.h, z0.h, z24.h253; CHECK-NEXT: ret254 call void @llvm.aarch64.sme.mop4a.1x1.nxv8f16(i32 0, <vscale x 8 x half> %zn, <vscale x 8 x half> %zm)255 ret void256}257 258define void @mop4s_za16_f16(<vscale x 8 x half> %zn, <vscale x 8 x half> %zm) #0 {259; CHECK-LABEL: mop4s_za16_f16:260; CHECK: // %bb.0:261; CHECK-NEXT: mov z24.d, z1.d262; CHECK-NEXT: fmop4s za0.h, z0.h, z24.h263; CHECK-NEXT: ret264 call void @llvm.aarch64.sme.mop4s.1x1.nxv8f16(i32 0, <vscale x 8 x half> %zn, <vscale x 8 x half> %zm)265 ret void266}267 268define void @mop4a_za32_f32(<vscale x 4 x float> %zn, <vscale x 4 x float> %zm) #0 {269; CHECK-LABEL: mop4a_za32_f32:270; CHECK: // %bb.0:271; CHECK-NEXT: mov z24.d, z1.d272; CHECK-NEXT: fmop4a za0.s, z0.s, z24.s273; CHECK-NEXT: ret274 call void @llvm.aarch64.sme.mop4a.1x1.nxv4f32(i32 0, <vscale x 4 x float> %zn, <vscale x 4 x float> %zm)275 ret void276}277 278define void @mop4s_za32_f32(<vscale x 4 x float> %zn, <vscale x 4 x float> %zm) #0 {279; CHECK-LABEL: mop4s_za32_f32:280; CHECK: // %bb.0:281; CHECK-NEXT: mov z24.d, z1.d282; CHECK-NEXT: fmop4s za0.s, z0.s, z24.s283; CHECK-NEXT: ret284 call void @llvm.aarch64.sme.mop4s.1x1.nxv4f32(i32 0, <vscale x 4 x float> %zn, <vscale x 4 x float> %zm)285 ret void286}287 288define void @mop4a_za64_f64(<vscale x 2 x double> %zn, <vscale x 2 x double> %zm) #0 {289; CHECK-LABEL: mop4a_za64_f64:290; CHECK: // %bb.0:291; CHECK-NEXT: mov z24.d, z1.d292; CHECK-NEXT: fmop4a za0.d, z0.d, z24.d293; CHECK-NEXT: ret294 call void @llvm.aarch64.sme.mop4a.1x1.nxv2f64(i32 0, <vscale x 2 x double> %zn, <vscale x 2 x double> %zm)295 ret void296}297 298define void @mop4s_za64_f64(<vscale x 2 x double> %zn, <vscale x 2 x double> %zm) #0 {299; CHECK-LABEL: mop4s_za64_f64:300; CHECK: // %bb.0:301; CHECK-NEXT: mov z24.d, z1.d302; CHECK-NEXT: fmop4s za0.d, z0.d, z24.d303; CHECK-NEXT: ret304 call void @llvm.aarch64.sme.mop4s.1x1.nxv2f64(i32 0, <vscale x 2 x double> %zn, <vscale x 2 x double> %zm)305 ret void306}307 308define void @mop4a_za16_bf16(<vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm) #0 {309; CHECK-LABEL: mop4a_za16_bf16:310; CHECK: // %bb.0:311; CHECK-NEXT: mov z24.d, z1.d312; CHECK-NEXT: bfmop4a za0.h, z0.h, z24.h313; CHECK-NEXT: ret314 call void @llvm.aarch64.sme.mop4a.1x1.nxv8bf16(i32 0, <vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm)315 ret void316}317 318define void @mop4s_za16_bf16(<vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm) #0 {319; CHECK-LABEL: mop4s_za16_bf16:320; CHECK: // %bb.0:321; CHECK-NEXT: mov z24.d, z1.d322; CHECK-NEXT: bfmop4s za0.h, z0.h, z24.h323; CHECK-NEXT: ret324 call void @llvm.aarch64.sme.mop4s.1x1.nxv8bf16(i32 0, <vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm)325 ret void326}327 328; Tile limits329define void @mop4s_za32_s8_limit(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm) #0 {330; CHECK-LABEL: mop4s_za32_s8_limit:331; CHECK: // %bb.0:332; CHECK-NEXT: mov z24.d, z1.d333; CHECK-NEXT: smop4s za3.s, z0.b, z24.b334; CHECK-NEXT: ret335 call void @llvm.aarch64.sme.smop4s.wide.1x1.nxv16i8(i32 3, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm)336 ret void337}338 339define void @mop4s_za32_s16_limit(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {340; CHECK-LABEL: mop4s_za32_s16_limit:341; CHECK: // %bb.0:342; CHECK-NEXT: mov z24.d, z1.d343; CHECK-NEXT: smop4s za3.s, z0.h, z24.h344; CHECK-NEXT: ret345 call void @llvm.aarch64.sme.smop4s.wide.1x1.nxv8i16(i32 3, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm)346 ret void347}348 349define void @mop4s_za32_f16_limit(<vscale x 8 x half> %zn, <vscale x 8 x half> %zm) #0 {350; CHECK-LABEL: mop4s_za32_f16_limit:351; CHECK: // %bb.0:352; CHECK-NEXT: mov z24.d, z1.d353; CHECK-NEXT: fmop4s za3.s, z0.h, z24.h354; CHECK-NEXT: ret355 call void @llvm.aarch64.sme.mop4s.wide.1x1.nxv8f16(i32 3, <vscale x 8 x half> %zn, <vscale x 8 x half> %zm)356 ret void357}358 359define void @mop4s_za32_bf16_limit(<vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm) #0 {360; CHECK-LABEL: mop4s_za32_bf16_limit:361; CHECK: // %bb.0:362; CHECK-NEXT: mov z24.d, z1.d363; CHECK-NEXT: bfmop4s za3.s, z0.h, z24.h364; CHECK-NEXT: ret365 call void @llvm.aarch64.sme.mop4s.wide.1x1.nxv8bf16(i32 3, <vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm)366 ret void367}368 369define void @mop4s_za64_s16_limit(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm) #0 {370; CHECK-LABEL: mop4s_za64_s16_limit:371; CHECK: // %bb.0:372; CHECK-NEXT: mov z24.d, z1.d373; CHECK-NEXT: smop4s za7.d, z0.h, z24.h374; CHECK-NEXT: ret375 call void @llvm.aarch64.sme.smop4s.za64.wide.1x1.nxv8i16(i32 7, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm)376 ret void377}378 379define void @mop4s_za64_f64_limit(<vscale x 2 x double> %zn, <vscale x 2 x double> %zm) #0 {380; CHECK-LABEL: mop4s_za64_f64_limit:381; CHECK: // %bb.0:382; CHECK-NEXT: mov z24.d, z1.d383; CHECK-NEXT: fmop4s za7.d, z0.d, z24.d384; CHECK-NEXT: ret385 call void @llvm.aarch64.sme.mop4s.1x1.nxv2f64(i32 7, <vscale x 2 x double> %zn, <vscale x 2 x double> %zm)386 ret void387}388 389define void @mop4s_za32_f32_limit(<vscale x 4 x float> %zn, <vscale x 4 x float> %zm) #0 {390; CHECK-LABEL: mop4s_za32_f32_limit:391; CHECK: // %bb.0:392; CHECK-NEXT: mov z24.d, z1.d393; CHECK-NEXT: fmop4s za3.s, z0.s, z24.s394; CHECK-NEXT: ret395 call void @llvm.aarch64.sme.mop4s.1x1.nxv4f32(i32 3, <vscale x 4 x float> %zn, <vscale x 4 x float> %zm)396 ret void397}398 399define void @mop4s_za16_f16_limit(<vscale x 8 x half> %zn, <vscale x 8 x half> %zm) #0 {400; CHECK-LABEL: mop4s_za16_f16_limit:401; CHECK: // %bb.0:402; CHECK-NEXT: mov z24.d, z1.d403; CHECK-NEXT: fmop4s za1.h, z0.h, z24.h404; CHECK-NEXT: ret405 call void @llvm.aarch64.sme.mop4s.1x1.nxv8f16(i32 1, <vscale x 8 x half> %zn, <vscale x 8 x half> %zm)406 ret void407}408 409define void @mop4s_za16_bf16_limit(<vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm) #0 {410; CHECK-LABEL: mop4s_za16_bf16_limit:411; CHECK: // %bb.0:412; CHECK-NEXT: mov z24.d, z1.d413; CHECK-NEXT: bfmop4s za1.h, z0.h, z24.h414; CHECK-NEXT: ret415 call void @llvm.aarch64.sme.mop4s.1x1.nxv8bf16(i32 1, <vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm)416 ret void417}418 419attributes #0 = {nounwind "target-features" = "+sme-i16i64,+sme-f64f64,+sme-b16b16,+sme2p1,+bf16,+sme-f16f16,+sme-mop4" }420