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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 42; RUN: llc -force-streaming -verify-machineinstrs < %s | FileCheck %s3 4target triple = "aarch64-linux"5 6; Widening7define void @mop4a_za32_s8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2) #0 {8; CHECK-LABEL: mop4a_za32_s8:9; CHECK: // %bb.0:10; CHECK-NEXT: mov z25.d, z2.d11; CHECK-NEXT: mov z24.d, z1.d12; CHECK-NEXT: smop4a za0.s, z0.b, { z24.b, z25.b }13; CHECK-NEXT: ret14 call void @llvm.aarch64.sme.smop4a.wide.1x2.nxv16i8(i32 0, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2)15 ret void16}17 18define void @mop4s_za32_s8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2) #0 {19; CHECK-LABEL: mop4s_za32_s8:20; CHECK: // %bb.0:21; CHECK-NEXT: mov z25.d, z2.d22; CHECK-NEXT: mov z24.d, z1.d23; CHECK-NEXT: smop4s za0.s, z0.b, { z24.b, z25.b }24; CHECK-NEXT: ret25 call void @llvm.aarch64.sme.smop4s.wide.1x2.nxv16i8(i32 0, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2)26 ret void27}28 29define void @mop4a_za32_u8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2) #0 {30; CHECK-LABEL: mop4a_za32_u8:31; CHECK: // %bb.0:32; CHECK-NEXT: mov z25.d, z2.d33; CHECK-NEXT: mov z24.d, z1.d34; CHECK-NEXT: umop4a za0.s, z0.b, { z24.b, z25.b }35; CHECK-NEXT: ret36 call void @llvm.aarch64.sme.umop4a.wide.1x2.nxv16i8(i32 0, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2)37 ret void38}39 40define void @mop4s_za32_u8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2) #0 {41; CHECK-LABEL: mop4s_za32_u8:42; CHECK: // %bb.0:43; CHECK-NEXT: mov z25.d, z2.d44; CHECK-NEXT: mov z24.d, z1.d45; CHECK-NEXT: umop4s za0.s, z0.b, { z24.b, z25.b }46; CHECK-NEXT: ret47 call void @llvm.aarch64.sme.umop4s.wide.1x2.nxv16i8(i32 0, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2)48 ret void49}50 51define void @mop4a_za32_s8_u8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2) #0 {52; CHECK-LABEL: mop4a_za32_s8_u8:53; CHECK: // %bb.0:54; CHECK-NEXT: mov z25.d, z2.d55; CHECK-NEXT: mov z24.d, z1.d56; CHECK-NEXT: sumop4a za0.s, z0.b, { z24.b, z25.b }57; CHECK-NEXT: ret58 call void @llvm.aarch64.sme.sumop4a.wide.1x2.nxv16i8(i32 0, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2)59 ret void60}61 62define void @mop4s_za32_s8_u8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2) #0 {63; CHECK-LABEL: mop4s_za32_s8_u8:64; CHECK: // %bb.0:65; CHECK-NEXT: mov z25.d, z2.d66; CHECK-NEXT: mov z24.d, z1.d67; CHECK-NEXT: sumop4s za0.s, z0.b, { z24.b, z25.b }68; CHECK-NEXT: ret69 call void @llvm.aarch64.sme.sumop4s.wide.1x2.nxv16i8(i32 0, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2)70 ret void71}72 73define void @mop4a_za32_u8_s8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2) #0 {74; CHECK-LABEL: mop4a_za32_u8_s8:75; CHECK: // %bb.0:76; CHECK-NEXT: mov z25.d, z2.d77; CHECK-NEXT: mov z24.d, z1.d78; CHECK-NEXT: usmop4a za0.s, z0.b, { z24.b, z25.b }79; CHECK-NEXT: ret80 call void @llvm.aarch64.sme.usmop4a.wide.1x2.nxv16i8(i32 0, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2)81 ret void82}83 84define void @mop4s_za32_u8_s8(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2) #0 {85; CHECK-LABEL: mop4s_za32_u8_s8:86; CHECK: // %bb.0:87; CHECK-NEXT: mov z25.d, z2.d88; CHECK-NEXT: mov z24.d, z1.d89; CHECK-NEXT: usmop4s za0.s, z0.b, { z24.b, z25.b }90; CHECK-NEXT: ret91 call void @llvm.aarch64.sme.usmop4s.wide.1x2.nxv16i8(i32 0, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2)92 ret void93}94 95 96define void @mop4a_za32_s16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm1, <vscale x 8 x i16> %zm2) #0 {97; CHECK-LABEL: mop4a_za32_s16:98; CHECK: // %bb.0:99; CHECK-NEXT: mov z25.d, z2.d100; CHECK-NEXT: mov z24.d, z1.d101; CHECK-NEXT: smop4a za0.s, z0.h, { z24.h, z25.h }102; CHECK-NEXT: ret103 call void @llvm.aarch64.sme.smop4a.wide.1x2.nxv8i16(i32 0, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm1, <vscale x 8 x i16> %zm2)104 ret void105}106 107define void @mop4s_za32_s16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm1, <vscale x 8 x i16> %zm2) #0 {108; CHECK-LABEL: mop4s_za32_s16:109; CHECK: // %bb.0:110; CHECK-NEXT: mov z25.d, z2.d111; CHECK-NEXT: mov z24.d, z1.d112; CHECK-NEXT: smop4s za0.s, z0.h, { z24.h, z25.h }113; CHECK-NEXT: ret114 call void @llvm.aarch64.sme.smop4s.wide.1x2.nxv8i16(i32 0, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm1, <vscale x 8 x i16> %zm2)115 ret void116}117 118define void @mop4a_za32_u16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm1, <vscale x 8 x i16> %zm2) #0 {119; CHECK-LABEL: mop4a_za32_u16:120; CHECK: // %bb.0:121; CHECK-NEXT: mov z25.d, z2.d122; CHECK-NEXT: mov z24.d, z1.d123; CHECK-NEXT: umop4a za0.s, z0.h, { z24.h, z25.h }124; CHECK-NEXT: ret125 call void @llvm.aarch64.sme.umop4a.wide.1x2.nxv8i16(i32 0, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm1, <vscale x 8 x i16> %zm2)126 ret void127}128 129define void @mop4s_za32_u16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm1, <vscale x 8 x i16> %zm2) #0 {130; CHECK-LABEL: mop4s_za32_u16:131; CHECK: // %bb.0:132; CHECK-NEXT: mov z25.d, z2.d133; CHECK-NEXT: mov z24.d, z1.d134; CHECK-NEXT: umop4s za0.s, z0.h, { z24.h, z25.h }135; CHECK-NEXT: ret136 call void @llvm.aarch64.sme.umop4s.wide.1x2.nxv8i16(i32 0, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm1, <vscale x 8 x i16> %zm2)137 ret void138}139 140define void @mop4a_za32_f16(<vscale x 8 x half> %zn, <vscale x 8 x half> %zm1, <vscale x 8 x half> %zm2) #0 {141; CHECK-LABEL: mop4a_za32_f16:142; CHECK: // %bb.0:143; CHECK-NEXT: mov z25.d, z2.d144; CHECK-NEXT: mov z24.d, z1.d145; CHECK-NEXT: fmop4a za0.s, z0.h, { z24.h, z25.h }146; CHECK-NEXT: ret147 call void @llvm.aarch64.sme.mop4a.wide.1x2.nxv8f16(i32 0, <vscale x 8 x half> %zn, <vscale x 8 x half> %zm1, <vscale x 8 x half> %zm2)148 ret void149}150 151define void @mop4s_za32_f16(<vscale x 8 x half> %zn, <vscale x 8 x half> %zm1, <vscale x 8 x half> %zm2) #0 {152; CHECK-LABEL: mop4s_za32_f16:153; CHECK: // %bb.0:154; CHECK-NEXT: mov z25.d, z2.d155; CHECK-NEXT: mov z24.d, z1.d156; CHECK-NEXT: fmop4s za0.s, z0.h, { z24.h, z25.h }157; CHECK-NEXT: ret158 call void @llvm.aarch64.sme.mop4s.wide.1x2.nxv8f16(i32 0, <vscale x 8 x half> %zn, <vscale x 8 x half> %zm1, <vscale x 8 x half> %zm2)159 ret void160}161 162define void @mop4a_za32_bf16(<vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm1, <vscale x 8 x bfloat> %zm2) #0 {163; CHECK-LABEL: mop4a_za32_bf16:164; CHECK: // %bb.0:165; CHECK-NEXT: mov z25.d, z2.d166; CHECK-NEXT: mov z24.d, z1.d167; CHECK-NEXT: bfmop4a za0.s, z0.h, { z24.h, z25.h }168; CHECK-NEXT: ret169 call void @llvm.aarch64.sme.mop4a.wide.1x2.nxv8bf16(i32 0, <vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm1, <vscale x 8 x bfloat> %zm2)170 ret void171}172 173define void @mop4s_za32_bf16(<vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm1, <vscale x 8 x bfloat> %zm2) #0 {174; CHECK-LABEL: mop4s_za32_bf16:175; CHECK: // %bb.0:176; CHECK-NEXT: mov z25.d, z2.d177; CHECK-NEXT: mov z24.d, z1.d178; CHECK-NEXT: bfmop4s za0.s, z0.h, { z24.h, z25.h }179; CHECK-NEXT: ret180 call void @llvm.aarch64.sme.mop4s.wide.1x2.nxv8bf16(i32 0, <vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm1, <vscale x 8 x bfloat> %zm2)181 ret void182}183 184define void @mop4a_za64_s16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm1, <vscale x 8 x i16> %zm2) #0 {185; CHECK-LABEL: mop4a_za64_s16:186; CHECK: // %bb.0:187; CHECK-NEXT: mov z25.d, z2.d188; CHECK-NEXT: mov z24.d, z1.d189; CHECK-NEXT: smop4a za0.d, z0.h, { z24.h, z25.h }190; CHECK-NEXT: ret191 call void @llvm.aarch64.sme.smop4a.za64.wide.1x2.nxv8i16(i32 0, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm1, <vscale x 8 x i16> %zm2)192 ret void193}194 195define void @mop4s_za64_s16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm1, <vscale x 8 x i16> %zm2) #0 {196; CHECK-LABEL: mop4s_za64_s16:197; CHECK: // %bb.0:198; CHECK-NEXT: mov z25.d, z2.d199; CHECK-NEXT: mov z24.d, z1.d200; CHECK-NEXT: smop4s za0.d, z0.h, { z24.h, z25.h }201; CHECK-NEXT: ret202 call void @llvm.aarch64.sme.smop4s.za64.wide.1x2.nxv8i16(i32 0, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm1, <vscale x 8 x i16> %zm2)203 ret void204}205 206define void @mop4a_za64_u16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm1, <vscale x 8 x i16> %zm2) #0 {207; CHECK-LABEL: mop4a_za64_u16:208; CHECK: // %bb.0:209; CHECK-NEXT: mov z25.d, z2.d210; CHECK-NEXT: mov z24.d, z1.d211; CHECK-NEXT: umop4a za0.d, z0.h, { z24.h, z25.h }212; CHECK-NEXT: ret213 call void @llvm.aarch64.sme.umop4a.za64.wide.1x2.nxv8i16(i32 0, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm1, <vscale x 8 x i16> %zm2)214 ret void215}216 217define void @mop4s_za64_u16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm1, <vscale x 8 x i16> %zm2) #0 {218; CHECK-LABEL: mop4s_za64_u16:219; CHECK: // %bb.0:220; CHECK-NEXT: mov z25.d, z2.d221; CHECK-NEXT: mov z24.d, z1.d222; CHECK-NEXT: umop4s za0.d, z0.h, { z24.h, z25.h }223; CHECK-NEXT: ret224 call void @llvm.aarch64.sme.umop4s.za64.wide.1x2.nxv8i16(i32 0, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm1, <vscale x 8 x i16> %zm2)225 ret void226}227 228define void @mop4a_za64_s16_u16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm1, <vscale x 8 x i16> %zm2) #0 {229; CHECK-LABEL: mop4a_za64_s16_u16:230; CHECK: // %bb.0:231; CHECK-NEXT: mov z25.d, z2.d232; CHECK-NEXT: mov z24.d, z1.d233; CHECK-NEXT: sumop4a za0.d, z0.h, { z24.h, z25.h }234; CHECK-NEXT: ret235 call void @llvm.aarch64.sme.sumop4a.za64.wide.1x2.nxv8i16(i32 0, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm1, <vscale x 8 x i16> %zm2)236 ret void237}238 239define void @mop4s_za64_s16_u16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm1, <vscale x 8 x i16> %zm2) #0 {240; CHECK-LABEL: mop4s_za64_s16_u16:241; CHECK: // %bb.0:242; CHECK-NEXT: mov z25.d, z2.d243; CHECK-NEXT: mov z24.d, z1.d244; CHECK-NEXT: sumop4s za0.d, z0.h, { z24.h, z25.h }245; CHECK-NEXT: ret246 call void @llvm.aarch64.sme.sumop4s.za64.wide.1x2.nxv8i16(i32 0, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm1, <vscale x 8 x i16> %zm2)247 ret void248}249 250define void @mop4a_za64_u16_s16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm1, <vscale x 8 x i16> %zm2) #0 {251; CHECK-LABEL: mop4a_za64_u16_s16:252; CHECK: // %bb.0:253; CHECK-NEXT: mov z25.d, z2.d254; CHECK-NEXT: mov z24.d, z1.d255; CHECK-NEXT: usmop4a za0.d, z0.h, { z24.h, z25.h }256; CHECK-NEXT: ret257 call void @llvm.aarch64.sme.usmop4a.za64.wide.1x2.nxv8i16(i32 0, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm1, <vscale x 8 x i16> %zm2)258 ret void259}260 261define void @mop4s_za64_u16_s16(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm1, <vscale x 8 x i16> %zm2) #0 {262; CHECK-LABEL: mop4s_za64_u16_s16:263; CHECK: // %bb.0:264; CHECK-NEXT: mov z25.d, z2.d265; CHECK-NEXT: mov z24.d, z1.d266; CHECK-NEXT: usmop4s za0.d, z0.h, { z24.h, z25.h }267; CHECK-NEXT: ret268 call void @llvm.aarch64.sme.usmop4s.za64.wide.1x2.nxv8i16(i32 0, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm1, <vscale x 8 x i16> %zm2)269 ret void270}271 272; Non-widening273define void @mop4a_za16_f16(<vscale x 8 x half> %zn, <vscale x 8 x half> %zm1, <vscale x 8 x half> %zm2) #0 {274; CHECK-LABEL: mop4a_za16_f16:275; CHECK: // %bb.0:276; CHECK-NEXT: mov z25.d, z2.d277; CHECK-NEXT: mov z24.d, z1.d278; CHECK-NEXT: fmop4a za0.h, z0.h, { z24.h, z25.h }279; CHECK-NEXT: ret280 call void @llvm.aarch64.sme.mop4a.1x2.nxv8f16(i32 0, <vscale x 8 x half> %zn, <vscale x 8 x half> %zm1, <vscale x 8 x half> %zm2)281 ret void282}283 284define void @mop4s_za16_f16(<vscale x 8 x half> %zn, <vscale x 8 x half> %zm1, <vscale x 8 x half> %zm2) #0 {285; CHECK-LABEL: mop4s_za16_f16:286; CHECK: // %bb.0:287; CHECK-NEXT: mov z25.d, z2.d288; CHECK-NEXT: mov z24.d, z1.d289; CHECK-NEXT: fmop4s za0.h, z0.h, { z24.h, z25.h }290; CHECK-NEXT: ret291 call void @llvm.aarch64.sme.mop4s.1x2.nxv8f16(i32 0, <vscale x 8 x half> %zn, <vscale x 8 x half> %zm1, <vscale x 8 x half> %zm2)292 ret void293}294 295define void @mop4a_za32_f32(<vscale x 4 x float> %zn, <vscale x 4 x float> %zm1, <vscale x 4 x float> %zm2) #0 {296; CHECK-LABEL: mop4a_za32_f32:297; CHECK: // %bb.0:298; CHECK-NEXT: mov z25.d, z2.d299; CHECK-NEXT: mov z24.d, z1.d300; CHECK-NEXT: fmop4a za0.s, z0.s, { z24.s, z25.s }301; CHECK-NEXT: ret302 call void @llvm.aarch64.sme.mop4a.1x2.nxv4f32(i32 0, <vscale x 4 x float> %zn, <vscale x 4 x float> %zm1, <vscale x 4 x float> %zm2)303 ret void304}305 306define void @mop4s_za32_f32(<vscale x 4 x float> %zn, <vscale x 4 x float> %zm1, <vscale x 4 x float> %zm2) #0 {307; CHECK-LABEL: mop4s_za32_f32:308; CHECK: // %bb.0:309; CHECK-NEXT: mov z25.d, z2.d310; CHECK-NEXT: mov z24.d, z1.d311; CHECK-NEXT: fmop4s za0.s, z0.s, { z24.s, z25.s }312; CHECK-NEXT: ret313 call void @llvm.aarch64.sme.mop4s.1x2.nxv4f32(i32 0, <vscale x 4 x float> %zn, <vscale x 4 x float> %zm1, <vscale x 4 x float> %zm2)314 ret void315}316 317define void @mop4a_za64_f64(<vscale x 2 x double> %zn, <vscale x 2 x double> %zm1, <vscale x 2 x double> %zm2) #0 {318; CHECK-LABEL: mop4a_za64_f64:319; CHECK: // %bb.0:320; CHECK-NEXT: mov z25.d, z2.d321; CHECK-NEXT: mov z24.d, z1.d322; CHECK-NEXT: fmop4a za0.d, z0.d, { z24.d, z25.d }323; CHECK-NEXT: ret324 call void @llvm.aarch64.sme.mop4a.1x2.nxv2f64(i32 0, <vscale x 2 x double> %zn, <vscale x 2 x double> %zm1, <vscale x 2 x double> %zm2)325 ret void326}327 328define void @mop4s_za64_f64(<vscale x 2 x double> %zn, <vscale x 2 x double> %zm1, <vscale x 2 x double> %zm2) #0 {329; CHECK-LABEL: mop4s_za64_f64:330; CHECK: // %bb.0:331; CHECK-NEXT: mov z25.d, z2.d332; CHECK-NEXT: mov z24.d, z1.d333; CHECK-NEXT: fmop4s za0.d, z0.d, { z24.d, z25.d }334; CHECK-NEXT: ret335 call void @llvm.aarch64.sme.mop4s.1x2.nxv2f64(i32 0, <vscale x 2 x double> %zn, <vscale x 2 x double> %zm1, <vscale x 2 x double> %zm2)336 ret void337}338 339define void @mop4a_za16_bf16(<vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm1, <vscale x 8 x bfloat> %zm2) #0 {340; CHECK-LABEL: mop4a_za16_bf16:341; CHECK: // %bb.0:342; CHECK-NEXT: mov z25.d, z2.d343; CHECK-NEXT: mov z24.d, z1.d344; CHECK-NEXT: bfmop4a za0.h, z0.h, { z24.h, z25.h }345; CHECK-NEXT: ret346 call void @llvm.aarch64.sme.mop4a.1x2.nxv8bf16(i32 0, <vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm1, <vscale x 8 x bfloat> %zm2)347 ret void348}349 350define void @mop4s_za16_bf16(<vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm1, <vscale x 8 x bfloat> %zm2) #0 {351; CHECK-LABEL: mop4s_za16_bf16:352; CHECK: // %bb.0:353; CHECK-NEXT: mov z25.d, z2.d354; CHECK-NEXT: mov z24.d, z1.d355; CHECK-NEXT: bfmop4s za0.h, z0.h, { z24.h, z25.h }356; CHECK-NEXT: ret357 call void @llvm.aarch64.sme.mop4s.1x2.nxv8bf16(i32 0, <vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm1, <vscale x 8 x bfloat> %zm2)358 ret void359}360 361; Tile limits362 363define void @mop4s_za32_s8_limit(<vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2) #0 {364; CHECK-LABEL: mop4s_za32_s8_limit:365; CHECK: // %bb.0:366; CHECK-NEXT: mov z25.d, z2.d367; CHECK-NEXT: mov z24.d, z1.d368; CHECK-NEXT: smop4s za3.s, z0.b, { z24.b, z25.b }369; CHECK-NEXT: ret370 call void @llvm.aarch64.sme.smop4s.wide.1x2.nxv16i8(i32 3, <vscale x 16 x i8> %zn, <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2)371 ret void372}373 374define void @mop4s_za32_s16_limit(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm1, <vscale x 8 x i16> %zm2) #0 {375; CHECK-LABEL: mop4s_za32_s16_limit:376; CHECK: // %bb.0:377; CHECK-NEXT: mov z25.d, z2.d378; CHECK-NEXT: mov z24.d, z1.d379; CHECK-NEXT: smop4s za3.s, z0.h, { z24.h, z25.h }380; CHECK-NEXT: ret381 call void @llvm.aarch64.sme.smop4s.wide.1x2.nxv8i16(i32 3, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm1, <vscale x 8 x i16> %zm2)382 ret void383}384 385define void @mop4s_za32_f16_limit(<vscale x 8 x half> %zn, <vscale x 8 x half> %zm1, <vscale x 8 x half> %zm2) #0 {386; CHECK-LABEL: mop4s_za32_f16_limit:387; CHECK: // %bb.0:388; CHECK-NEXT: mov z25.d, z2.d389; CHECK-NEXT: mov z24.d, z1.d390; CHECK-NEXT: fmop4s za3.s, z0.h, { z24.h, z25.h }391; CHECK-NEXT: ret392 call void @llvm.aarch64.sme.mop4s.wide.1x2.nxv8f16(i32 3, <vscale x 8 x half> %zn, <vscale x 8 x half> %zm1, <vscale x 8 x half> %zm2)393 ret void394}395 396define void @mop4s_za32_bf16_limit(<vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm1, <vscale x 8 x bfloat> %zm2) #0 {397; CHECK-LABEL: mop4s_za32_bf16_limit:398; CHECK: // %bb.0:399; CHECK-NEXT: mov z25.d, z2.d400; CHECK-NEXT: mov z24.d, z1.d401; CHECK-NEXT: bfmop4s za3.s, z0.h, { z24.h, z25.h }402; CHECK-NEXT: ret403 call void @llvm.aarch64.sme.mop4s.wide.1x2.nxv8bf16(i32 3, <vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm1, <vscale x 8 x bfloat> %zm2)404 ret void405}406 407define void @mop4s_za64_s16_limit(<vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm1, <vscale x 8 x i16> %zm2) #0 {408; CHECK-LABEL: mop4s_za64_s16_limit:409; CHECK: // %bb.0:410; CHECK-NEXT: mov z25.d, z2.d411; CHECK-NEXT: mov z24.d, z1.d412; CHECK-NEXT: smop4s za7.d, z0.h, { z24.h, z25.h }413; CHECK-NEXT: ret414 call void @llvm.aarch64.sme.smop4s.za64.wide.1x2.nxv8i16(i32 7, <vscale x 8 x i16> %zn, <vscale x 8 x i16> %zm1, <vscale x 8 x i16> %zm2)415 ret void416}417 418define void @mop4s_za64_f64_limit(<vscale x 2 x double> %zn, <vscale x 2 x double> %zm1, <vscale x 2 x double> %zm2) #0 {419; CHECK-LABEL: mop4s_za64_f64_limit:420; CHECK: // %bb.0:421; CHECK-NEXT: mov z25.d, z2.d422; CHECK-NEXT: mov z24.d, z1.d423; CHECK-NEXT: fmop4s za7.d, z0.d, { z24.d, z25.d }424; CHECK-NEXT: ret425 call void @llvm.aarch64.sme.mop4s.1x2.nxv2f64(i32 7, <vscale x 2 x double> %zn, <vscale x 2 x double> %zm1, <vscale x 2 x double> %zm2)426 ret void427}428 429define void @mop4s_za32_f32_limit(<vscale x 4 x float> %zn, <vscale x 4 x float> %zm1, <vscale x 4 x float> %zm2) #0 {430; CHECK-LABEL: mop4s_za32_f32_limit:431; CHECK: // %bb.0:432; CHECK-NEXT: mov z25.d, z2.d433; CHECK-NEXT: mov z24.d, z1.d434; CHECK-NEXT: fmop4s za3.s, z0.s, { z24.s, z25.s }435; CHECK-NEXT: ret436 call void @llvm.aarch64.sme.mop4s.1x2.nxv4f32(i32 3, <vscale x 4 x float> %zn, <vscale x 4 x float> %zm1, <vscale x 4 x float> %zm2)437 ret void438}439 440define void @mop4s_za16_f16_limit(<vscale x 8 x half> %zn, <vscale x 8 x half> %zm1, <vscale x 8 x half> %zm2) #0 {441; CHECK-LABEL: mop4s_za16_f16_limit:442; CHECK: // %bb.0:443; CHECK-NEXT: mov z25.d, z2.d444; CHECK-NEXT: mov z24.d, z1.d445; CHECK-NEXT: fmop4s za1.h, z0.h, { z24.h, z25.h }446; CHECK-NEXT: ret447 call void @llvm.aarch64.sme.mop4s.1x2.nxv8f16(i32 1, <vscale x 8 x half> %zn, <vscale x 8 x half> %zm1, <vscale x 8 x half> %zm2)448 ret void449}450 451define void @mop4s_za16_bf16_limit(<vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm1, <vscale x 8 x bfloat> %zm2) #0 {452; CHECK-LABEL: mop4s_za16_bf16_limit:453; CHECK: // %bb.0:454; CHECK-NEXT: mov z25.d, z2.d455; CHECK-NEXT: mov z24.d, z1.d456; CHECK-NEXT: bfmop4s za1.h, z0.h, { z24.h, z25.h }457; CHECK-NEXT: ret458 call void @llvm.aarch64.sme.mop4s.1x2.nxv8bf16(i32 1, <vscale x 8 x bfloat> %zn, <vscale x 8 x bfloat> %zm1, <vscale x 8 x bfloat> %zm2)459 ret void460}461 462attributes #0 = {nounwind "target-features" = "+sme-i16i64,+sme-f64f64,+sme-b16b16,+sme2p1,+bf16,+sme-f16f16,+sme-mop4" }463