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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py$2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme2 -force-streaming -verify-machineinstrs < %s | FileCheck %s3 4;5; SQCVTN6;7 8; x49define <vscale x 16 x i8 > @multi_vector_qcvtn_x4_s8_s32(<vscale x 4 x i32> %unused, <vscale x 4 x i32> %zn1, <vscale x 4 x i32> %zn2, <vscale x 4 x i32> %zn3, <vscale x 4 x i32> %zn4) {10; CHECK-LABEL: multi_vector_qcvtn_x4_s8_s32:11; CHECK: // %bb.0:12; CHECK-NEXT: mov z7.d, z4.d13; CHECK-NEXT: mov z6.d, z3.d14; CHECK-NEXT: mov z5.d, z2.d15; CHECK-NEXT: mov z4.d, z1.d16; CHECK-NEXT: sqcvtn z0.b, { z4.s - z7.s }17; CHECK-NEXT: ret18 %res = call <vscale x 16 x i8> @llvm.aarch64.sve.sqcvtn.x4.nxv4i32(<vscale x 4 x i32> %zn1, <vscale x 4 x i32> %zn2, <vscale x 4 x i32> %zn3, <vscale x 4 x i32> %zn4)19 ret <vscale x 16 x i8> %res20}21 22define <vscale x 8 x i16> @multi_vector_qcvtn_x4_s16_s64(<vscale x 2 x i64> %unused, <vscale x 2 x i64> %zn1, <vscale x 2 x i64> %zn2, <vscale x 2 x i64> %zn3, <vscale x 2 x i64> %zn4) {23; CHECK-LABEL: multi_vector_qcvtn_x4_s16_s64:24; CHECK: // %bb.0:25; CHECK-NEXT: mov z7.d, z4.d26; CHECK-NEXT: mov z6.d, z3.d27; CHECK-NEXT: mov z5.d, z2.d28; CHECK-NEXT: mov z4.d, z1.d29; CHECK-NEXT: sqcvtn z0.h, { z4.d - z7.d }30; CHECK-NEXT: ret31 %res = call <vscale x 8 x i16> @llvm.aarch64.sve.sqcvtn.x4.nxv2i64(<vscale x 2 x i64> %zn1, <vscale x 2 x i64> %zn2, <vscale x 2 x i64> %zn3, <vscale x 2 x i64> %zn4)32 ret <vscale x 8 x i16> %res33}34 35;36; UQCVTN37;38 39; x440define <vscale x 16 x i8> @multi_vector_qcvtn_x4_u8_u32(<vscale x 4 x i32> %unused, <vscale x 4 x i32> %zn1, <vscale x 4 x i32> %zn2, <vscale x 4 x i32> %zn3, <vscale x 4 x i32> %zn4) {41; CHECK-LABEL: multi_vector_qcvtn_x4_u8_u32:42; CHECK: // %bb.0:43; CHECK-NEXT: mov z7.d, z4.d44; CHECK-NEXT: mov z6.d, z3.d45; CHECK-NEXT: mov z5.d, z2.d46; CHECK-NEXT: mov z4.d, z1.d47; CHECK-NEXT: uqcvtn z0.b, { z4.s - z7.s }48; CHECK-NEXT: ret49 %res = call <vscale x 16 x i8> @llvm.aarch64.sve.uqcvtn.x4.nxv4i32(<vscale x 4 x i32> %zn1, <vscale x 4 x i32> %zn2, <vscale x 4 x i32> %zn3, <vscale x 4 x i32> %zn4)50 ret <vscale x 16 x i8> %res51}52 53define <vscale x 8 x i16> @multi_vector_qcvtn_x4_u16_u64(<vscale x 2 x i64> %unused, <vscale x 2 x i64> %zn1, <vscale x 2 x i64> %zn2, <vscale x 2 x i64> %zn3, <vscale x 2 x i64> %zn4) {54; CHECK-LABEL: multi_vector_qcvtn_x4_u16_u64:55; CHECK: // %bb.0:56; CHECK-NEXT: mov z7.d, z4.d57; CHECK-NEXT: mov z6.d, z3.d58; CHECK-NEXT: mov z5.d, z2.d59; CHECK-NEXT: mov z4.d, z1.d60; CHECK-NEXT: uqcvtn z0.h, { z4.d - z7.d }61; CHECK-NEXT: ret62 %res = call <vscale x 8 x i16> @llvm.aarch64.sve.uqcvtn.x4.nxv2i64(<vscale x 2 x i64> %zn1, <vscale x 2 x i64> %zn2, <vscale x 2 x i64> %zn3, <vscale x 2 x i64> %zn4)63 ret <vscale x 8 x i16> %res64}65 66;67; SQCVTUN68;69 70; x471define <vscale x 16 x i8> @multi_vector_qcvtn_x4_u8_s32(<vscale x 4 x i32> %unused, <vscale x 4 x i32> %zn1, <vscale x 4 x i32> %zn2, <vscale x 4 x i32> %zn3, <vscale x 4 x i32> %zn4) {72; CHECK-LABEL: multi_vector_qcvtn_x4_u8_s32:73; CHECK: // %bb.0:74; CHECK-NEXT: mov z7.d, z4.d75; CHECK-NEXT: mov z6.d, z3.d76; CHECK-NEXT: mov z5.d, z2.d77; CHECK-NEXT: mov z4.d, z1.d78; CHECK-NEXT: sqcvtun z0.b, { z4.s - z7.s }79; CHECK-NEXT: ret80 %res = call <vscale x 16 x i8> @llvm.aarch64.sve.sqcvtun.x4.nxv4i32(<vscale x 4 x i32> %zn1, <vscale x 4 x i32> %zn2, <vscale x 4 x i32> %zn3, <vscale x 4 x i32> %zn4)81 ret <vscale x 16 x i8> %res82}83 84define <vscale x 8 x i16> @multi_vector_qcvtn_x4_u16_s64(<vscale x 2 x i64> %unused, <vscale x 2 x i64> %zn1, <vscale x 2 x i64> %zn2, <vscale x 2 x i64> %zn3, <vscale x 2 x i64> %zn4) {85; CHECK-LABEL: multi_vector_qcvtn_x4_u16_s64:86; CHECK: // %bb.0:87; CHECK-NEXT: mov z7.d, z4.d88; CHECK-NEXT: mov z6.d, z3.d89; CHECK-NEXT: mov z5.d, z2.d90; CHECK-NEXT: mov z4.d, z1.d91; CHECK-NEXT: sqcvtun z0.h, { z4.d - z7.d }92; CHECK-NEXT: ret93 %res = call <vscale x 8 x i16> @llvm.aarch64.sve.sqcvtun.x4.nxv2i64(<vscale x 2 x i64> %zn1, <vscale x 2 x i64> %zn2, <vscale x 2 x i64> %zn3, <vscale x 2 x i64> %zn4)94 ret <vscale x 8 x i16> %res95}96 97declare <vscale x 16 x i8> @llvm.aarch64.sve.sqcvtn.x4.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>)98declare <vscale x 8 x i16> @llvm.aarch64.sve.sqcvtn.x4.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>)99declare <vscale x 16 x i8> @llvm.aarch64.sve.uqcvtn.x4.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>)100declare <vscale x 8 x i16> @llvm.aarch64.sve.uqcvtn.x4.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>)101declare <vscale x 16 x i8> @llvm.aarch64.sve.sqcvtun.x4.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>)102declare <vscale x 8 x i16> @llvm.aarch64.sve.sqcvtun.x4.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>)103