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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 42; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme2 -force-streaming -verify-machineinstrs < %s | FileCheck %s3 4; SRSHL (Single, x2)5 6define { <vscale x 16 x i8>, <vscale x 16 x i8> } @multi_vec_rounding_shl_single_x2_s8(<vscale x 16 x i8> %dummy, <vscale x 16 x i8> %zdn1, <vscale x 16 x i8> %zdn2, <vscale x 16 x i8> %zm) {7; CHECK-LABEL: multi_vec_rounding_shl_single_x2_s8:8; CHECK: // %bb.0:9; CHECK-NEXT: mov z5.d, z2.d10; CHECK-NEXT: mov z4.d, z1.d11; CHECK-NEXT: srshl { z4.b, z5.b }, { z4.b, z5.b }, z3.b12; CHECK-NEXT: mov z0.d, z4.d13; CHECK-NEXT: mov z1.d, z5.d14; CHECK-NEXT: ret15 %res = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.srshl.single.x2.nxv16i8(<vscale x 16 x i8> %zdn1, <vscale x 16 x i8> %zdn2, <vscale x 16 x i8> %zm)16 ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %res17}18 19define { <vscale x 8 x i16>, <vscale x 8 x i16> } @multi_vec_rounding_shl_single_x2_s16(<vscale x 8 x i16> %dummy, <vscale x 8 x i16> %zdn1, <vscale x 8 x i16> %zdn2, <vscale x 8 x i16> %zm) {20; CHECK-LABEL: multi_vec_rounding_shl_single_x2_s16:21; CHECK: // %bb.0:22; CHECK-NEXT: mov z5.d, z2.d23; CHECK-NEXT: mov z4.d, z1.d24; CHECK-NEXT: srshl { z4.h, z5.h }, { z4.h, z5.h }, z3.h25; CHECK-NEXT: mov z0.d, z4.d26; CHECK-NEXT: mov z1.d, z5.d27; CHECK-NEXT: ret28 %res = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.srshl.single.x2.nxv8i16(<vscale x 8 x i16> %zdn1, <vscale x 8 x i16> %zdn2, <vscale x 8 x i16> %zm)29 ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %res30}31 32define { <vscale x 4 x i32>, <vscale x 4 x i32> } @multi_vec_rounding_shl_single_x2_s32(<vscale x 4 x i32> %dummy, <vscale x 4 x i32> %zdn1, <vscale x 4 x i32> %zdn2, <vscale x 4 x i32> %zm) {33; CHECK-LABEL: multi_vec_rounding_shl_single_x2_s32:34; CHECK: // %bb.0:35; CHECK-NEXT: mov z5.d, z2.d36; CHECK-NEXT: mov z4.d, z1.d37; CHECK-NEXT: srshl { z4.s, z5.s }, { z4.s, z5.s }, z3.s38; CHECK-NEXT: mov z0.d, z4.d39; CHECK-NEXT: mov z1.d, z5.d40; CHECK-NEXT: ret41 %res = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.srshl.single.x2.nxv4i32(<vscale x 4 x i32> %zdn1, <vscale x 4 x i32> %zdn2, <vscale x 4 x i32> %zm)42 ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %res43}44 45define { <vscale x 2 x i64>, <vscale x 2 x i64> } @multi_vec_rounding_shl_single_x2_s64(<vscale x 2 x i64> %dummy, <vscale x 2 x i64> %zdn1, <vscale x 2 x i64> %zdn2, <vscale x 2 x i64> %zm) {46; CHECK-LABEL: multi_vec_rounding_shl_single_x2_s64:47; CHECK: // %bb.0:48; CHECK-NEXT: mov z5.d, z2.d49; CHECK-NEXT: mov z4.d, z1.d50; CHECK-NEXT: srshl { z4.d, z5.d }, { z4.d, z5.d }, z3.d51; CHECK-NEXT: mov z0.d, z4.d52; CHECK-NEXT: mov z1.d, z5.d53; CHECK-NEXT: ret54 %res = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.srshl.single.x2.nxv2i64(<vscale x 2 x i64> %zdn1, <vscale x 2 x i64> %zdn2, <vscale x 2 x i64> %zm)55 ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %res56}57 58; SRSHL (Single, x4)59 60define { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @multi_vec_rounding_shl_single_x4_s8(<vscale x 16 x i8> %dummy, <vscale x 16 x i8> %zdn1, <vscale x 16 x i8> %zdn2, <vscale x 16 x i8> %zdn3, <vscale x 16 x i8> %zdn4, <vscale x 16 x i8> %zm) {61; CHECK-LABEL: multi_vec_rounding_shl_single_x4_s8:62; CHECK: // %bb.0:63; CHECK-NEXT: mov z27.d, z4.d64; CHECK-NEXT: mov z26.d, z3.d65; CHECK-NEXT: mov z25.d, z2.d66; CHECK-NEXT: mov z24.d, z1.d67; CHECK-NEXT: srshl { z24.b - z27.b }, { z24.b - z27.b }, z5.b68; CHECK-NEXT: mov z0.d, z24.d69; CHECK-NEXT: mov z1.d, z25.d70; CHECK-NEXT: mov z2.d, z26.d71; CHECK-NEXT: mov z3.d, z27.d72; CHECK-NEXT: ret73 %res = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }74 @llvm.aarch64.sve.srshl.single.x4.nxv16i8(<vscale x 16 x i8> %zdn1, <vscale x 16 x i8> %zdn2, <vscale x 16 x i8> %zdn3, <vscale x 16 x i8> %zdn4, <vscale x 16 x i8> %zm)75 ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %res76}77 78define { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @multi_vec_rounding_shl_single_x4_s16(<vscale x 8 x i16> %dummy, <vscale x 8 x i16> %zdn1, <vscale x 8 x i16> %zdn2, <vscale x 8 x i16> %zdn3, <vscale x 8 x i16> %zdn4, <vscale x 8 x i16> %zm) {79; CHECK-LABEL: multi_vec_rounding_shl_single_x4_s16:80; CHECK: // %bb.0:81; CHECK-NEXT: mov z27.d, z4.d82; CHECK-NEXT: mov z26.d, z3.d83; CHECK-NEXT: mov z25.d, z2.d84; CHECK-NEXT: mov z24.d, z1.d85; CHECK-NEXT: srshl { z24.h - z27.h }, { z24.h - z27.h }, z5.h86; CHECK-NEXT: mov z0.d, z24.d87; CHECK-NEXT: mov z1.d, z25.d88; CHECK-NEXT: mov z2.d, z26.d89; CHECK-NEXT: mov z3.d, z27.d90; CHECK-NEXT: ret91 %res = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }92 @llvm.aarch64.sve.srshl.single.x4.nxv8i16(<vscale x 8 x i16> %zdn1, <vscale x 8 x i16> %zdn2, <vscale x 8 x i16> %zdn3, <vscale x 8 x i16> %zdn4, <vscale x 8 x i16> %zm)93 ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %res94}95 96define { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @multi_vec_rounding_shl_single_x4_s32(<vscale x 4 x i32> %dummy, <vscale x 4 x i32> %zdn1, <vscale x 4 x i32> %zdn2, <vscale x 4 x i32> %zdn3, <vscale x 4 x i32> %zdn4, <vscale x 4 x i32> %zm) {97; CHECK-LABEL: multi_vec_rounding_shl_single_x4_s32:98; CHECK: // %bb.0:99; CHECK-NEXT: mov z27.d, z4.d100; CHECK-NEXT: mov z26.d, z3.d101; CHECK-NEXT: mov z25.d, z2.d102; CHECK-NEXT: mov z24.d, z1.d103; CHECK-NEXT: srshl { z24.s - z27.s }, { z24.s - z27.s }, z5.s104; CHECK-NEXT: mov z0.d, z24.d105; CHECK-NEXT: mov z1.d, z25.d106; CHECK-NEXT: mov z2.d, z26.d107; CHECK-NEXT: mov z3.d, z27.d108; CHECK-NEXT: ret109 %res = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }110 @llvm.aarch64.sve.srshl.single.x4.nxv4i32(<vscale x 4 x i32> %zdn1, <vscale x 4 x i32> %zdn2, <vscale x 4 x i32> %zdn3, <vscale x 4 x i32> %zdn4, <vscale x 4 x i32> %zm)111 ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %res112}113 114define { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @multi_vec_rounding_shl_single_x4_s64(<vscale x 2 x i64> %dummy, <vscale x 2 x i64> %zdn1, <vscale x 2 x i64> %zdn2, <vscale x 2 x i64> %zdn3, <vscale x 2 x i64> %zdn4, <vscale x 2 x i64> %zm) {115; CHECK-LABEL: multi_vec_rounding_shl_single_x4_s64:116; CHECK: // %bb.0:117; CHECK-NEXT: mov z27.d, z4.d118; CHECK-NEXT: mov z26.d, z3.d119; CHECK-NEXT: mov z25.d, z2.d120; CHECK-NEXT: mov z24.d, z1.d121; CHECK-NEXT: srshl { z24.d - z27.d }, { z24.d - z27.d }, z5.d122; CHECK-NEXT: mov z0.d, z24.d123; CHECK-NEXT: mov z1.d, z25.d124; CHECK-NEXT: mov z2.d, z26.d125; CHECK-NEXT: mov z3.d, z27.d126; CHECK-NEXT: ret127 %res = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }128 @llvm.aarch64.sve.srshl.single.x4.nxv2i64(<vscale x 2 x i64> %zdn1, <vscale x 2 x i64> %zdn2, <vscale x 2 x i64> %zdn3, <vscale x 2 x i64> %zdn4, <vscale x 2 x i64> %zm)129 ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %res130}131 132; URSHL (Single, x2)133 134define { <vscale x 16 x i8>, <vscale x 16 x i8> } @multi_vec_rounding_shl_single_x2_u8(<vscale x 16 x i8> %dummy, <vscale x 16 x i8> %zdn1, <vscale x 16 x i8> %zdn2, <vscale x 16 x i8> %zm) {135; CHECK-LABEL: multi_vec_rounding_shl_single_x2_u8:136; CHECK: // %bb.0:137; CHECK-NEXT: mov z5.d, z2.d138; CHECK-NEXT: mov z4.d, z1.d139; CHECK-NEXT: urshl { z4.b, z5.b }, { z4.b, z5.b }, z3.b140; CHECK-NEXT: mov z0.d, z4.d141; CHECK-NEXT: mov z1.d, z5.d142; CHECK-NEXT: ret143 %res = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.urshl.single.x2.nxv16i8(<vscale x 16 x i8> %zdn1, <vscale x 16 x i8> %zdn2, <vscale x 16 x i8> %zm)144 ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %res145}146 147define { <vscale x 8 x i16>, <vscale x 8 x i16> } @multi_vec_rounding_shl_single_x2_u16(<vscale x 8 x i16> %dummy, <vscale x 8 x i16> %zdn1, <vscale x 8 x i16> %zdn2, <vscale x 8 x i16> %zm) {148; CHECK-LABEL: multi_vec_rounding_shl_single_x2_u16:149; CHECK: // %bb.0:150; CHECK-NEXT: mov z5.d, z2.d151; CHECK-NEXT: mov z4.d, z1.d152; CHECK-NEXT: urshl { z4.h, z5.h }, { z4.h, z5.h }, z3.h153; CHECK-NEXT: mov z0.d, z4.d154; CHECK-NEXT: mov z1.d, z5.d155; CHECK-NEXT: ret156 %res = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.urshl.single.x2.nxv8i16(<vscale x 8 x i16> %zdn1, <vscale x 8 x i16> %zdn2, <vscale x 8 x i16> %zm)157 ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %res158}159 160define { <vscale x 4 x i32>, <vscale x 4 x i32> } @multi_vec_rounding_shl_single_x2_u32(<vscale x 4 x i32> %dummy, <vscale x 4 x i32> %zdn1, <vscale x 4 x i32> %zdn2, <vscale x 4 x i32> %zm) {161; CHECK-LABEL: multi_vec_rounding_shl_single_x2_u32:162; CHECK: // %bb.0:163; CHECK-NEXT: mov z5.d, z2.d164; CHECK-NEXT: mov z4.d, z1.d165; CHECK-NEXT: urshl { z4.s, z5.s }, { z4.s, z5.s }, z3.s166; CHECK-NEXT: mov z0.d, z4.d167; CHECK-NEXT: mov z1.d, z5.d168; CHECK-NEXT: ret169 %res = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.urshl.single.x2.nxv4i32(<vscale x 4 x i32> %zdn1, <vscale x 4 x i32> %zdn2, <vscale x 4 x i32> %zm)170 ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %res171}172 173define { <vscale x 2 x i64>, <vscale x 2 x i64> } @multi_vec_rounding_shl_single_x2_u64(<vscale x 2 x i64> %dummy, <vscale x 2 x i64> %zdn1, <vscale x 2 x i64> %zdn2, <vscale x 2 x i64> %zm) {174; CHECK-LABEL: multi_vec_rounding_shl_single_x2_u64:175; CHECK: // %bb.0:176; CHECK-NEXT: mov z5.d, z2.d177; CHECK-NEXT: mov z4.d, z1.d178; CHECK-NEXT: urshl { z4.d, z5.d }, { z4.d, z5.d }, z3.d179; CHECK-NEXT: mov z0.d, z4.d180; CHECK-NEXT: mov z1.d, z5.d181; CHECK-NEXT: ret182 %res = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.urshl.single.x2.nxv2i64(<vscale x 2 x i64> %zdn1, <vscale x 2 x i64> %zdn2, <vscale x 2 x i64> %zm)183 ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %res184}185 186; URSHL (Single, x4)187 188define { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @multi_vec_rounding_shl_single_x4_u8(<vscale x 16 x i8> %dummy, <vscale x 16 x i8> %zdn1, <vscale x 16 x i8> %zdn2, <vscale x 16 x i8> %zdn3, <vscale x 16 x i8> %zdn4, <vscale x 16 x i8> %zm) {189; CHECK-LABEL: multi_vec_rounding_shl_single_x4_u8:190; CHECK: // %bb.0:191; CHECK-NEXT: mov z27.d, z4.d192; CHECK-NEXT: mov z26.d, z3.d193; CHECK-NEXT: mov z25.d, z2.d194; CHECK-NEXT: mov z24.d, z1.d195; CHECK-NEXT: urshl { z24.b - z27.b }, { z24.b - z27.b }, z5.b196; CHECK-NEXT: mov z0.d, z24.d197; CHECK-NEXT: mov z1.d, z25.d198; CHECK-NEXT: mov z2.d, z26.d199; CHECK-NEXT: mov z3.d, z27.d200; CHECK-NEXT: ret201 %res = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }202 @llvm.aarch64.sve.urshl.single.x4.nxv16i8(<vscale x 16 x i8> %zdn1, <vscale x 16 x i8> %zdn2, <vscale x 16 x i8> %zdn3, <vscale x 16 x i8> %zdn4, <vscale x 16 x i8> %zm)203 ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %res204}205 206define { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @multi_vec_rounding_shl_single_x4_u16(<vscale x 8 x i16> %dummy, <vscale x 8 x i16> %zdn1, <vscale x 8 x i16> %zdn2, <vscale x 8 x i16> %zdn3, <vscale x 8 x i16> %zdn4, <vscale x 8 x i16> %zm) {207; CHECK-LABEL: multi_vec_rounding_shl_single_x4_u16:208; CHECK: // %bb.0:209; CHECK-NEXT: mov z27.d, z4.d210; CHECK-NEXT: mov z26.d, z3.d211; CHECK-NEXT: mov z25.d, z2.d212; CHECK-NEXT: mov z24.d, z1.d213; CHECK-NEXT: urshl { z24.h - z27.h }, { z24.h - z27.h }, z5.h214; CHECK-NEXT: mov z0.d, z24.d215; CHECK-NEXT: mov z1.d, z25.d216; CHECK-NEXT: mov z2.d, z26.d217; CHECK-NEXT: mov z3.d, z27.d218; CHECK-NEXT: ret219 %res = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }220 @llvm.aarch64.sve.urshl.single.x4.nxv8i16(<vscale x 8 x i16> %zdn1, <vscale x 8 x i16> %zdn2, <vscale x 8 x i16> %zdn3, <vscale x 8 x i16> %zdn4, <vscale x 8 x i16> %zm)221 ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %res222}223 224define { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @multi_vec_rounding_shl_single_x4_u32(<vscale x 4 x i32> %dummy, <vscale x 4 x i32> %zdn1, <vscale x 4 x i32> %zdn2, <vscale x 4 x i32> %zdn3, <vscale x 4 x i32> %zdn4, <vscale x 4 x i32> %zm) {225; CHECK-LABEL: multi_vec_rounding_shl_single_x4_u32:226; CHECK: // %bb.0:227; CHECK-NEXT: mov z27.d, z4.d228; CHECK-NEXT: mov z26.d, z3.d229; CHECK-NEXT: mov z25.d, z2.d230; CHECK-NEXT: mov z24.d, z1.d231; CHECK-NEXT: urshl { z24.s - z27.s }, { z24.s - z27.s }, z5.s232; CHECK-NEXT: mov z0.d, z24.d233; CHECK-NEXT: mov z1.d, z25.d234; CHECK-NEXT: mov z2.d, z26.d235; CHECK-NEXT: mov z3.d, z27.d236; CHECK-NEXT: ret237 %res = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }238 @llvm.aarch64.sve.urshl.single.x4.nxv4i32(<vscale x 4 x i32> %zdn1, <vscale x 4 x i32> %zdn2, <vscale x 4 x i32> %zdn3, <vscale x 4 x i32> %zdn4, <vscale x 4 x i32> %zm)239 ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %res240}241 242define { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @multi_vec_rounding_shl_single_x4_u64(<vscale x 2 x i64> %dummy, <vscale x 2 x i64> %zdn1, <vscale x 2 x i64> %zdn2, <vscale x 2 x i64> %zdn3, <vscale x 2 x i64> %zdn4, <vscale x 2 x i64> %zm) {243; CHECK-LABEL: multi_vec_rounding_shl_single_x4_u64:244; CHECK: // %bb.0:245; CHECK-NEXT: mov z27.d, z4.d246; CHECK-NEXT: mov z26.d, z3.d247; CHECK-NEXT: mov z25.d, z2.d248; CHECK-NEXT: mov z24.d, z1.d249; CHECK-NEXT: urshl { z24.d - z27.d }, { z24.d - z27.d }, z5.d250; CHECK-NEXT: mov z0.d, z24.d251; CHECK-NEXT: mov z1.d, z25.d252; CHECK-NEXT: mov z2.d, z26.d253; CHECK-NEXT: mov z3.d, z27.d254; CHECK-NEXT: ret255 %res = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }256 @llvm.aarch64.sve.urshl.single.x4.nxv2i64(<vscale x 2 x i64> %zdn1, <vscale x 2 x i64> %zdn2, <vscale x 2 x i64> %zdn3, <vscale x 2 x i64> %zdn4, <vscale x 2 x i64> %zm)257 ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %res258}259 260; SRSHL (Multi, x2)261 262define { <vscale x 16 x i8>, <vscale x 16 x i8> } @multi_vec_rounding_shl_x2_s8(<vscale x 16 x i8> %dummy, <vscale x 16 x i8> %zdn1, <vscale x 16 x i8> %zdn2, <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2) {263; CHECK-LABEL: multi_vec_rounding_shl_x2_s8:264; CHECK: // %bb.0:265; CHECK-NEXT: mov z7.d, z4.d266; CHECK-NEXT: mov z5.d, z2.d267; CHECK-NEXT: mov z6.d, z3.d268; CHECK-NEXT: mov z4.d, z1.d269; CHECK-NEXT: srshl { z4.b, z5.b }, { z4.b, z5.b }, { z6.b, z7.b }270; CHECK-NEXT: mov z0.d, z4.d271; CHECK-NEXT: mov z1.d, z5.d272; CHECK-NEXT: ret273 %res = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.srshl.x2.nxv16i8(<vscale x 16 x i8> %zdn1, <vscale x 16 x i8> %zdn2, <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2)274 ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %res275}276 277define { <vscale x 8 x i16>, <vscale x 8 x i16> } @multi_vec_rounding_shl_x2_s16(<vscale x 8 x i16> %dummy, <vscale x 8 x i16> %zdn1, <vscale x 8 x i16> %zdn2, <vscale x 8 x i16> %zm1, <vscale x 8 x i16> %zm2) {278; CHECK-LABEL: multi_vec_rounding_shl_x2_s16:279; CHECK: // %bb.0:280; CHECK-NEXT: mov z7.d, z4.d281; CHECK-NEXT: mov z5.d, z2.d282; CHECK-NEXT: mov z6.d, z3.d283; CHECK-NEXT: mov z4.d, z1.d284; CHECK-NEXT: srshl { z4.h, z5.h }, { z4.h, z5.h }, { z6.h, z7.h }285; CHECK-NEXT: mov z0.d, z4.d286; CHECK-NEXT: mov z1.d, z5.d287; CHECK-NEXT: ret288 %res = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.srshl.x2.nxv8i16(<vscale x 8 x i16> %zdn1, <vscale x 8 x i16> %zdn2, <vscale x 8 x i16> %zm1, <vscale x 8 x i16> %zm2)289 ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %res290}291 292define { <vscale x 4 x i32>, <vscale x 4 x i32> } @multi_vec_rounding_shl_x2_s32(<vscale x 4 x i32> %dummy, <vscale x 4 x i32> %zdn1, <vscale x 4 x i32> %zdn2, <vscale x 4 x i32> %zm1, <vscale x 4 x i32> %zm2) {293; CHECK-LABEL: multi_vec_rounding_shl_x2_s32:294; CHECK: // %bb.0:295; CHECK-NEXT: mov z7.d, z4.d296; CHECK-NEXT: mov z5.d, z2.d297; CHECK-NEXT: mov z6.d, z3.d298; CHECK-NEXT: mov z4.d, z1.d299; CHECK-NEXT: srshl { z4.s, z5.s }, { z4.s, z5.s }, { z6.s, z7.s }300; CHECK-NEXT: mov z0.d, z4.d301; CHECK-NEXT: mov z1.d, z5.d302; CHECK-NEXT: ret303 %res = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.srshl.x2.nxv4i32(<vscale x 4 x i32> %zdn1, <vscale x 4 x i32> %zdn2, <vscale x 4 x i32> %zm1, <vscale x 4 x i32> %zm2)304 ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %res305}306 307define { <vscale x 2 x i64>, <vscale x 2 x i64> } @multi_vec_rounding_shl_x2_s64(<vscale x 2 x i64> %dummy, <vscale x 2 x i64> %zdn1, <vscale x 2 x i64> %zdn2, <vscale x 2 x i64> %zm1, <vscale x 2 x i64> %zm2) {308; CHECK-LABEL: multi_vec_rounding_shl_x2_s64:309; CHECK: // %bb.0:310; CHECK-NEXT: mov z7.d, z4.d311; CHECK-NEXT: mov z5.d, z2.d312; CHECK-NEXT: mov z6.d, z3.d313; CHECK-NEXT: mov z4.d, z1.d314; CHECK-NEXT: srshl { z4.d, z5.d }, { z4.d, z5.d }, { z6.d, z7.d }315; CHECK-NEXT: mov z0.d, z4.d316; CHECK-NEXT: mov z1.d, z5.d317; CHECK-NEXT: ret318 %res = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.srshl.x2.nxv2i64(<vscale x 2 x i64> %zdn1, <vscale x 2 x i64> %zdn2, <vscale x 2 x i64> %zm1, <vscale x 2 x i64> %zm2)319 ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %res320}321 322; SRSHL (Multi, x4)323 324define { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @multi_vec_rounding_shl_x4_s8(<vscale x 16 x i8> %dummy, <vscale x 16 x i8> %zdn1, <vscale x 16 x i8> %zdn2, <vscale x 16 x i8> %zdn3, <vscale x 16 x i8> %zdn4, <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2, <vscale x 16 x i8> %zm3, <vscale x 16 x i8> %zm4) {325; CHECK-LABEL: multi_vec_rounding_shl_x4_s8:326; CHECK: // %bb.0:327; CHECK-NEXT: mov z30.d, z7.d328; CHECK-NEXT: mov z27.d, z4.d329; CHECK-NEXT: mov z29.d, z6.d330; CHECK-NEXT: mov z26.d, z3.d331; CHECK-NEXT: mov z28.d, z5.d332; CHECK-NEXT: mov z25.d, z2.d333; CHECK-NEXT: ldr z31, [x0]334; CHECK-NEXT: mov z24.d, z1.d335; CHECK-NEXT: srshl { z24.b - z27.b }, { z24.b - z27.b }, { z28.b - z31.b }336; CHECK-NEXT: mov z0.d, z24.d337; CHECK-NEXT: mov z1.d, z25.d338; CHECK-NEXT: mov z2.d, z26.d339; CHECK-NEXT: mov z3.d, z27.d340; CHECK-NEXT: ret341 %res = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }342 @llvm.aarch64.sve.srshl.x4.nxv16i8(<vscale x 16 x i8> %zdn1, <vscale x 16 x i8> %zdn2, <vscale x 16 x i8> %zdn3, <vscale x 16 x i8> %zdn4,343 <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2, <vscale x 16 x i8> %zm3, <vscale x 16 x i8> %zm4)344 ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %res345}346 347define { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @multi_vec_rounding_shl_x4_s16(<vscale x 8 x i16> %dummy, <vscale x 8 x i16> %zdn1, <vscale x 8 x i16> %zdn2, <vscale x 8 x i16> %zdn3, <vscale x 8 x i16> %zdn4, <vscale x 8 x i16> %zm1, <vscale x 8 x i16> %zm2, <vscale x 8 x i16> %zm3, <vscale x 8 x i16> %zm4) {348; CHECK-LABEL: multi_vec_rounding_shl_x4_s16:349; CHECK: // %bb.0:350; CHECK-NEXT: mov z30.d, z7.d351; CHECK-NEXT: mov z27.d, z4.d352; CHECK-NEXT: mov z29.d, z6.d353; CHECK-NEXT: mov z26.d, z3.d354; CHECK-NEXT: mov z28.d, z5.d355; CHECK-NEXT: mov z25.d, z2.d356; CHECK-NEXT: ldr z31, [x0]357; CHECK-NEXT: mov z24.d, z1.d358; CHECK-NEXT: srshl { z24.h - z27.h }, { z24.h - z27.h }, { z28.h - z31.h }359; CHECK-NEXT: mov z0.d, z24.d360; CHECK-NEXT: mov z1.d, z25.d361; CHECK-NEXT: mov z2.d, z26.d362; CHECK-NEXT: mov z3.d, z27.d363; CHECK-NEXT: ret364 %res = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }365 @llvm.aarch64.sve.srshl.x4.nxv8i16(<vscale x 8 x i16> %zdn1, <vscale x 8 x i16> %zdn2, <vscale x 8 x i16> %zdn3, <vscale x 8 x i16> %zdn4,366 <vscale x 8 x i16> %zm1, <vscale x 8 x i16> %zm2, <vscale x 8 x i16> %zm3, <vscale x 8 x i16> %zm4)367 ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %res368}369 370define { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @multi_vec_rounding_shl_x4_s32(<vscale x 4 x i32> %dummy, <vscale x 4 x i32> %zdn1, <vscale x 4 x i32> %zdn2, <vscale x 4 x i32> %zdn3, <vscale x 4 x i32> %zdn4, <vscale x 4 x i32> %zm1, <vscale x 4 x i32> %zm2, <vscale x 4 x i32> %zm3, <vscale x 4 x i32> %zm4) {371; CHECK-LABEL: multi_vec_rounding_shl_x4_s32:372; CHECK: // %bb.0:373; CHECK-NEXT: mov z30.d, z7.d374; CHECK-NEXT: mov z27.d, z4.d375; CHECK-NEXT: mov z29.d, z6.d376; CHECK-NEXT: mov z26.d, z3.d377; CHECK-NEXT: mov z28.d, z5.d378; CHECK-NEXT: mov z25.d, z2.d379; CHECK-NEXT: ldr z31, [x0]380; CHECK-NEXT: mov z24.d, z1.d381; CHECK-NEXT: srshl { z24.s - z27.s }, { z24.s - z27.s }, { z28.s - z31.s }382; CHECK-NEXT: mov z0.d, z24.d383; CHECK-NEXT: mov z1.d, z25.d384; CHECK-NEXT: mov z2.d, z26.d385; CHECK-NEXT: mov z3.d, z27.d386; CHECK-NEXT: ret387 %res = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }388 @llvm.aarch64.sve.srshl.x4.nxv4i32(<vscale x 4 x i32> %zdn1, <vscale x 4 x i32> %zdn2, <vscale x 4 x i32> %zdn3, <vscale x 4 x i32> %zdn4,389 <vscale x 4 x i32> %zm1, <vscale x 4 x i32> %zm2, <vscale x 4 x i32> %zm3, <vscale x 4 x i32> %zm4)390 ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %res391}392 393define { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @multi_vec_rounding_shl_x4_s64(<vscale x 2 x i64> %dummy, <vscale x 2 x i64> %zdn1, <vscale x 2 x i64> %zdn2, <vscale x 2 x i64> %zdn3, <vscale x 2 x i64> %zdn4, <vscale x 2 x i64> %zm1, <vscale x 2 x i64> %zm2, <vscale x 2 x i64> %zm3, <vscale x 2 x i64> %zm4) {394; CHECK-LABEL: multi_vec_rounding_shl_x4_s64:395; CHECK: // %bb.0:396; CHECK-NEXT: mov z30.d, z7.d397; CHECK-NEXT: mov z27.d, z4.d398; CHECK-NEXT: mov z29.d, z6.d399; CHECK-NEXT: mov z26.d, z3.d400; CHECK-NEXT: mov z28.d, z5.d401; CHECK-NEXT: mov z25.d, z2.d402; CHECK-NEXT: ldr z31, [x0]403; CHECK-NEXT: mov z24.d, z1.d404; CHECK-NEXT: srshl { z24.d - z27.d }, { z24.d - z27.d }, { z28.d - z31.d }405; CHECK-NEXT: mov z0.d, z24.d406; CHECK-NEXT: mov z1.d, z25.d407; CHECK-NEXT: mov z2.d, z26.d408; CHECK-NEXT: mov z3.d, z27.d409; CHECK-NEXT: ret410 %res = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }411 @llvm.aarch64.sve.srshl.x4.nxv2i64(<vscale x 2 x i64> %zdn1, <vscale x 2 x i64> %zdn2, <vscale x 2 x i64> %zdn3, <vscale x 2 x i64> %zdn4,412 <vscale x 2 x i64> %zm1, <vscale x 2 x i64> %zm2, <vscale x 2 x i64> %zm3, <vscale x 2 x i64> %zm4)413 ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %res414}415 416; URSHL (Multi, x2)417 418define { <vscale x 16 x i8>, <vscale x 16 x i8> } @multi_vec_rounding_uhl_x2_u8(<vscale x 16 x i8> %dummy, <vscale x 16 x i8> %zdn1, <vscale x 16 x i8> %zdn2, <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2) {419; CHECK-LABEL: multi_vec_rounding_uhl_x2_u8:420; CHECK: // %bb.0:421; CHECK-NEXT: mov z7.d, z4.d422; CHECK-NEXT: mov z5.d, z2.d423; CHECK-NEXT: mov z6.d, z3.d424; CHECK-NEXT: mov z4.d, z1.d425; CHECK-NEXT: urshl { z4.b, z5.b }, { z4.b, z5.b }, { z6.b, z7.b }426; CHECK-NEXT: mov z0.d, z4.d427; CHECK-NEXT: mov z1.d, z5.d428; CHECK-NEXT: ret429 %res = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.urshl.x2.nxv16i8(<vscale x 16 x i8> %zdn1, <vscale x 16 x i8> %zdn2, <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2)430 ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %res431}432 433define { <vscale x 8 x i16>, <vscale x 8 x i16> } @multi_vec_rounding_uhl_x2_u16(<vscale x 8 x i16> %dummy, <vscale x 8 x i16> %zdn1, <vscale x 8 x i16> %zdn2, <vscale x 8 x i16> %zm1, <vscale x 8 x i16> %zm2) {434; CHECK-LABEL: multi_vec_rounding_uhl_x2_u16:435; CHECK: // %bb.0:436; CHECK-NEXT: mov z7.d, z4.d437; CHECK-NEXT: mov z5.d, z2.d438; CHECK-NEXT: mov z6.d, z3.d439; CHECK-NEXT: mov z4.d, z1.d440; CHECK-NEXT: urshl { z4.h, z5.h }, { z4.h, z5.h }, { z6.h, z7.h }441; CHECK-NEXT: mov z0.d, z4.d442; CHECK-NEXT: mov z1.d, z5.d443; CHECK-NEXT: ret444 %res = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.urshl.x2.nxv8i16(<vscale x 8 x i16> %zdn1, <vscale x 8 x i16> %zdn2, <vscale x 8 x i16> %zm1, <vscale x 8 x i16> %zm2)445 ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %res446}447 448define { <vscale x 4 x i32>, <vscale x 4 x i32> } @multi_vec_rounding_uhl_x2_u32(<vscale x 4 x i32> %dummy, <vscale x 4 x i32> %zdn1, <vscale x 4 x i32> %zdn2, <vscale x 4 x i32> %zm1, <vscale x 4 x i32> %zm2) {449; CHECK-LABEL: multi_vec_rounding_uhl_x2_u32:450; CHECK: // %bb.0:451; CHECK-NEXT: mov z7.d, z4.d452; CHECK-NEXT: mov z5.d, z2.d453; CHECK-NEXT: mov z6.d, z3.d454; CHECK-NEXT: mov z4.d, z1.d455; CHECK-NEXT: urshl { z4.s, z5.s }, { z4.s, z5.s }, { z6.s, z7.s }456; CHECK-NEXT: mov z0.d, z4.d457; CHECK-NEXT: mov z1.d, z5.d458; CHECK-NEXT: ret459 %res = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.urshl.x2.nxv4i32(<vscale x 4 x i32> %zdn1, <vscale x 4 x i32> %zdn2, <vscale x 4 x i32> %zm1, <vscale x 4 x i32> %zm2)460 ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %res461}462 463define { <vscale x 2 x i64>, <vscale x 2 x i64> } @multi_vec_rounding_uhl_x2_u64(<vscale x 2 x i64> %dummy, <vscale x 2 x i64> %zdn1, <vscale x 2 x i64> %zdn2, <vscale x 2 x i64> %zm1, <vscale x 2 x i64> %zm2) {464; CHECK-LABEL: multi_vec_rounding_uhl_x2_u64:465; CHECK: // %bb.0:466; CHECK-NEXT: mov z7.d, z4.d467; CHECK-NEXT: mov z5.d, z2.d468; CHECK-NEXT: mov z6.d, z3.d469; CHECK-NEXT: mov z4.d, z1.d470; CHECK-NEXT: urshl { z4.d, z5.d }, { z4.d, z5.d }, { z6.d, z7.d }471; CHECK-NEXT: mov z0.d, z4.d472; CHECK-NEXT: mov z1.d, z5.d473; CHECK-NEXT: ret474 %res = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.urshl.x2.nxv2i64(<vscale x 2 x i64> %zdn1, <vscale x 2 x i64> %zdn2, <vscale x 2 x i64> %zm1, <vscale x 2 x i64> %zm2)475 ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %res476}477 478; URSHL (Multi, x4)479 480define { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @multi_vec_rounding_shl_x4_u8(<vscale x 16 x i8> %dummy, <vscale x 16 x i8> %zdn1, <vscale x 16 x i8> %zdn2, <vscale x 16 x i8> %zdn3, <vscale x 16 x i8> %zdn4, <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2, <vscale x 16 x i8> %zm3, <vscale x 16 x i8> %zm4) {481; CHECK-LABEL: multi_vec_rounding_shl_x4_u8:482; CHECK: // %bb.0:483; CHECK-NEXT: mov z30.d, z7.d484; CHECK-NEXT: mov z27.d, z4.d485; CHECK-NEXT: mov z29.d, z6.d486; CHECK-NEXT: mov z26.d, z3.d487; CHECK-NEXT: mov z28.d, z5.d488; CHECK-NEXT: mov z25.d, z2.d489; CHECK-NEXT: ldr z31, [x0]490; CHECK-NEXT: mov z24.d, z1.d491; CHECK-NEXT: urshl { z24.b - z27.b }, { z24.b - z27.b }, { z28.b - z31.b }492; CHECK-NEXT: mov z0.d, z24.d493; CHECK-NEXT: mov z1.d, z25.d494; CHECK-NEXT: mov z2.d, z26.d495; CHECK-NEXT: mov z3.d, z27.d496; CHECK-NEXT: ret497 %res = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }498 @llvm.aarch64.sve.urshl.x4.nxv16i8(<vscale x 16 x i8> %zdn1, <vscale x 16 x i8> %zdn2, <vscale x 16 x i8> %zdn3, <vscale x 16 x i8> %zdn4,499 <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2, <vscale x 16 x i8> %zm3, <vscale x 16 x i8> %zm4)500 ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %res501}502 503define { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @multi_vec_rounding_shl_x4_u16(<vscale x 8 x i16> %dummy, <vscale x 8 x i16> %zdn1, <vscale x 8 x i16> %zdn2, <vscale x 8 x i16> %zdn3, <vscale x 8 x i16> %zdn4, <vscale x 8 x i16> %zm1, <vscale x 8 x i16> %zm2, <vscale x 8 x i16> %zm3, <vscale x 8 x i16> %zm4) {504; CHECK-LABEL: multi_vec_rounding_shl_x4_u16:505; CHECK: // %bb.0:506; CHECK-NEXT: mov z30.d, z7.d507; CHECK-NEXT: mov z27.d, z4.d508; CHECK-NEXT: mov z29.d, z6.d509; CHECK-NEXT: mov z26.d, z3.d510; CHECK-NEXT: mov z28.d, z5.d511; CHECK-NEXT: mov z25.d, z2.d512; CHECK-NEXT: ldr z31, [x0]513; CHECK-NEXT: mov z24.d, z1.d514; CHECK-NEXT: urshl { z24.h - z27.h }, { z24.h - z27.h }, { z28.h - z31.h }515; CHECK-NEXT: mov z0.d, z24.d516; CHECK-NEXT: mov z1.d, z25.d517; CHECK-NEXT: mov z2.d, z26.d518; CHECK-NEXT: mov z3.d, z27.d519; CHECK-NEXT: ret520 %res = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }521 @llvm.aarch64.sve.urshl.x4.nxv8i16(<vscale x 8 x i16> %zdn1, <vscale x 8 x i16> %zdn2, <vscale x 8 x i16> %zdn3, <vscale x 8 x i16> %zdn4,522 <vscale x 8 x i16> %zm1, <vscale x 8 x i16> %zm2, <vscale x 8 x i16> %zm3, <vscale x 8 x i16> %zm4)523 ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %res524}525 526define { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @multi_vec_rounding_shl_x4_u32(<vscale x 4 x i32> %dummy, <vscale x 4 x i32> %zdn1, <vscale x 4 x i32> %zdn2, <vscale x 4 x i32> %zdn3, <vscale x 4 x i32> %zdn4, <vscale x 4 x i32> %zm1, <vscale x 4 x i32> %zm2, <vscale x 4 x i32> %zm3, <vscale x 4 x i32> %zm4) {527; CHECK-LABEL: multi_vec_rounding_shl_x4_u32:528; CHECK: // %bb.0:529; CHECK-NEXT: mov z30.d, z7.d530; CHECK-NEXT: mov z27.d, z4.d531; CHECK-NEXT: mov z29.d, z6.d532; CHECK-NEXT: mov z26.d, z3.d533; CHECK-NEXT: mov z28.d, z5.d534; CHECK-NEXT: mov z25.d, z2.d535; CHECK-NEXT: ldr z31, [x0]536; CHECK-NEXT: mov z24.d, z1.d537; CHECK-NEXT: urshl { z24.s - z27.s }, { z24.s - z27.s }, { z28.s - z31.s }538; CHECK-NEXT: mov z0.d, z24.d539; CHECK-NEXT: mov z1.d, z25.d540; CHECK-NEXT: mov z2.d, z26.d541; CHECK-NEXT: mov z3.d, z27.d542; CHECK-NEXT: ret543 %res = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }544 @llvm.aarch64.sve.urshl.x4.nxv4i32(<vscale x 4 x i32> %zdn1, <vscale x 4 x i32> %zdn2, <vscale x 4 x i32> %zdn3, <vscale x 4 x i32> %zdn4,545 <vscale x 4 x i32> %zm1, <vscale x 4 x i32> %zm2, <vscale x 4 x i32> %zm3, <vscale x 4 x i32> %zm4)546 ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %res547}548 549define { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @multi_vec_rounding_shl_x4_u64(<vscale x 2 x i64> %dummy, <vscale x 2 x i64> %zdn1, <vscale x 2 x i64> %zdn2, <vscale x 2 x i64> %zdn3, <vscale x 2 x i64> %zdn4, <vscale x 2 x i64> %zm1, <vscale x 2 x i64> %zm2, <vscale x 2 x i64> %zm3, <vscale x 2 x i64> %zm4) {550; CHECK-LABEL: multi_vec_rounding_shl_x4_u64:551; CHECK: // %bb.0:552; CHECK-NEXT: mov z30.d, z7.d553; CHECK-NEXT: mov z27.d, z4.d554; CHECK-NEXT: mov z29.d, z6.d555; CHECK-NEXT: mov z26.d, z3.d556; CHECK-NEXT: mov z28.d, z5.d557; CHECK-NEXT: mov z25.d, z2.d558; CHECK-NEXT: ldr z31, [x0]559; CHECK-NEXT: mov z24.d, z1.d560; CHECK-NEXT: urshl { z24.d - z27.d }, { z24.d - z27.d }, { z28.d - z31.d }561; CHECK-NEXT: mov z0.d, z24.d562; CHECK-NEXT: mov z1.d, z25.d563; CHECK-NEXT: mov z2.d, z26.d564; CHECK-NEXT: mov z3.d, z27.d565; CHECK-NEXT: ret566 %res = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }567 @llvm.aarch64.sve.urshl.x4.nxv2i64(<vscale x 2 x i64> %zdn1, <vscale x 2 x i64> %zdn2, <vscale x 2 x i64> %zdn3, <vscale x 2 x i64> %zdn4,568 <vscale x 2 x i64> %zm1, <vscale x 2 x i64> %zm2, <vscale x 2 x i64> %zm3, <vscale x 2 x i64> %zm4)569 ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %res570}571 572declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.srshl.single.x2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>)573declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.srshl.single.x2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>)574declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.srshl.single.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>)575declare { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.srshl.single.x2.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>)576 577declare { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.srshl.single.x4.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>)578declare { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.srshl.single.x4.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>)579declare { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.srshl.single.x4.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>)580declare { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.srshl.single.x4.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>)581 582declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.urshl.single.x2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>)583declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.urshl.single.x2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>)584declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.urshl.single.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>)585declare { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.urshl.single.x2.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>)586 587declare { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.urshl.single.x4.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>)588declare { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.urshl.single.x4.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>)589declare { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.urshl.single.x4.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>)590declare { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.urshl.single.x4.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>)591 592declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.srshl.x2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>)593declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.srshl.x2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>)594declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.srshl.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>)595declare { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.srshl.x2.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>)596 597declare { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }598 @llvm.aarch64.sve.srshl.x4.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>)599declare { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }600 @llvm.aarch64.sve.srshl.x4.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>)601declare { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }602 @llvm.aarch64.sve.srshl.x4.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>)603declare { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }604 @llvm.aarch64.sve.srshl.x4.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> )605 606declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.urshl.x2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>)607declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.urshl.x2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>)608declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.urshl.x2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>)609declare { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.urshl.x2.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>)610 611declare { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }612 @llvm.aarch64.sve.urshl.x4.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>)613declare { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }614 @llvm.aarch64.sve.urshl.x4.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>)615declare { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }616 @llvm.aarch64.sve.urshl.x4.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>)617declare { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }618 @llvm.aarch64.sve.urshl.x4.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>)619