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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; RUN: llc -force-streaming < %s | FileCheck %s3 4target triple = "aarch64"5 6define <vscale x 2 x i64> @test_tileslice_no_add(i32 %idx) #0 {7; CHECK-LABEL: test_tileslice_no_add:8; CHECK: // %bb.0: // %entry9; CHECK-NEXT: mov w8, w010; CHECK-NEXT: mov { z0.d, z1.d }, za.d[w8, 0, vgx2]11; CHECK-NEXT: // kill: def $z0 killed $z0 killed $z0_z112; CHECK-NEXT: ret13entry:14 %read = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sme.read.vg1x2.nxv2i64(i32 %idx)15 %read.ext = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %read, 016 ret <vscale x 2 x i64> %read.ext17}18 19define <vscale x 2 x i64> @test_tileslice_add_nonconstant(i32 %idx1, i32 %idx2) #0 {20; CHECK-LABEL: test_tileslice_add_nonconstant:21; CHECK: // %bb.0: // %entry22; CHECK-NEXT: add w8, w0, w123; CHECK-NEXT: mov { z0.d, z1.d }, za.d[w8, 0, vgx2]24; CHECK-NEXT: // kill: def $z0 killed $z0 killed $z0_z125; CHECK-NEXT: ret26entry:27 %add = add i32 %idx1, %idx228 %read = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sme.read.vg1x2.nxv2i64(i32 %add)29 %read.ext = extractvalue { <vscale x 2 x i64>, <vscale x 2 x i64> } %read, 030 ret <vscale x 2 x i64> %read.ext31}32 33declare { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sme.read.vg1x2.nxv2i64(i32)34 35attributes #0 = { nounwind "target-features"="+sme2" }36