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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 42; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme2 -force-streaming -verify-machineinstrs < %s | FileCheck %s3 4; SQDMULH (Single, x2)5 6define { <vscale x 16 x i8>, <vscale x 16 x i8> } @multi_vec_sat_double_mulh_single_x2_s8(<vscale x 16 x i8> %unused, <vscale x 16 x i8> %zdn1, <vscale x 16 x i8> %zdn2, <vscale x 16 x i8> %zm) {7; CHECK-LABEL: multi_vec_sat_double_mulh_single_x2_s8:8; CHECK: // %bb.0:9; CHECK-NEXT: mov z5.d, z2.d10; CHECK-NEXT: mov z4.d, z1.d11; CHECK-NEXT: sqdmulh { z4.b, z5.b }, { z4.b, z5.b }, z3.b12; CHECK-NEXT: mov z0.d, z4.d13; CHECK-NEXT: mov z1.d, z5.d14; CHECK-NEXT: ret15 %res = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.sqdmulh.single.vgx2.nxv16i8(<vscale x 16 x i8> %zdn1, <vscale x 16 x i8> %zdn2, <vscale x 16 x i8> %zm)16 ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %res17}18 19define { <vscale x 8 x i16>, <vscale x 8 x i16> } @multi_vec_sat_double_mulh_single_x2_s16(<vscale x 8 x i16> %unused, <vscale x 8 x i16> %zdn1, <vscale x 8 x i16> %zdn2, <vscale x 8 x i16> %zm) {20; CHECK-LABEL: multi_vec_sat_double_mulh_single_x2_s16:21; CHECK: // %bb.0:22; CHECK-NEXT: mov z5.d, z2.d23; CHECK-NEXT: mov z4.d, z1.d24; CHECK-NEXT: sqdmulh { z4.h, z5.h }, { z4.h, z5.h }, z3.h25; CHECK-NEXT: mov z0.d, z4.d26; CHECK-NEXT: mov z1.d, z5.d27; CHECK-NEXT: ret28 %res = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.sqdmulh.single.vgx2.nxv8i16(<vscale x 8 x i16> %zdn1, <vscale x 8 x i16> %zdn2, <vscale x 8 x i16> %zm)29 ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %res30}31 32define { <vscale x 4 x i32>, <vscale x 4 x i32> } @multi_vec_sat_double_mulh_single_x2_s32(<vscale x 4 x i32> %unused, <vscale x 4 x i32> %zdn1, <vscale x 4 x i32> %zdn2, <vscale x 4 x i32> %zm) {33; CHECK-LABEL: multi_vec_sat_double_mulh_single_x2_s32:34; CHECK: // %bb.0:35; CHECK-NEXT: mov z5.d, z2.d36; CHECK-NEXT: mov z4.d, z1.d37; CHECK-NEXT: sqdmulh { z4.s, z5.s }, { z4.s, z5.s }, z3.s38; CHECK-NEXT: mov z0.d, z4.d39; CHECK-NEXT: mov z1.d, z5.d40; CHECK-NEXT: ret41 %res = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.sqdmulh.single.vgx2.nxv4i32(<vscale x 4 x i32> %zdn1, <vscale x 4 x i32> %zdn2, <vscale x 4 x i32> %zm)42 ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %res43}44 45define { <vscale x 2 x i64>, <vscale x 2 x i64> } @multi_vec_sat_double_mulh_single_x2_s64(<vscale x 2 x i64> %unused, <vscale x 2 x i64> %zdn1, <vscale x 2 x i64> %zdn2, <vscale x 2 x i64> %zm) {46; CHECK-LABEL: multi_vec_sat_double_mulh_single_x2_s64:47; CHECK: // %bb.0:48; CHECK-NEXT: mov z5.d, z2.d49; CHECK-NEXT: mov z4.d, z1.d50; CHECK-NEXT: sqdmulh { z4.d, z5.d }, { z4.d, z5.d }, z3.d51; CHECK-NEXT: mov z0.d, z4.d52; CHECK-NEXT: mov z1.d, z5.d53; CHECK-NEXT: ret54 %res = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.sqdmulh.single.vgx2.nxv2i64(<vscale x 2 x i64> %zdn1, <vscale x 2 x i64> %zdn2, <vscale x 2 x i64> %zm)55 ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %res56}57 58; SQDMULH (Single, x4)59 60define { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @multi_vec_sat_double_mulh_single_x4_s8(<vscale x 16 x i8> %unused, <vscale x 16 x i8> %zdn1, <vscale x 16 x i8> %zdn2, <vscale x 16 x i8> %zdn3, <vscale x 16 x i8> %zdn4, <vscale x 16 x i8> %zm) {61; CHECK-LABEL: multi_vec_sat_double_mulh_single_x4_s8:62; CHECK: // %bb.0:63; CHECK-NEXT: mov z27.d, z4.d64; CHECK-NEXT: mov z26.d, z3.d65; CHECK-NEXT: mov z25.d, z2.d66; CHECK-NEXT: mov z24.d, z1.d67; CHECK-NEXT: sqdmulh { z24.b - z27.b }, { z24.b - z27.b }, z5.b68; CHECK-NEXT: mov z0.d, z24.d69; CHECK-NEXT: mov z1.d, z25.d70; CHECK-NEXT: mov z2.d, z26.d71; CHECK-NEXT: mov z3.d, z27.d72; CHECK-NEXT: ret73 %res = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }74 @llvm.aarch64.sve.sqdmulh.single.vgx4.nxv16i8(<vscale x 16 x i8> %zdn1, <vscale x 16 x i8> %zdn2, <vscale x 16 x i8> %zdn3, <vscale x 16 x i8> %zdn4, <vscale x 16 x i8> %zm)75 ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %res76}77 78define { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @multi_vec_sat_double_mulh_single_x4_s16(<vscale x 8 x i16> %unused, <vscale x 8 x i16> %zdn1, <vscale x 8 x i16> %zdn2, <vscale x 8 x i16> %zdn3, <vscale x 8 x i16> %zdn4, <vscale x 8 x i16> %zm) {79; CHECK-LABEL: multi_vec_sat_double_mulh_single_x4_s16:80; CHECK: // %bb.0:81; CHECK-NEXT: mov z27.d, z4.d82; CHECK-NEXT: mov z26.d, z3.d83; CHECK-NEXT: mov z25.d, z2.d84; CHECK-NEXT: mov z24.d, z1.d85; CHECK-NEXT: sqdmulh { z24.h - z27.h }, { z24.h - z27.h }, z5.h86; CHECK-NEXT: mov z0.d, z24.d87; CHECK-NEXT: mov z1.d, z25.d88; CHECK-NEXT: mov z2.d, z26.d89; CHECK-NEXT: mov z3.d, z27.d90; CHECK-NEXT: ret91 %res = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }92 @llvm.aarch64.sve.sqdmulh.single.vgx4.nxv8i16(<vscale x 8 x i16> %zdn1, <vscale x 8 x i16> %zdn2, <vscale x 8 x i16> %zdn3, <vscale x 8 x i16> %zdn4, <vscale x 8 x i16> %zm)93 ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %res94}95 96define { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @multi_vec_sat_double_mulh_single_x4_s32(<vscale x 4 x i32> %unused, <vscale x 4 x i32> %zdn1, <vscale x 4 x i32> %zdn2, <vscale x 4 x i32> %zdn3, <vscale x 4 x i32> %zdn4, <vscale x 4 x i32> %zm) {97; CHECK-LABEL: multi_vec_sat_double_mulh_single_x4_s32:98; CHECK: // %bb.0:99; CHECK-NEXT: mov z27.d, z4.d100; CHECK-NEXT: mov z26.d, z3.d101; CHECK-NEXT: mov z25.d, z2.d102; CHECK-NEXT: mov z24.d, z1.d103; CHECK-NEXT: sqdmulh { z24.s - z27.s }, { z24.s - z27.s }, z5.s104; CHECK-NEXT: mov z0.d, z24.d105; CHECK-NEXT: mov z1.d, z25.d106; CHECK-NEXT: mov z2.d, z26.d107; CHECK-NEXT: mov z3.d, z27.d108; CHECK-NEXT: ret109 %res = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }110 @llvm.aarch64.sve.sqdmulh.single.vgx4.nxv4i32(<vscale x 4 x i32> %zdn1, <vscale x 4 x i32> %zdn2, <vscale x 4 x i32> %zdn3, <vscale x 4 x i32> %zdn4, <vscale x 4 x i32> %zm)111 ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %res112}113 114define { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @multi_vec_sat_double_mulh_single_x4_s64(<vscale x 2 x i64> %unused, <vscale x 2 x i64> %zdn1, <vscale x 2 x i64> %zdn2, <vscale x 2 x i64> %zdn3, <vscale x 2 x i64> %zdn4, <vscale x 2 x i64> %zm) {115; CHECK-LABEL: multi_vec_sat_double_mulh_single_x4_s64:116; CHECK: // %bb.0:117; CHECK-NEXT: mov z27.d, z4.d118; CHECK-NEXT: mov z26.d, z3.d119; CHECK-NEXT: mov z25.d, z2.d120; CHECK-NEXT: mov z24.d, z1.d121; CHECK-NEXT: sqdmulh { z24.d - z27.d }, { z24.d - z27.d }, z5.d122; CHECK-NEXT: mov z0.d, z24.d123; CHECK-NEXT: mov z1.d, z25.d124; CHECK-NEXT: mov z2.d, z26.d125; CHECK-NEXT: mov z3.d, z27.d126; CHECK-NEXT: ret127 %res = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }128 @llvm.aarch64.sve.sqdmulh.single.vgx4.nxv2i64(<vscale x 2 x i64> %zdn1, <vscale x 2 x i64> %zdn2, <vscale x 2 x i64> %zdn3, <vscale x 2 x i64> %zdn4, <vscale x 2 x i64> %zm)129 ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %res130}131 132; SQDMULH (x2, Multi)133 134define { <vscale x 16 x i8>, <vscale x 16 x i8> } @multi_vec_sat_double_mulh_multi_x2_s8(<vscale x 16 x i8> %unused, <vscale x 16 x i8> %zdn1, <vscale x 16 x i8> %zdn2, <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2) {135; CHECK-LABEL: multi_vec_sat_double_mulh_multi_x2_s8:136; CHECK: // %bb.0:137; CHECK-NEXT: mov z7.d, z4.d138; CHECK-NEXT: mov z5.d, z2.d139; CHECK-NEXT: mov z6.d, z3.d140; CHECK-NEXT: mov z4.d, z1.d141; CHECK-NEXT: sqdmulh { z4.b, z5.b }, { z4.b, z5.b }, { z6.b, z7.b }142; CHECK-NEXT: mov z0.d, z4.d143; CHECK-NEXT: mov z1.d, z5.d144; CHECK-NEXT: ret145 %res = call { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.sqdmulh.vgx2.nxv16i8(<vscale x 16 x i8> %zdn1, <vscale x 16 x i8> %zdn2, <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2)146 ret { <vscale x 16 x i8>, <vscale x 16 x i8> } %res147}148 149define { <vscale x 8 x i16>, <vscale x 8 x i16> } @multi_vec_sat_double_mulh_multi_x2_s16(<vscale x 8 x i16> %unused, <vscale x 8 x i16> %zdn1, <vscale x 8 x i16> %zdn2, <vscale x 8 x i16> %zm1, <vscale x 8 x i16> %zm2) {150; CHECK-LABEL: multi_vec_sat_double_mulh_multi_x2_s16:151; CHECK: // %bb.0:152; CHECK-NEXT: mov z7.d, z4.d153; CHECK-NEXT: mov z5.d, z2.d154; CHECK-NEXT: mov z6.d, z3.d155; CHECK-NEXT: mov z4.d, z1.d156; CHECK-NEXT: sqdmulh { z4.h, z5.h }, { z4.h, z5.h }, { z6.h, z7.h }157; CHECK-NEXT: mov z0.d, z4.d158; CHECK-NEXT: mov z1.d, z5.d159; CHECK-NEXT: ret160 %res = call { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.sqdmulh.vgx2.nxv8i16(<vscale x 8 x i16> %zdn1, <vscale x 8 x i16> %zdn2, <vscale x 8 x i16> %zm1, <vscale x 8 x i16> %zm2)161 ret { <vscale x 8 x i16>, <vscale x 8 x i16> } %res162}163 164define { <vscale x 4 x i32>, <vscale x 4 x i32> } @multi_vec_sat_double_mulh_multi_x2_s32(<vscale x 4 x i32> %unused, <vscale x 4 x i32> %zdn1, <vscale x 4 x i32> %zdn2, <vscale x 4 x i32> %zm1, <vscale x 4 x i32> %zm2) {165; CHECK-LABEL: multi_vec_sat_double_mulh_multi_x2_s32:166; CHECK: // %bb.0:167; CHECK-NEXT: mov z7.d, z4.d168; CHECK-NEXT: mov z5.d, z2.d169; CHECK-NEXT: mov z6.d, z3.d170; CHECK-NEXT: mov z4.d, z1.d171; CHECK-NEXT: sqdmulh { z4.s, z5.s }, { z4.s, z5.s }, { z6.s, z7.s }172; CHECK-NEXT: mov z0.d, z4.d173; CHECK-NEXT: mov z1.d, z5.d174; CHECK-NEXT: ret175 %res = call { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.sqdmulh.vgx2.nxv4i32(<vscale x 4 x i32> %zdn1, <vscale x 4 x i32> %zdn2, <vscale x 4 x i32> %zm1, <vscale x 4 x i32> %zm2)176 ret { <vscale x 4 x i32>, <vscale x 4 x i32> } %res177}178 179define { <vscale x 2 x i64>, <vscale x 2 x i64> } @multi_vec_sat_double_mulh_multi_x2_s64(<vscale x 2 x i64> %unused, <vscale x 2 x i64> %zdn1, <vscale x 2 x i64> %zdn2, <vscale x 2 x i64> %zm1, <vscale x 2 x i64> %zm2) {180; CHECK-LABEL: multi_vec_sat_double_mulh_multi_x2_s64:181; CHECK: // %bb.0:182; CHECK-NEXT: mov z7.d, z4.d183; CHECK-NEXT: mov z5.d, z2.d184; CHECK-NEXT: mov z6.d, z3.d185; CHECK-NEXT: mov z4.d, z1.d186; CHECK-NEXT: sqdmulh { z4.d, z5.d }, { z4.d, z5.d }, { z6.d, z7.d }187; CHECK-NEXT: mov z0.d, z4.d188; CHECK-NEXT: mov z1.d, z5.d189; CHECK-NEXT: ret190 %res = call { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.sqdmulh.vgx2.nxv2i64(<vscale x 2 x i64> %zdn1, <vscale x 2 x i64> %zdn2, <vscale x 2 x i64> %zm1, <vscale x 2 x i64> %zm2)191 ret { <vscale x 2 x i64>, <vscale x 2 x i64> } %res192}193 194; SQDMULH (x4, Multi)195 196define { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } @multi_vec_sat_double_mulh_multi_x4_s8(<vscale x 16 x i8> %unused, <vscale x 16 x i8> %zdn1, <vscale x 16 x i8> %zdn2, <vscale x 16 x i8> %zdn3, <vscale x 16 x i8> %zdn4,197; CHECK-LABEL: multi_vec_sat_double_mulh_multi_x4_s8:198; CHECK: // %bb.0:199; CHECK-NEXT: mov z30.d, z7.d200; CHECK-NEXT: mov z27.d, z4.d201; CHECK-NEXT: mov z29.d, z6.d202; CHECK-NEXT: mov z26.d, z3.d203; CHECK-NEXT: mov z28.d, z5.d204; CHECK-NEXT: mov z25.d, z2.d205; CHECK-NEXT: ldr z31, [x0]206; CHECK-NEXT: mov z24.d, z1.d207; CHECK-NEXT: sqdmulh { z24.b - z27.b }, { z24.b - z27.b }, { z28.b - z31.b }208; CHECK-NEXT: mov z0.d, z24.d209; CHECK-NEXT: mov z1.d, z25.d210; CHECK-NEXT: mov z2.d, z26.d211; CHECK-NEXT: mov z3.d, z27.d212; CHECK-NEXT: ret213 <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2, <vscale x 16 x i8> %zm3, <vscale x 16 x i8> %zm4) {214 %res = call { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }215 @llvm.aarch64.sve.sqdmulh.vgx4.nxv16i8(<vscale x 16 x i8> %zdn1, <vscale x 16 x i8> %zdn2, <vscale x 16 x i8> %zdn3, <vscale x 16 x i8> %zdn4,216 <vscale x 16 x i8> %zm1, <vscale x 16 x i8> %zm2, <vscale x 16 x i8> %zm3, <vscale x 16 x i8> %zm4)217 ret { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> } %res218}219 220define { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } @multi_vec_sat_double_mulh_multi_x4_s16(<vscale x 8 x i16> %unused, <vscale x 8 x i16> %zdn1, <vscale x 8 x i16> %zdn2, <vscale x 8 x i16> %zdn3, <vscale x 8 x i16> %zdn4,221; CHECK-LABEL: multi_vec_sat_double_mulh_multi_x4_s16:222; CHECK: // %bb.0:223; CHECK-NEXT: mov z30.d, z7.d224; CHECK-NEXT: mov z27.d, z4.d225; CHECK-NEXT: mov z29.d, z6.d226; CHECK-NEXT: mov z26.d, z3.d227; CHECK-NEXT: mov z28.d, z5.d228; CHECK-NEXT: mov z25.d, z2.d229; CHECK-NEXT: ldr z31, [x0]230; CHECK-NEXT: mov z24.d, z1.d231; CHECK-NEXT: sqdmulh { z24.h - z27.h }, { z24.h - z27.h }, { z28.h - z31.h }232; CHECK-NEXT: mov z0.d, z24.d233; CHECK-NEXT: mov z1.d, z25.d234; CHECK-NEXT: mov z2.d, z26.d235; CHECK-NEXT: mov z3.d, z27.d236; CHECK-NEXT: ret237 <vscale x 8 x i16> %zm1, <vscale x 8 x i16> %zm2, <vscale x 8 x i16> %zm3, <vscale x 8 x i16> %zm4) {238 %res = call { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }239 @llvm.aarch64.sve.sqdmulh.vgx4.nxv8i16(<vscale x 8 x i16> %zdn1, <vscale x 8 x i16> %zdn2, <vscale x 8 x i16> %zdn3, <vscale x 8 x i16> %zdn4,240 <vscale x 8 x i16> %zm1, <vscale x 8 x i16> %zm2, <vscale x 8 x i16> %zm3, <vscale x 8 x i16> %zm4)241 ret { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> } %res242}243 244define { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } @multi_vec_sat_double_mulh_multi_x4_s32(<vscale x 4 x i32> %unused, <vscale x 4 x i32> %zdn1, <vscale x 4 x i32> %zdn2, <vscale x 4 x i32> %zdn3, <vscale x 4 x i32> %zdn4,245; CHECK-LABEL: multi_vec_sat_double_mulh_multi_x4_s32:246; CHECK: // %bb.0:247; CHECK-NEXT: mov z30.d, z7.d248; CHECK-NEXT: mov z27.d, z4.d249; CHECK-NEXT: mov z29.d, z6.d250; CHECK-NEXT: mov z26.d, z3.d251; CHECK-NEXT: mov z28.d, z5.d252; CHECK-NEXT: mov z25.d, z2.d253; CHECK-NEXT: ldr z31, [x0]254; CHECK-NEXT: mov z24.d, z1.d255; CHECK-NEXT: sqdmulh { z24.s - z27.s }, { z24.s - z27.s }, { z28.s - z31.s }256; CHECK-NEXT: mov z0.d, z24.d257; CHECK-NEXT: mov z1.d, z25.d258; CHECK-NEXT: mov z2.d, z26.d259; CHECK-NEXT: mov z3.d, z27.d260; CHECK-NEXT: ret261 <vscale x 4 x i32> %zm1, <vscale x 4 x i32> %zm2, <vscale x 4 x i32> %zm3, <vscale x 4 x i32> %zm4) {262 %res = call { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }263 @llvm.aarch64.sve.sqdmulh.vgx4.nxv4i32(<vscale x 4 x i32> %zdn1, <vscale x 4 x i32> %zdn2, <vscale x 4 x i32> %zdn3, <vscale x 4 x i32> %zdn4,264 <vscale x 4 x i32> %zm1, <vscale x 4 x i32> %zm2, <vscale x 4 x i32> %zm3, <vscale x 4 x i32> %zm4)265 ret { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> } %res266}267 268define { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } @multi_vec_sat_double_mulh_multi_x4_s64(<vscale x 2 x i64> %unused, <vscale x 2 x i64> %zdn1, <vscale x 2 x i64> %zdn2, <vscale x 2 x i64> %zdn3, <vscale x 2 x i64> %zdn4,269; CHECK-LABEL: multi_vec_sat_double_mulh_multi_x4_s64:270; CHECK: // %bb.0:271; CHECK-NEXT: mov z30.d, z7.d272; CHECK-NEXT: mov z27.d, z4.d273; CHECK-NEXT: mov z29.d, z6.d274; CHECK-NEXT: mov z26.d, z3.d275; CHECK-NEXT: mov z28.d, z5.d276; CHECK-NEXT: mov z25.d, z2.d277; CHECK-NEXT: ldr z31, [x0]278; CHECK-NEXT: mov z24.d, z1.d279; CHECK-NEXT: sqdmulh { z24.d - z27.d }, { z24.d - z27.d }, { z28.d - z31.d }280; CHECK-NEXT: mov z0.d, z24.d281; CHECK-NEXT: mov z1.d, z25.d282; CHECK-NEXT: mov z2.d, z26.d283; CHECK-NEXT: mov z3.d, z27.d284; CHECK-NEXT: ret285 <vscale x 2 x i64> %zm1, <vscale x 2 x i64> %zm2, <vscale x 2 x i64> %zm3, <vscale x 2 x i64> %zm4) {286 %res = call { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }287 @llvm.aarch64.sve.sqdmulh.vgx4.nxv2i64(<vscale x 2 x i64> %zdn1, <vscale x 2 x i64> %zdn2, <vscale x 2 x i64> %zdn3, <vscale x 2 x i64> %zdn4,288 <vscale x 2 x i64> %zm1, <vscale x 2 x i64> %zm2, <vscale x 2 x i64> %zm3, <vscale x 2 x i64> %zm4)289 ret { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> } %res290}291 292declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.sqdmulh.single.vgx2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>)293declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.sqdmulh.single.vgx2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>)294declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.sqdmulh.single.vgx2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>)295declare { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.sqdmulh.single.vgx2.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>)296 297declare { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }298 @llvm.aarch64.sve.sqdmulh.single.vgx4.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>)299declare { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }300 @llvm.aarch64.sve.sqdmulh.single.vgx4.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>)301declare { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }302 @llvm.aarch64.sve.sqdmulh.single.vgx4.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>)303declare { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }304 @llvm.aarch64.sve.sqdmulh.single.vgx4.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>)305 306declare { <vscale x 16 x i8>, <vscale x 16 x i8> } @llvm.aarch64.sve.sqdmulh.vgx2.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>)307declare { <vscale x 8 x i16>, <vscale x 8 x i16> } @llvm.aarch64.sve.sqdmulh.vgx2.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>)308declare { <vscale x 4 x i32>, <vscale x 4 x i32> } @llvm.aarch64.sve.sqdmulh.vgx2.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>)309declare { <vscale x 2 x i64>, <vscale x 2 x i64> } @llvm.aarch64.sve.sqdmulh.vgx2.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>)310 311declare { <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8> }312 @llvm.aarch64.sve.sqdmulh.vgx4.nxv16i8(<vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>,313 <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>)314declare { <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16> }315 @llvm.aarch64.sve.sqdmulh.vgx4.nxv8i16(<vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>,316 <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>)317declare { <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32> }318 @llvm.aarch64.sve.sqdmulh.vgx4.nxv4i32(<vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>,319 <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>)320declare { <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64> }321 @llvm.aarch64.sve.sqdmulh.vgx4.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>,322 <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>)323