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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme2 -mattr=+sme-i16i64 -mattr=+sme-f64f64 -force-streaming -verify-machineinstrs < %s | FileCheck %s3 4;5; SUB Multi-Single x26;7 8define void @multi_vector_sub_write_single_za_vg1x2_i32(i32 %slice, <vscale x 4 x i32> %zn0, <vscale x 4 x i32> %zn1, <vscale x 4 x i32> %zm) {9; CHECK-LABEL: multi_vector_sub_write_single_za_vg1x2_i32:10; CHECK: // %bb.0:11; CHECK-NEXT: // kill: def $z1 killed $z1 killed $z0_z1 def $z0_z112; CHECK-NEXT: mov w8, w013; CHECK-NEXT: // kill: def $z0 killed $z0 killed $z0_z1 def $z0_z114; CHECK-NEXT: sub za.s[w8, 0, vgx2], { z0.s, z1.s }, z2.s15; CHECK-NEXT: sub za.s[w8, 7, vgx2], { z0.s, z1.s }, z2.s16; CHECK-NEXT: ret17 call void @llvm.aarch64.sme.sub.write.single.za.vg1x2.nxv4i32(i32 %slice,18 <vscale x 4 x i32> %zn0, <vscale x 4 x i32> %zn1,19 <vscale x 4 x i32> %zm)20 %slice.7 = add i32 %slice, 721 call void @llvm.aarch64.sme.sub.write.single.za.vg1x2.nxv4i32(i32 %slice.7,22 <vscale x 4 x i32> %zn0, <vscale x 4 x i32> %zn1,23 <vscale x 4 x i32> %zm)24 ret void25}26 27define void @multi_vector_sub_write_single_za_vg1x2_i64(i32 %slice, <vscale x 2 x i64> %zn0, <vscale x 2 x i64> %zn1, <vscale x 2 x i64> %zm) {28; CHECK-LABEL: multi_vector_sub_write_single_za_vg1x2_i64:29; CHECK: // %bb.0:30; CHECK-NEXT: // kill: def $z1 killed $z1 killed $z0_z1 def $z0_z131; CHECK-NEXT: mov w8, w032; CHECK-NEXT: // kill: def $z0 killed $z0 killed $z0_z1 def $z0_z133; CHECK-NEXT: sub za.d[w8, 0, vgx2], { z0.d, z1.d }, z2.d34; CHECK-NEXT: sub za.d[w8, 7, vgx2], { z0.d, z1.d }, z2.d35; CHECK-NEXT: ret36 call void @llvm.aarch64.sme.sub.write.single.za.vg1x2.nxv2i64(i32 %slice,37 <vscale x 2 x i64> %zn0, <vscale x 2 x i64> %zn1,38 <vscale x 2 x i64> %zm)39 %slice.7 = add i32 %slice, 740 call void @llvm.aarch64.sme.sub.write.single.za.vg1x2.nxv2i64(i32 %slice.7,41 <vscale x 2 x i64> %zn0, <vscale x 2 x i64> %zn1,42 <vscale x 2 x i64> %zm)43 ret void44}45 46;47; SUB Multi-Single x448;49 50define void @multi_vector_sub_write_single_za_vg1x4_i32(i32 %slice, <vscale x 4 x i32> %zn0, <vscale x 4 x i32> %zn1,51; CHECK-LABEL: multi_vector_sub_write_single_za_vg1x4_i32:52; CHECK: // %bb.0:53; CHECK-NEXT: // kill: def $z3 killed $z3 killed $z0_z1_z2_z3 def $z0_z1_z2_z354; CHECK-NEXT: mov w8, w055; CHECK-NEXT: // kill: def $z2 killed $z2 killed $z0_z1_z2_z3 def $z0_z1_z2_z356; CHECK-NEXT: // kill: def $z1 killed $z1 killed $z0_z1_z2_z3 def $z0_z1_z2_z357; CHECK-NEXT: // kill: def $z0 killed $z0 killed $z0_z1_z2_z3 def $z0_z1_z2_z358; CHECK-NEXT: sub za.s[w8, 0, vgx4], { z0.s - z3.s }, z4.s59; CHECK-NEXT: sub za.s[w8, 7, vgx4], { z0.s - z3.s }, z4.s60; CHECK-NEXT: ret61 <vscale x 4 x i32> %zn2, <vscale x 4 x i32> %zn3,62 <vscale x 4 x i32> %zm) {63 call void @llvm.aarch64.sme.sub.write.single.za.vg1x4.nxv4i32(i32 %slice,64 <vscale x 4 x i32> %zn0, <vscale x 4 x i32> %zn1,65 <vscale x 4 x i32> %zn2, <vscale x 4 x i32> %zn3,66 <vscale x 4 x i32> %zm)67 %slice.7 = add i32 %slice, 768 call void @llvm.aarch64.sme.sub.write.single.za.vg1x4.nxv4i32(i32 %slice.7,69 <vscale x 4 x i32> %zn0, <vscale x 4 x i32> %zn1,70 <vscale x 4 x i32> %zn2, <vscale x 4 x i32> %zn3,71 <vscale x 4 x i32> %zm)72 ret void73}74 75define void @multi_vector_sub_write_single_za_vg1x4_i64(i32 %slice,76; CHECK-LABEL: multi_vector_sub_write_single_za_vg1x4_i64:77; CHECK: // %bb.0:78; CHECK-NEXT: // kill: def $z3 killed $z3 killed $z0_z1_z2_z3 def $z0_z1_z2_z379; CHECK-NEXT: mov w8, w080; CHECK-NEXT: // kill: def $z2 killed $z2 killed $z0_z1_z2_z3 def $z0_z1_z2_z381; CHECK-NEXT: // kill: def $z1 killed $z1 killed $z0_z1_z2_z3 def $z0_z1_z2_z382; CHECK-NEXT: // kill: def $z0 killed $z0 killed $z0_z1_z2_z3 def $z0_z1_z2_z383; CHECK-NEXT: sub za.d[w8, 0, vgx4], { z0.d - z3.d }, z4.d84; CHECK-NEXT: sub za.d[w8, 7, vgx4], { z0.d - z3.d }, z4.d85; CHECK-NEXT: ret86 <vscale x 2 x i64> %zn0, <vscale x 2 x i64> %zn1,87 <vscale x 2 x i64> %zn2, <vscale x 2 x i64> %zn3,88 <vscale x 2 x i64> %zm) {89 call void @llvm.aarch64.sme.sub.write.single.za.vg1x4.nxv2i64(i32 %slice,90 <vscale x 2 x i64> %zn0, <vscale x 2 x i64> %zn1,91 <vscale x 2 x i64> %zn2, <vscale x 2 x i64> %zn3,92 <vscale x 2 x i64> %zm)93 %slice.7 = add i32 %slice, 794 call void @llvm.aarch64.sme.sub.write.single.za.vg1x4.nxv2i64(i32 %slice.7,95 <vscale x 2 x i64> %zn0, <vscale x 2 x i64> %zn1,96 <vscale x 2 x i64> %zn2, <vscale x 2 x i64> %zn3,97 <vscale x 2 x i64> %zm)98 ret void99}100 101;102; SUB Multi-Multi x2103;104 105define void @multi_vector_sub_write_za_vg1x2_i32(i32 %slice, <vscale x 4 x i32> %zn0, <vscale x 4 x i32> %zn1,106; CHECK-LABEL: multi_vector_sub_write_za_vg1x2_i32:107; CHECK: // %bb.0:108; CHECK-NEXT: // kill: def $z3 killed $z3 killed $z2_z3 def $z2_z3109; CHECK-NEXT: // kill: def $z1 killed $z1 killed $z0_z1 def $z0_z1110; CHECK-NEXT: mov w8, w0111; CHECK-NEXT: // kill: def $z2 killed $z2 killed $z2_z3 def $z2_z3112; CHECK-NEXT: // kill: def $z0 killed $z0 killed $z0_z1 def $z0_z1113; CHECK-NEXT: sub za.s[w8, 0, vgx2], { z0.s, z1.s }, { z2.s, z3.s }114; CHECK-NEXT: sub za.s[w8, 7, vgx2], { z0.s, z1.s }, { z2.s, z3.s }115; CHECK-NEXT: ret116 <vscale x 4 x i32> %zm1, <vscale x 4 x i32> %zm2) {117 call void @llvm.aarch64.sme.sub.write.za.vg1x2.nxv4i32(i32 %slice,118 <vscale x 4 x i32> %zn0, <vscale x 4 x i32> %zn1,119 <vscale x 4 x i32> %zm1, <vscale x 4 x i32> %zm2)120 %slice.7 = add i32 %slice, 7121 call void @llvm.aarch64.sme.sub.write.za.vg1x2.nxv4i32(i32 %slice.7,122 <vscale x 4 x i32> %zn0, <vscale x 4 x i32> %zn1,123 <vscale x 4 x i32> %zm1, <vscale x 4 x i32> %zm2)124 ret void125}126 127 128define void @multi_vector_sub_write_za_vg1x2_i64(i32 %slice, <vscale x 2 x i64> %zn0, <vscale x 2 x i64> %zn1,129; CHECK-LABEL: multi_vector_sub_write_za_vg1x2_i64:130; CHECK: // %bb.0:131; CHECK-NEXT: // kill: def $z3 killed $z3 killed $z2_z3 def $z2_z3132; CHECK-NEXT: // kill: def $z1 killed $z1 killed $z0_z1 def $z0_z1133; CHECK-NEXT: mov w8, w0134; CHECK-NEXT: // kill: def $z2 killed $z2 killed $z2_z3 def $z2_z3135; CHECK-NEXT: // kill: def $z0 killed $z0 killed $z0_z1 def $z0_z1136; CHECK-NEXT: sub za.d[w8, 0, vgx2], { z0.d, z1.d }, { z2.d, z3.d }137; CHECK-NEXT: sub za.d[w8, 7, vgx2], { z0.d, z1.d }, { z2.d, z3.d }138; CHECK-NEXT: ret139 <vscale x 2 x i64> %zm1, <vscale x 2 x i64> %zm2) {140 call void @llvm.aarch64.sme.sub.write.za.vg1x2.nxv2i64(i32 %slice,141 <vscale x 2 x i64> %zn0, <vscale x 2 x i64> %zn1,142 <vscale x 2 x i64> %zm1, <vscale x 2 x i64> %zm2)143 %slice.7 = add i32 %slice, 7144 call void @llvm.aarch64.sme.sub.write.za.vg1x2.nxv2i64(i32 %slice.7,145 <vscale x 2 x i64> %zn0, <vscale x 2 x i64> %zn1,146 <vscale x 2 x i64> %zm1, <vscale x 2 x i64> %zm2)147 ret void148}149 150 151;152; SUB Multi-Multi x4153;154 155define void @multi_vector_sub_write_za_vg1x4_i32(i32 %slice, <vscale x 4 x i32> %zn0, <vscale x 4 x i32> %zn1,156; CHECK-LABEL: multi_vector_sub_write_za_vg1x4_i32:157; CHECK: // %bb.0:158; CHECK-NEXT: // kill: def $z7 killed $z7 killed $z4_z5_z6_z7 def $z4_z5_z6_z7159; CHECK-NEXT: // kill: def $z3 killed $z3 killed $z0_z1_z2_z3 def $z0_z1_z2_z3160; CHECK-NEXT: mov w8, w0161; CHECK-NEXT: // kill: def $z6 killed $z6 killed $z4_z5_z6_z7 def $z4_z5_z6_z7162; CHECK-NEXT: // kill: def $z2 killed $z2 killed $z0_z1_z2_z3 def $z0_z1_z2_z3163; CHECK-NEXT: // kill: def $z5 killed $z5 killed $z4_z5_z6_z7 def $z4_z5_z6_z7164; CHECK-NEXT: // kill: def $z1 killed $z1 killed $z0_z1_z2_z3 def $z0_z1_z2_z3165; CHECK-NEXT: // kill: def $z4 killed $z4 killed $z4_z5_z6_z7 def $z4_z5_z6_z7166; CHECK-NEXT: // kill: def $z0 killed $z0 killed $z0_z1_z2_z3 def $z0_z1_z2_z3167; CHECK-NEXT: sub za.s[w8, 0, vgx4], { z0.s - z3.s }, { z4.s - z7.s }168; CHECK-NEXT: sub za.s[w8, 7, vgx4], { z0.s - z3.s }, { z4.s - z7.s }169; CHECK-NEXT: ret170 <vscale x 4 x i32> %zn2, <vscale x 4 x i32> %zn3,171 <vscale x 4 x i32> %zm0, <vscale x 4 x i32> %zm1,172 <vscale x 4 x i32> %zm2, <vscale x 4 x i32> %zm3) {173 call void @llvm.aarch64.sme.sub.write.za.vg1x4.nxv4i32(i32 %slice,174 <vscale x 4 x i32> %zn0, <vscale x 4 x i32> %zn1,175 <vscale x 4 x i32> %zn2, <vscale x 4 x i32> %zn3,176 <vscale x 4 x i32> %zm0, <vscale x 4 x i32> %zm1,177 <vscale x 4 x i32> %zm2, <vscale x 4 x i32> %zm3)178 %slice.7 = add i32 %slice, 7179 call void @llvm.aarch64.sme.sub.write.za.vg1x4.nxv4i32(i32 %slice.7,180 <vscale x 4 x i32> %zn0, <vscale x 4 x i32> %zn1,181 <vscale x 4 x i32> %zn2, <vscale x 4 x i32> %zn3,182 <vscale x 4 x i32> %zm0, <vscale x 4 x i32> %zm1,183 <vscale x 4 x i32> %zm2, <vscale x 4 x i32> %zm3)184 ret void185}186 187define void @multi_vector_sub_write_za_vg1x4_i64(i32 %slice, <vscale x 2 x i64> %zn0, <vscale x 2 x i64> %zn1,188; CHECK-LABEL: multi_vector_sub_write_za_vg1x4_i64:189; CHECK: // %bb.0:190; CHECK-NEXT: // kill: def $z7 killed $z7 killed $z4_z5_z6_z7 def $z4_z5_z6_z7191; CHECK-NEXT: // kill: def $z3 killed $z3 killed $z0_z1_z2_z3 def $z0_z1_z2_z3192; CHECK-NEXT: mov w8, w0193; CHECK-NEXT: // kill: def $z6 killed $z6 killed $z4_z5_z6_z7 def $z4_z5_z6_z7194; CHECK-NEXT: // kill: def $z2 killed $z2 killed $z0_z1_z2_z3 def $z0_z1_z2_z3195; CHECK-NEXT: // kill: def $z5 killed $z5 killed $z4_z5_z6_z7 def $z4_z5_z6_z7196; CHECK-NEXT: // kill: def $z1 killed $z1 killed $z0_z1_z2_z3 def $z0_z1_z2_z3197; CHECK-NEXT: // kill: def $z4 killed $z4 killed $z4_z5_z6_z7 def $z4_z5_z6_z7198; CHECK-NEXT: // kill: def $z0 killed $z0 killed $z0_z1_z2_z3 def $z0_z1_z2_z3199; CHECK-NEXT: sub za.d[w8, 0, vgx4], { z0.d - z3.d }, { z4.d - z7.d }200; CHECK-NEXT: sub za.d[w8, 7, vgx4], { z0.d - z3.d }, { z4.d - z7.d }201; CHECK-NEXT: ret202 <vscale x 2 x i64> %zn2, <vscale x 2 x i64> %zn3,203 <vscale x 2 x i64> %zm0, <vscale x 2 x i64> %zm1,204 <vscale x 2 x i64> %zm2, <vscale x 2 x i64> %zm3) {205 call void @llvm.aarch64.sme.sub.write.za.vg1x4.nxv2i64(i32 %slice,206 <vscale x 2 x i64> %zn0, <vscale x 2 x i64> %zn1,207 <vscale x 2 x i64> %zn2, <vscale x 2 x i64> %zn3,208 <vscale x 2 x i64> %zm0, <vscale x 2 x i64> %zm1,209 <vscale x 2 x i64> %zm2, <vscale x 2 x i64> %zm3)210 %slice.7 = add i32 %slice, 7211 call void @llvm.aarch64.sme.sub.write.za.vg1x4.nxv2i64(i32 %slice.7,212 <vscale x 2 x i64> %zn0, <vscale x 2 x i64> %zn1,213 <vscale x 2 x i64> %zn2, <vscale x 2 x i64> %zn3,214 <vscale x 2 x i64> %zm0, <vscale x 2 x i64> %zm1,215 <vscale x 2 x i64> %zm2, <vscale x 2 x i64> %zm3)216 ret void217}218 219 220;221; SUB and accumulate into ZA222;223 224; x2225define void @multi_vector_sub_za_vg1x2_i32(i32 %slice, <vscale x 4 x i32> %zn0, <vscale x 4 x i32> %zn1) {226; CHECK-LABEL: multi_vector_sub_za_vg1x2_i32:227; CHECK: // %bb.0:228; CHECK-NEXT: // kill: def $z1 killed $z1 killed $z0_z1 def $z0_z1229; CHECK-NEXT: mov w8, w0230; CHECK-NEXT: // kill: def $z0 killed $z0 killed $z0_z1 def $z0_z1231; CHECK-NEXT: sub za.s[w8, 0, vgx2], { z0.s, z1.s }232; CHECK-NEXT: sub za.s[w8, 7, vgx2], { z0.s, z1.s }233; CHECK-NEXT: ret234 call void @llvm.aarch64.sme.sub.za32.vg1x2.nxv4i32(i32 %slice,<vscale x 4 x i32> %zn0, <vscale x 4 x i32> %zn1)235 %slice.7 = add i32 %slice, 7236 call void @llvm.aarch64.sme.sub.za32.vg1x2.nxv4i32(i32 %slice.7, <vscale x 4 x i32> %zn0, <vscale x 4 x i32> %zn1)237 ret void238}239 240define void @multi_vector_sub_za_vg1x2_i64(i32 %slice, <vscale x 2 x i64> %zn0, <vscale x 2 x i64> %zn1) {241; CHECK-LABEL: multi_vector_sub_za_vg1x2_i64:242; CHECK: // %bb.0:243; CHECK-NEXT: // kill: def $z1 killed $z1 killed $z0_z1 def $z0_z1244; CHECK-NEXT: mov w8, w0245; CHECK-NEXT: // kill: def $z0 killed $z0 killed $z0_z1 def $z0_z1246; CHECK-NEXT: sub za.d[w8, 0, vgx2], { z0.d, z1.d }247; CHECK-NEXT: sub za.d[w8, 7, vgx2], { z0.d, z1.d }248; CHECK-NEXT: ret249 call void @llvm.aarch64.sme.sub.za64.vg1x2.nxv2i64(i32 %slice, <vscale x 2 x i64> %zn0, <vscale x 2 x i64> %zn1)250 %slice.7 = add i32 %slice, 7251 call void @llvm.aarch64.sme.sub.za64.vg1x2.nxv2i64(i32 %slice.7, <vscale x 2 x i64> %zn0, <vscale x 2 x i64> %zn1)252 ret void253}254 255define void @multi_vector_sub_za_vg1x2_f32(i32 %slice, <vscale x 4 x float> %zn0, <vscale x 4 x float> %zn1) {256; CHECK-LABEL: multi_vector_sub_za_vg1x2_f32:257; CHECK: // %bb.0:258; CHECK-NEXT: // kill: def $z1 killed $z1 killed $z0_z1 def $z0_z1259; CHECK-NEXT: mov w8, w0260; CHECK-NEXT: // kill: def $z0 killed $z0 killed $z0_z1 def $z0_z1261; CHECK-NEXT: fsub za.s[w8, 0, vgx2], { z0.s, z1.s }262; CHECK-NEXT: fsub za.s[w8, 7, vgx2], { z0.s, z1.s }263; CHECK-NEXT: ret264 call void @llvm.aarch64.sme.sub.za32.vg1x2.nxv4f32(i32 %slice,265 <vscale x 4 x float> %zn0, <vscale x 4 x float> %zn1)266 %slice.7 = add i32 %slice, 7267 call void @llvm.aarch64.sme.sub.za32.vg1x2.nxv4f32(i32 %slice.7,268 <vscale x 4 x float> %zn0, <vscale x 4 x float> %zn1)269 ret void270}271 272define void @multi_vector_sub_za_vg1x2_f64(i32 %slice, <vscale x 2 x double> %zn0, <vscale x 2 x double> %zn1) {273; CHECK-LABEL: multi_vector_sub_za_vg1x2_f64:274; CHECK: // %bb.0:275; CHECK-NEXT: // kill: def $z1 killed $z1 killed $z0_z1 def $z0_z1276; CHECK-NEXT: mov w8, w0277; CHECK-NEXT: // kill: def $z0 killed $z0 killed $z0_z1 def $z0_z1278; CHECK-NEXT: fsub za.d[w8, 0, vgx2], { z0.d, z1.d }279; CHECK-NEXT: fsub za.d[w8, 7, vgx2], { z0.d, z1.d }280; CHECK-NEXT: ret281 call void @llvm.aarch64.sme.sub.za64.vg1x2.nxv2f64(i32 %slice,282 <vscale x 2 x double> %zn0, <vscale x 2 x double> %zn1)283 %slice.7 = add i32 %slice, 7284 call void @llvm.aarch64.sme.sub.za64.vg1x2.nxv2f64(i32 %slice.7,285 <vscale x 2 x double> %zn0, <vscale x 2 x double> %zn1)286 ret void287}288 289; x4290 291define void @multi_vector_sub_za_vg1x4_i32(i32 %slice,292; CHECK-LABEL: multi_vector_sub_za_vg1x4_i32:293; CHECK: // %bb.0:294; CHECK-NEXT: // kill: def $z3 killed $z3 killed $z0_z1_z2_z3 def $z0_z1_z2_z3295; CHECK-NEXT: mov w8, w0296; CHECK-NEXT: // kill: def $z2 killed $z2 killed $z0_z1_z2_z3 def $z0_z1_z2_z3297; CHECK-NEXT: // kill: def $z1 killed $z1 killed $z0_z1_z2_z3 def $z0_z1_z2_z3298; CHECK-NEXT: // kill: def $z0 killed $z0 killed $z0_z1_z2_z3 def $z0_z1_z2_z3299; CHECK-NEXT: sub za.s[w8, 0, vgx4], { z0.s - z3.s }300; CHECK-NEXT: sub za.s[w8, 7, vgx4], { z0.s - z3.s }301; CHECK-NEXT: ret302 <vscale x 4 x i32> %zn0, <vscale x 4 x i32> %zn1,303 <vscale x 4 x i32> %zn2, <vscale x 4 x i32> %zn3) {304 call void @llvm.aarch64.sme.sub.za32.vg1x4.nxv4i32(i32 %slice,305 <vscale x 4 x i32> %zn0, <vscale x 4 x i32> %zn1,306 <vscale x 4 x i32> %zn2, <vscale x 4 x i32> %zn3)307 %slice.7 = add i32 %slice, 7308 call void @llvm.aarch64.sme.sub.za32.vg1x4.nxv4i32(i32 %slice.7,309 <vscale x 4 x i32> %zn0, <vscale x 4 x i32> %zn1,310 <vscale x 4 x i32> %zn2, <vscale x 4 x i32> %zn3)311 ret void312}313 314define void @multi_vector_sub_za_vg1x4_i64(i32 %slice,315; CHECK-LABEL: multi_vector_sub_za_vg1x4_i64:316; CHECK: // %bb.0:317; CHECK-NEXT: // kill: def $z3 killed $z3 killed $z0_z1_z2_z3 def $z0_z1_z2_z3318; CHECK-NEXT: mov w8, w0319; CHECK-NEXT: // kill: def $z2 killed $z2 killed $z0_z1_z2_z3 def $z0_z1_z2_z3320; CHECK-NEXT: // kill: def $z1 killed $z1 killed $z0_z1_z2_z3 def $z0_z1_z2_z3321; CHECK-NEXT: // kill: def $z0 killed $z0 killed $z0_z1_z2_z3 def $z0_z1_z2_z3322; CHECK-NEXT: sub za.d[w8, 0, vgx4], { z0.d - z3.d }323; CHECK-NEXT: sub za.d[w8, 7, vgx4], { z0.d - z3.d }324; CHECK-NEXT: ret325 <vscale x 2 x i64> %zn0, <vscale x 2 x i64> %zn1,326 <vscale x 2 x i64> %zn2, <vscale x 2 x i64> %zn3) {327 call void @llvm.aarch64.sme.sub.za64.vg1x4.nxv2i64(i32 %slice,328 <vscale x 2 x i64> %zn0, <vscale x 2 x i64> %zn1,329 <vscale x 2 x i64> %zn2, <vscale x 2 x i64> %zn3)330 %slice.7 = add i32 %slice, 7331 call void @llvm.aarch64.sme.sub.za64.vg1x4.nxv2i64(i32 %slice.7,332 <vscale x 2 x i64> %zn0, <vscale x 2 x i64> %zn1,333 <vscale x 2 x i64> %zn2, <vscale x 2 x i64> %zn3)334 ret void335}336 337define void @multi_vector_sub_za_vg1x4_f32(i32 %slice,338; CHECK-LABEL: multi_vector_sub_za_vg1x4_f32:339; CHECK: // %bb.0:340; CHECK-NEXT: // kill: def $z3 killed $z3 killed $z0_z1_z2_z3 def $z0_z1_z2_z3341; CHECK-NEXT: mov w8, w0342; CHECK-NEXT: // kill: def $z2 killed $z2 killed $z0_z1_z2_z3 def $z0_z1_z2_z3343; CHECK-NEXT: // kill: def $z1 killed $z1 killed $z0_z1_z2_z3 def $z0_z1_z2_z3344; CHECK-NEXT: // kill: def $z0 killed $z0 killed $z0_z1_z2_z3 def $z0_z1_z2_z3345; CHECK-NEXT: fsub za.s[w8, 0, vgx4], { z0.s - z3.s }346; CHECK-NEXT: fsub za.s[w8, 7, vgx4], { z0.s - z3.s }347; CHECK-NEXT: ret348 <vscale x 4 x float> %zn0, <vscale x 4 x float> %zn1,349 <vscale x 4 x float> %zn2, <vscale x 4 x float> %zn3) {350 call void @llvm.aarch64.sme.sub.za32.vg1x4.nxv4f32(i32 %slice,351 <vscale x 4 x float> %zn0, <vscale x 4 x float> %zn1,352 <vscale x 4 x float> %zn2, <vscale x 4 x float> %zn3)353 %slice.7 = add i32 %slice, 7354 call void @llvm.aarch64.sme.sub.za32.vg1x4.nxv4f32(i32 %slice.7,355 <vscale x 4 x float> %zn0, <vscale x 4 x float> %zn1,356 <vscale x 4 x float> %zn2, <vscale x 4 x float> %zn3)357 ret void358}359 360define void @multi_vector_sub_za_vg1x4_f64(i32 %slice,361; CHECK-LABEL: multi_vector_sub_za_vg1x4_f64:362; CHECK: // %bb.0:363; CHECK-NEXT: // kill: def $z3 killed $z3 killed $z0_z1_z2_z3 def $z0_z1_z2_z3364; CHECK-NEXT: mov w8, w0365; CHECK-NEXT: // kill: def $z2 killed $z2 killed $z0_z1_z2_z3 def $z0_z1_z2_z3366; CHECK-NEXT: // kill: def $z1 killed $z1 killed $z0_z1_z2_z3 def $z0_z1_z2_z3367; CHECK-NEXT: // kill: def $z0 killed $z0 killed $z0_z1_z2_z3 def $z0_z1_z2_z3368; CHECK-NEXT: fsub za.d[w8, 0, vgx4], { z0.d - z3.d }369; CHECK-NEXT: fsub za.d[w8, 7, vgx4], { z0.d - z3.d }370; CHECK-NEXT: ret371 <vscale x 2 x double> %zn0, <vscale x 2 x double> %zn1,372 <vscale x 2 x double> %zn2, <vscale x 2 x double> %zn3) {373 call void @llvm.aarch64.sme.sub.za64.vg1x4.nxv2f64(i32 %slice,374 <vscale x 2 x double> %zn0, <vscale x 2 x double> %zn1,375 <vscale x 2 x double> %zn2, <vscale x 2 x double> %zn3)376 %slice.7 = add i32 %slice, 7377 call void @llvm.aarch64.sme.sub.za64.vg1x4.nxv2f64(i32 %slice.7,378 <vscale x 2 x double> %zn0, <vscale x 2 x double> %zn1,379 <vscale x 2 x double> %zn2, <vscale x 2 x double> %zn3)380 ret void381}382 383declare void@llvm.aarch64.sme.sub.write.single.za.vg1x2.nxv4i32(i32, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>)384declare void@llvm.aarch64.sme.sub.write.single.za.vg1x2.nxv2i64(i32, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>)385declare void@llvm.aarch64.sme.sub.write.single.za.vg1x4.nxv4i32(i32, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>,386<vscale x 4 x i32>, <vscale x 4 x i32>)387declare void@llvm.aarch64.sme.sub.write.single.za.vg1x4.nxv2i64(i32, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>,388<vscale x 2 x i64>, <vscale x 2 x i64>)389declare void@llvm.aarch64.sme.sub.write.za.vg1x2.nxv4i32(i32, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>)390declare void@llvm.aarch64.sme.sub.write.za.vg1x2.nxv2i64(i32, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>)391declare void@llvm.aarch64.sme.sub.write.za.vg1x4.nxv4i32(i32, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>)392declare void@llvm.aarch64.sme.sub.write.za.vg1x4.nxv2i64(i32, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>)393declare void@llvm.aarch64.sme.sub.za32.vg1x2.nxv4i32(i32, <vscale x 4 x i32>,<vscale x 4 x i32>)394declare void@llvm.aarch64.sme.sub.za64.vg1x2.nxv2i64(i32, <vscale x 2 x i64>,<vscale x 2 x i64>)395declare void@llvm.aarch64.sme.sub.za32.vg1x4.nxv4i32(i32, <vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>,<vscale x 4 x i32>)396declare void@llvm.aarch64.sme.sub.za64.vg1x4.nxv2i64(i32, <vscale x 2 x i64>,<vscale x 2 x i64>,<vscale x 2 x i64>, <vscale x 2 x i64>)397declare void@llvm.aarch64.sme.sub.za32.vg1x2.nxv4f32(i32, <vscale x 4 x float>, <vscale x 4 x float>)398declare void@llvm.aarch64.sme.sub.za64.vg1x2.nxv2f64(i32, <vscale x 2 x double>, <vscale x 2 x double>)399declare void@llvm.aarch64.sme.sub.za32.vg1x4.nxv4f32(i32, <vscale x 4 x float>, <vscale x 4 x float>,<vscale x 4 x float>, <vscale x 4 x float>)400declare void@llvm.aarch64.sme.sub.za64.vg1x4.nxv2f64(i32, <vscale x 2 x double>, <vscale x 2 x double>,<vscale x 2 x double>, <vscale x 2 x double>)401