163 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -verify-machineinstrs -force-streaming < %s | FileCheck %s3 4target triple = "aarch64-linux"5 6 7define void @test_write_zt_i8_0(<vscale x 16 x i8> %zn) #0 {8; CHECK-LABEL: test_write_zt_i8_0:9; CHECK: // %bb.0:10; CHECK-NEXT: movt zt0, z011; CHECK-NEXT: ret12 call void @llvm.aarch64.sme.write.lane.zt.nxv16i8(i32 0, <vscale x 16 x i8> %zn, i32 0)13 ret void14}15 16define void @test_write_zt_i8_1(<vscale x 16 x i8> %zn) #0 {17; CHECK-LABEL: test_write_zt_i8_1:18; CHECK: // %bb.0:19; CHECK-NEXT: movt zt0[1, mul vl], z020; CHECK-NEXT: ret21 call void @llvm.aarch64.sme.write.lane.zt.nxv16i8(i32 0, <vscale x 16 x i8> %zn, i32 1)22 ret void23}24 25define void @test_write_zt_i16_2(<vscale x 8 x i16> %zn) #0 {26; CHECK-LABEL: test_write_zt_i16_2:27; CHECK: // %bb.0:28; CHECK-NEXT: movt zt0[2, mul vl], z029; CHECK-NEXT: ret30 call void @llvm.aarch64.sme.write.lane.zt.nxv8i16(i32 0, <vscale x 8 x i16> %zn, i32 2)31 ret void32}33 34define void @test_write_zt_i32_3(<vscale x 4 x i32> %zn) #0 {35; CHECK-LABEL: test_write_zt_i32_3:36; CHECK: // %bb.0:37; CHECK-NEXT: movt zt0[3, mul vl], z038; CHECK-NEXT: ret39 call void @llvm.aarch64.sme.write.lane.zt.nxv4i32(i32 0, <vscale x 4 x i32> %zn, i32 3)40 ret void41}42 43define void @test_write_zt_i64_1(<vscale x 2 x i64> %zn) #0 {44; CHECK-LABEL: test_write_zt_i64_1:45; CHECK: // %bb.0:46; CHECK-NEXT: movt zt0[1, mul vl], z047; CHECK-NEXT: ret48 call void @llvm.aarch64.sme.write.lane.zt.nxv2i64(i32 0, <vscale x 2 x i64> %zn, i32 1)49 ret void50}51 52define void @test_write_zt_f16_2(<vscale x 8 x half> %zn) #0 {53; CHECK-LABEL: test_write_zt_f16_2:54; CHECK: // %bb.0:55; CHECK-NEXT: movt zt0[2, mul vl], z056; CHECK-NEXT: ret57 call void @llvm.aarch64.sme.write.lane.zt.nxv8f16(i32 0, <vscale x 8 x half> %zn, i32 2)58 ret void59}60 61define void @test_write_zt_f32_3(<vscale x 4 x float> %zn) #0 {62; CHECK-LABEL: test_write_zt_f32_3:63; CHECK: // %bb.0:64; CHECK-NEXT: movt zt0[3, mul vl], z065; CHECK-NEXT: ret66 call void @llvm.aarch64.sme.write.lane.zt.nxv4f32(i32 0, <vscale x 4 x float> %zn, i32 3)67 ret void68}69 70define void @test_write_zt_f64_1(<vscale x 2 x double> %zn) #0 {71; CHECK-LABEL: test_write_zt_f64_1:72; CHECK: // %bb.0:73; CHECK-NEXT: movt zt0[1, mul vl], z074; CHECK-NEXT: ret75 call void @llvm.aarch64.sme.write.lane.zt.nxv2f64(i32 0, <vscale x 2 x double> %zn, i32 1)76 ret void77}78 79define void @test_write_zt_bf16_2(<vscale x 8 x bfloat> %zn) #0 {80; CHECK-LABEL: test_write_zt_bf16_2:81; CHECK: // %bb.0:82; CHECK-NEXT: movt zt0[2, mul vl], z083; CHECK-NEXT: ret84 call void @llvm.aarch64.sme.write.lane.zt.nxv8bf16(i32 0, <vscale x 8 x bfloat> %zn, i32 2)85 ret void86}87 88;; ALIAS89 90define void @test_write_zt_i8(<vscale x 16 x i8> %v) #0 {91; CHECK-LABEL: test_write_zt_i8:92; CHECK: // %bb.0:93; CHECK-NEXT: movt zt0, z094; CHECK-NEXT: ret95 tail call void @llvm.aarch64.sme.write.zt.nxv16i8(i32 0, <vscale x 16 x i8> %v)96 ret void97}98 99define void @test_write_zt_i16(<vscale x 8 x i16> %v) #0 {100; CHECK-LABEL: test_write_zt_i16:101; CHECK: // %bb.0:102; CHECK-NEXT: movt zt0, z0103; CHECK-NEXT: ret104 tail call void @llvm.aarch64.sme.write.zt.nxv8i16(i32 0, <vscale x 8 x i16> %v)105 ret void106}107 108define void @test_write_zt_i32(<vscale x 4 x i32> %v) #0 {109; CHECK-LABEL: test_write_zt_i32:110; CHECK: // %bb.0:111; CHECK-NEXT: movt zt0, z0112; CHECK-NEXT: ret113 tail call void @llvm.aarch64.sme.write.zt.nxv4i32(i32 0, <vscale x 4 x i32> %v)114 ret void115}116 117define void @test_write_zt_i64(<vscale x 2 x i64> %v) #0 {118; CHECK-LABEL: test_write_zt_i64:119; CHECK: // %bb.0:120; CHECK-NEXT: movt zt0, z0121; CHECK-NEXT: ret122 tail call void @llvm.aarch64.sme.write.zt.nxv2i64(i32 0, <vscale x 2 x i64> %v)123 ret void124}125 126define void @test_write_zt_f16(<vscale x 8 x half> %v) #0 {127; CHECK-LABEL: test_write_zt_f16:128; CHECK: // %bb.0:129; CHECK-NEXT: movt zt0, z0130; CHECK-NEXT: ret131 tail call void @llvm.aarch64.sme.write.zt.nxv8f16(i32 0, <vscale x 8 x half> %v)132 ret void133}134 135define void @test_write_zt_bf16(<vscale x 8 x bfloat> %v) #0 {136; CHECK-LABEL: test_write_zt_bf16:137; CHECK: // %bb.0:138; CHECK-NEXT: movt zt0, z0139; CHECK-NEXT: ret140 tail call void @llvm.aarch64.sme.write.zt.nxv8bf16(i32 0, <vscale x 8 x bfloat> %v)141 ret void142}143 144define void @test_write_zt_f32(<vscale x 4 x float> %v) #0 {145; CHECK-LABEL: test_write_zt_f32:146; CHECK: // %bb.0:147; CHECK-NEXT: movt zt0, z0148; CHECK-NEXT: ret149 tail call void @llvm.aarch64.sme.write.zt.nxv4f32(i32 0, <vscale x 4 x float> %v)150 ret void151}152 153define void @test_write_zt_f64(<vscale x 2 x double> %v) #0 {154; CHECK-LABEL: test_write_zt_f64:155; CHECK: // %bb.0:156; CHECK-NEXT: movt zt0, z0157; CHECK-NEXT: ret158 tail call void @llvm.aarch64.sme.write.zt.nxv2f64(i32 0, <vscale x 2 x double> %v)159 ret void160}161 162attributes #0 = { "target-features"="+sme2,+sme-lutv2" }163