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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 42; RUN: llc -verify-machineinstrs -force-streaming < %s | FileCheck %s3 4target triple = "aarch64-linux"5 6define void @test_svzero_za64_vg1x2(i32 %slice) #0 {7; CHECK-LABEL: test_svzero_za64_vg1x2:8; CHECK: // %bb.0: // %entry9; CHECK-NEXT: mov w8, w010; CHECK-NEXT: zero za.d[w8, 0, vgx2]11; CHECK-NEXT: ret12entry:13 tail call void @llvm.aarch64.sme.zero.za64.vg1x2(i32 %slice)14 ret void15}16 17define void @test_svzero_za64_vg1x2_offset(i32 %slice) #0 {18; CHECK-LABEL: test_svzero_za64_vg1x2_offset:19; CHECK: // %bb.0: // %entry20; CHECK-NEXT: mov w8, w021; CHECK-NEXT: zero za.d[w8, 7, vgx2]22; CHECK-NEXT: ret23entry:24 %slice.max = add i32 %slice, 725 tail call void @llvm.aarch64.sme.zero.za64.vg1x2(i32 %slice.max)26 ret void27}28 29define void @test_svzero_za64_vg1x4(i32 %slice) #0 {30; CHECK-LABEL: test_svzero_za64_vg1x4:31; CHECK: // %bb.0: // %entry32; CHECK-NEXT: mov w8, w033; CHECK-NEXT: zero za.d[w8, 0, vgx4]34; CHECK-NEXT: ret35entry:36 tail call void @llvm.aarch64.sme.zero.za64.vg1x4(i32 %slice)37 ret void38}39 40define void @test_svzero_za64_vg1x4_offset(i32 %slice) #0 {41; CHECK-LABEL: test_svzero_za64_vg1x4_offset:42; CHECK: // %bb.0: // %entry43; CHECK-NEXT: mov w8, w044; CHECK-NEXT: zero za.d[w8, 1, vgx4]45; CHECK-NEXT: ret46entry:47 %slice.min = add i32 %slice, 148 tail call void @llvm.aarch64.sme.zero.za64.vg1x4(i32 %slice.min)49 ret void50}51 52define void @test_svzero_za64_vg2x1(i32 %slice) #0 {53; CHECK-LABEL: test_svzero_za64_vg2x1:54; CHECK: // %bb.0: // %entry55; CHECK-NEXT: mov w8, w056; CHECK-NEXT: zero za.d[w8, 0:1]57; CHECK-NEXT: ret58entry:59 tail call void @llvm.aarch64.sme.zero.za64.vg2x1(i32 %slice)60 ret void61}62 63define void @test_svzero_za64_vg2x1_offset(i32 %slice) #0 {64; CHECK-LABEL: test_svzero_za64_vg2x1_offset:65; CHECK: // %bb.0: // %entry66; CHECK-NEXT: mov w8, w067; CHECK-NEXT: zero za.d[w8, 6:7]68; CHECK-NEXT: ret69entry:70 %slice.max = add i32 %slice, 671 tail call void @llvm.aarch64.sme.zero.za64.vg2x1(i32 %slice.max)72 ret void73}74 75define void @test_svzero_za64_vg2x2(i32 %slice) #0 {76; CHECK-LABEL: test_svzero_za64_vg2x2:77; CHECK: // %bb.0: // %entry78; CHECK-NEXT: mov w8, w079; CHECK-NEXT: zero za.d[w8, 0:1, vgx2]80; CHECK-NEXT: ret81entry:82 tail call void @llvm.aarch64.sme.zero.za64.vg2x2(i32 %slice)83 ret void84}85 86define void @test_svzero_za64_vg2x2_offset(i32 %slice) #0 {87; CHECK-LABEL: test_svzero_za64_vg2x2_offset:88; CHECK: // %bb.0: // %entry89; CHECK-NEXT: mov w8, w090; CHECK-NEXT: zero za.d[w8, 2:3, vgx2]91; CHECK-NEXT: ret92entry:93 %slice.max = add i32 %slice, 294 tail call void @llvm.aarch64.sme.zero.za64.vg2x2(i32 %slice.max)95 ret void96}97 98define void @test_svzero_za64_vg2x4(i32 %slice) #0 {99; CHECK-LABEL: test_svzero_za64_vg2x4:100; CHECK: // %bb.0: // %entry101; CHECK-NEXT: mov w8, w0102; CHECK-NEXT: zero za.d[w8, 0:1, vgx4]103; CHECK-NEXT: ret104entry:105 tail call void @llvm.aarch64.sme.zero.za64.vg2x4(i32 %slice)106 ret void107}108 109define void @test_svzero_za64_vg2x4_offset(i32 %slice) #0 {110; CHECK-LABEL: test_svzero_za64_vg2x4_offset:111; CHECK: // %bb.0: // %entry112; CHECK-NEXT: add w8, w0, #1113; CHECK-NEXT: zero za.d[w8, 0:1, vgx4]114; CHECK-NEXT: ret115entry:116 %slice.min = add i32 %slice, 1117 tail call void @llvm.aarch64.sme.zero.za64.vg2x4(i32 %slice.min)118 ret void119}120 121define void @test_svzero_za64_vg4x1(i32 %slice) #0 {122; CHECK-LABEL: test_svzero_za64_vg4x1:123; CHECK: // %bb.0: // %entry124; CHECK-NEXT: mov w8, w0125; CHECK-NEXT: zero za.d[w8, 0:3]126; CHECK-NEXT: ret127entry:128 tail call void @llvm.aarch64.sme.zero.za64.vg4x1(i32 %slice)129 ret void130}131 132define void @test_svzero_za64_vg4x1_offset(i32 %slice) #0 {133; CHECK-LABEL: test_svzero_za64_vg4x1_offset:134; CHECK: // %bb.0: // %entry135; CHECK-NEXT: mov w8, w0136; CHECK-NEXT: zero za.d[w8, 4:7]137; CHECK-NEXT: ret138entry:139 %slice.max = add i32 %slice, 4140 tail call void @llvm.aarch64.sme.zero.za64.vg4x1(i32 %slice.max)141 ret void142}143 144define void @test_svzero_za64_vg4x2(i32 %slice) #0 {145; CHECK-LABEL: test_svzero_za64_vg4x2:146; CHECK: // %bb.0: // %entry147; CHECK-NEXT: mov w8, w0148; CHECK-NEXT: zero za.d[w8, 0:3, vgx2]149; CHECK-NEXT: ret150entry:151 tail call void @llvm.aarch64.sme.zero.za64.vg4x2(i32 %slice)152 ret void153}154 155define void @test_svzero_za64_vg4x2_offset(i32 %slice) #0 {156; CHECK-LABEL: test_svzero_za64_vg4x2_offset:157; CHECK: // %bb.0: // %entry158; CHECK-NEXT: mov w8, w0159; CHECK-NEXT: zero za.d[w8, 0:3, vgx2]160; CHECK-NEXT: ret161entry:162 %slice.max = add i32 %slice, 0163 tail call void @llvm.aarch64.sme.zero.za64.vg4x2(i32 %slice.max)164 ret void165}166 167define void @test_svzero_za64_vg4x4(i32 %slice) #0 {168; CHECK-LABEL: test_svzero_za64_vg4x4:169; CHECK: // %bb.0: // %entry170; CHECK-NEXT: mov w8, w0171; CHECK-NEXT: zero za.d[w8, 0:3, vgx4]172; CHECK-NEXT: ret173entry:174 tail call void @llvm.aarch64.sme.zero.za64.vg4x4(i32 %slice)175 ret void176}177 178define void @test_svzero_za64_vg4x4_offset(i32 %slice) #0 {179; CHECK-LABEL: test_svzero_za64_vg4x4_offset:180; CHECK: // %bb.0: // %entry181; CHECK-NEXT: add w8, w0, #1182; CHECK-NEXT: zero za.d[w8, 0:3, vgx4]183; CHECK-NEXT: ret184entry:185 %slice.min = add i32 %slice, 1186 tail call void @llvm.aarch64.sme.zero.za64.vg4x4(i32 %slice.min)187 ret void188}189 190attributes #0 = { nounwind "target-features" = "+sme2p1"}191