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1# RUN: llc -mtriple=aarch64 -run-pass=pipeliner -debug-only=pipeliner -aarch64-enable-pipeliner -pipeliner-mve-cg %s -o /dev/null 2>&1 | FileCheck %s2# REQUIRES: asserts3 4# Test a case where fenv is enabled, there are instructions that may raise a5# floating-point exception, and there is an instruction for barrier event. In6# this case the order of them must not change.7#8# FIXME: Currently the following dependencies are missed.9#10# Loop carried edges from SU(7)11# Order12# SU(2)13# SU(3)14# SU(4)15# SU(5)16 17# CHECK: ===== Loop Carried Edges Begin =====18# CHECK-NEXT: ===== Loop Carried Edges End =====19 20--- |21 @x = dso_local global i32 0, align 422 23 define dso_local void @f(ptr nocapture noundef writeonly %a, float noundef %y, i32 noundef %n) {24 entry:25 %cmp6 = icmp sgt i32 %n, 026 br i1 %cmp6, label %for.body.preheader, label %for.cond.cleanup27 28 for.body.preheader:29 %wide.trip.count = zext nneg i32 %n to i6430 br label %for.body31 32 for.cond.cleanup:33 ret void34 35 for.body:36 %indvars.iv = phi i64 [ 0, %for.body.preheader ], [ %indvars.iv.next, %for.body ]37 %tmp9 = trunc i64 %indvars.iv to i3238 %conv = tail call float @llvm.experimental.constrained.sitofp.f32.i32(i32 %tmp9, metadata !"round.dynamic", metadata !"fpexcept.strict") #239 %add = tail call float @llvm.experimental.constrained.fadd.f32(float %conv, float %y, metadata !"round.dynamic", metadata !"fpexcept.strict") #240 %0 = shl nuw nsw i64 %indvars.iv, 241 %scevgep = getelementptr i8, ptr %a, i64 %042 store float %add, ptr %scevgep, align 4, !tbaa !643 %1 = load volatile i32, ptr @x, align 4, !tbaa !1044 %2 = zext i32 %1 to i6445 %3 = add i64 %indvars.iv, %246 %tmp = trunc i64 %3 to i3247 store volatile i32 %tmp, ptr @x, align 4, !tbaa !1048 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 149 %exitcond.not = icmp eq i64 %wide.trip.count, %indvars.iv.next50 br i1 %exitcond.not, label %for.cond.cleanup, label %for.body51 }52 53 declare float @llvm.experimental.constrained.sitofp.f32.i32(i32, metadata, metadata)54 55 declare float @llvm.experimental.constrained.fadd.f32(float, float, metadata, metadata)56 57 attributes #2 = { strictfp }58 59 !6 = !{!7, !7, i64 0}60 !7 = !{!"float", !8, i64 0}61 !8 = !{!"omnipotent char", !9, i64 0}62 !9 = !{!"Simple C/C++ TBAA"}63 !10 = !{!11, !11, i64 0}64 !11 = !{!"int", !8, i64 0}65 66...67---68name: f69tracksRegLiveness: true70body: |71 bb.0.entry:72 successors: %bb.1, %bb.273 liveins: $x0, $s0, $w174 75 %5:gpr32common = COPY $w176 %4:fpr32 = COPY $s077 %3:gpr64common = COPY $x078 dead $wzr = SUBSWri %5, 1, 0, implicit-def $nzcv79 Bcc 11, %bb.2, implicit $nzcv80 B %bb.181 82 bb.1.for.body.preheader:83 %8:gpr32 = ORRWrs $wzr, %5, 084 %0:gpr64 = SUBREG_TO_REG 0, killed %8, %subreg.sub_3285 %9:gpr64all = COPY $xzr86 %7:gpr64all = COPY %987 %13:gpr64common = ADRP target-flags(aarch64-page) @x88 B %bb.389 90 bb.2.for.cond.cleanup:91 RET_ReallyLR92 93 bb.3.for.body:94 successors: %bb.2, %bb.395 96 %1:gpr64common = PHI %7, %bb.1, %2, %bb.397 %10:gpr32 = COPY %1.sub_3298 %11:fpr32 = SCVTFUWSri %10, implicit $fpcr99 %12:fpr32 = FADDSrr killed %11, %4, implicit $fpcr100 STRSroX killed %12, %3, %1, 0, 1 :: (store (s32) into %ir.scevgep, !tbaa !6)101 %14:gpr32 = LDRWui %13, target-flags(aarch64-pageoff, aarch64-nc) @x :: (volatile dereferenceable load (s32) from @x, !tbaa !10)102 %15:gpr32 = ADDWrr %10, killed %14103 STRWui killed %15, %13, target-flags(aarch64-pageoff, aarch64-nc) @x :: (volatile store (s32) into @x, !tbaa !10)104 %16:gpr64common = nuw nsw ADDXri %1, 1, 0105 %2:gpr64all = COPY %16106 dead $xzr = SUBSXrr %0, %16, implicit-def $nzcv107 Bcc 0, %bb.2, implicit $nzcv108 B %bb.3109...110