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1# RUN: llc -mtriple=aarch64 -run-pass=pipeliner -debug-only=pipeliner -aarch64-enable-pipeliner -pipeliner-mve-cg %s -o /dev/null 2>&1 | FileCheck %s2# REQUIRES: asserts3 4# Test a case where fenv is enabled, there are instructions that may raise a5# floatin-point exception, but there is no instruction for barrier event. In6# this case no loop-carried dependencies are necessary.7 8# CHECK: ===== Loop Carried Edges Begin =====9# CHECK-NEXT: ===== Loop Carried Edges End =====10 11--- |12 define dso_local float @f(ptr nocapture noundef writeonly %a, float noundef %y, i32 noundef %n) local_unnamed_addr {13 entry:14 %conv = tail call float @llvm.experimental.constrained.fptrunc.f32.f64(double 1.000000e+00, metadata !"round.dynamic", metadata !"fpexcept.strict")15 %cmp8 = icmp sgt i32 %n, 016 br i1 %cmp8, label %for.body.preheader, label %for.cond.cleanup17 18 for.body.preheader:19 %wide.trip.count = zext nneg i32 %n to i6420 br label %for.body21 22 for.cond.cleanup:23 %acc.0.lcssa = phi float [ %conv, %entry ], [ %mul, %for.body ]24 ret float %acc.0.lcssa25 26 for.body:27 %indvars.iv = phi i64 [ 0, %for.body.preheader ], [ %indvars.iv.next, %for.body ]28 %acc.010 = phi float [ %conv, %for.body.preheader ], [ %mul, %for.body ]29 %tmp = trunc i64 %indvars.iv to i3230 %conv2 = tail call float @llvm.experimental.constrained.sitofp.f32.i32(i32 %tmp, metadata !"round.dynamic", metadata !"fpexcept.strict")31 %add = tail call float @llvm.experimental.constrained.fadd.f32(float %conv2, float %y, metadata !"round.dynamic", metadata !"fpexcept.strict")32 %mul = tail call float @llvm.experimental.constrained.fmul.f32(float %acc.010, float %add, metadata !"round.dynamic", metadata !"fpexcept.strict")33 %0 = shl nuw nsw i64 %indvars.iv, 234 %scevgep = getelementptr i8, ptr %a, i64 %035 store float %add, ptr %scevgep, align 4, !tbaa !636 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 137 %exitcond.not = icmp eq i64 %wide.trip.count, %indvars.iv.next38 br i1 %exitcond.not, label %for.cond.cleanup, label %for.body39 }40 41 declare float @llvm.experimental.constrained.fptrunc.f32.f64(double, metadata, metadata)42 43 declare float @llvm.experimental.constrained.sitofp.f32.i32(i32, metadata, metadata)44 45 declare float @llvm.experimental.constrained.fadd.f32(float, float, metadata, metadata)46 47 declare float @llvm.experimental.constrained.fmul.f32(float, float, metadata, metadata)48 49 !6 = !{!7, !7, i64 0}50 !7 = !{!"float", !8, i64 0}51 !8 = !{!"omnipotent char", !9, i64 0}52 !9 = !{!"Simple C/C++ TBAA"}53 54...55---56name: f57tracksRegLiveness: true58body: |59 bb.0.entry:60 successors: %bb.1, %bb.261 liveins: $x0, $s0, $w162 63 %9:gpr32common = COPY $w164 %8:fpr32 = COPY $s065 %7:gpr64common = COPY $x066 %10:fpr64 = FMOVDi 11267 %0:fpr32 = FCVTSDr killed %10, implicit $fpcr68 dead $wzr = SUBSWri %9, 1, 0, implicit-def $nzcv69 Bcc 11, %bb.2, implicit $nzcv70 B %bb.171 72 bb.1.for.body.preheader:73 %13:gpr32 = ORRWrs $wzr, %9, 074 %1:gpr64 = SUBREG_TO_REG 0, killed %13, %subreg.sub_3275 %14:gpr64all = COPY $xzr76 %12:gpr64all = COPY %1477 B %bb.378 79 bb.2.for.cond.cleanup:80 %2:fpr32 = PHI %0, %bb.0, %5, %bb.381 $s0 = COPY %282 RET_ReallyLR implicit $s083 84 bb.3.for.body:85 successors: %bb.2, %bb.386 87 %3:gpr64common = PHI %12, %bb.1, %6, %bb.388 %4:fpr32 = PHI %0, %bb.1, %5, %bb.389 %15:gpr32 = COPY %3.sub_3290 %16:fpr32 = SCVTFUWSri killed %15, implicit $fpcr91 %17:fpr32 = FADDSrr killed %16, %8, implicit $fpcr92 %5:fpr32 = FMULSrr %4, %17, implicit $fpcr93 STRSroX %17, %7, %3, 0, 1 :: (store (s32) into %ir.scevgep, !tbaa !6)94 %18:gpr64common = nuw nsw ADDXri %3, 1, 095 %6:gpr64all = COPY %1896 dead $xzr = SUBSXrr %1, %18, implicit-def $nzcv97 Bcc 0, %bb.2, implicit $nzcv98 B %bb.399...100