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1# RUN: llc --verify-machineinstrs -mtriple=aarch64 -o - %s -run-pass pipeliner -aarch64-enable-pipeliner -pipeliner-max-mii=40 -pipeliner-register-pressure -pipeliner-ii-search-range=30 -debug-only=pipeliner 2>&1 | FileCheck %s2 3# REQUIRES: asserts4 5# Check that if the register pressure is too high, the schedule is rejected, II is incremented, and scheduling continues.6# The specific value of II is not important.7 8# CHECK: {{^ *}}Try to schedule with {{[0-9]+$}}9# CHECK: {{^ *}}Rejected the schedule because of too high register pressure{{$}}10# CHECK: {{^ *}}Try to schedule with {{[0-9]+$}}11# CHECK: {{^ *}}Schedule Found? 1 (II={{[0-9]+}}){{$}}12 13--- |14 target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"15 16 define dso_local double @kernel(ptr nocapture noundef readonly %a, ptr nocapture noundef readonly %b, i32 noundef %n) local_unnamed_addr {17 entry:18 %0 = load double, ptr %a, align 819 %arrayidx1 = getelementptr inbounds i8, ptr %a, i64 820 %1 = load double, ptr %arrayidx1, align 821 %cmp133 = icmp sgt i32 %n, 022 br i1 %cmp133, label %for.body.preheader, label %for.cond.cleanup23 24 for.body.preheader: ; preds = %entry25 %wide.trip.count = zext nneg i32 %n to i6426 br label %for.body27 28 for.cond.cleanup: ; preds = %for.body, %entry29 %res.0.lcssa = phi double [ 0.000000e+00, %entry ], [ %add54, %for.body ]30 ret double %res.0.lcssa31 32 for.body: ; preds = %for.body.preheader, %for.body33 %lsr.iv137 = phi i64 [ %wide.trip.count, %for.body.preheader ], [ %lsr.iv.next, %for.body ]34 %lsr.iv = phi ptr [ %b, %for.body.preheader ], [ %scevgep, %for.body ]35 %res.0135 = phi double [ 0.000000e+00, %for.body.preheader ], [ %add54, %for.body ]36 %2 = load double, ptr %lsr.iv, align 837 %3 = tail call double @llvm.fmuladd.f64(double %0, double %2, double %0)38 %4 = tail call double @llvm.fmuladd.f64(double %3, double %2, double %3)39 %5 = tail call double @llvm.fmuladd.f64(double %4, double %2, double %4)40 %6 = tail call double @llvm.fmuladd.f64(double %5, double %2, double %5)41 %7 = tail call double @llvm.fmuladd.f64(double %6, double %2, double %6)42 %8 = tail call double @llvm.fmuladd.f64(double %7, double %2, double %7)43 %9 = tail call double @llvm.fmuladd.f64(double %8, double %2, double %8)44 %10 = tail call double @llvm.fmuladd.f64(double %9, double %2, double %9)45 %11 = tail call double @llvm.fmuladd.f64(double %10, double %2, double %10)46 %12 = tail call double @llvm.fmuladd.f64(double %11, double %2, double %11)47 %13 = tail call double @llvm.fmuladd.f64(double %12, double %2, double %12)48 %14 = tail call double @llvm.fmuladd.f64(double %13, double %2, double %13)49 %15 = tail call double @llvm.fmuladd.f64(double %14, double %2, double %14)50 %16 = tail call double @llvm.fmuladd.f64(double %15, double %2, double %15)51 %17 = tail call double @llvm.fmuladd.f64(double %16, double %2, double %16)52 %18 = tail call double @llvm.fmuladd.f64(double %17, double %2, double %17)53 %add = fadd double %17, %1854 %19 = tail call double @llvm.fmuladd.f64(double %18, double %2, double %add)55 %add35 = fadd double %10, %1956 %20 = tail call double @llvm.fmuladd.f64(double %3, double %2, double %add35)57 %add38 = fadd double %11, %2058 %21 = tail call double @llvm.fmuladd.f64(double %4, double %2, double %add38)59 %add41 = fadd double %12, %2160 %22 = tail call double @llvm.fmuladd.f64(double %5, double %2, double %add41)61 %add44 = fadd double %14, %1562 %add45 = fadd double %13, %add4463 %add46 = fadd double %add45, %2264 %23 = tail call double @llvm.fmuladd.f64(double %6, double %2, double %add46)65 %mul = fmul double %2, %766 %mul51 = fmul double %1, %mul67 %24 = tail call double @llvm.fmuladd.f64(double %mul51, double %9, double %23)68 %25 = tail call double @llvm.fmuladd.f64(double %8, double %1, double %24)69 %add54 = fadd double %res.0135, %2570 %scevgep = getelementptr i8, ptr %lsr.iv, i64 871 %lsr.iv.next = add nsw i64 %lsr.iv137, -172 %exitcond.not = icmp eq i64 %lsr.iv.next, 073 br i1 %exitcond.not, label %for.cond.cleanup, label %for.body74 }75 76 declare double @llvm.fmuladd.f64(double, double, double)77 78...79---80name: kernel81tracksRegLiveness: true82liveins:83 - { reg: '$x0', virtual-reg: '%10' }84 - { reg: '$x1', virtual-reg: '%11' }85 - { reg: '$w2', virtual-reg: '%12' }86body: |87 bb.0.entry:88 successors: %bb.1, %bb.489 liveins: $x0, $x1, $w290 91 %12:gpr32common = COPY $w292 %11:gpr64 = COPY $x193 %10:gpr64common = COPY $x094 dead $wzr = SUBSWri %12, 1, 0, implicit-def $nzcv95 Bcc 10, %bb.1, implicit $nzcv96 97 bb.4:98 %13:fpr64 = FMOVD099 B %bb.2100 101 bb.1.for.body.preheader:102 %0:fpr64 = LDRDui %10, 0 :: (load (s64) from %ir.a)103 %1:fpr64 = LDRDui %10, 1 :: (load (s64) from %ir.arrayidx1)104 %16:gpr32 = ORRWrs $wzr, %12, 0105 %2:gpr64all = SUBREG_TO_REG 0, killed %16, %subreg.sub_32106 %15:fpr64 = FMOVD0107 B %bb.3108 109 bb.2.for.cond.cleanup:110 %3:fpr64 = PHI %13, %bb.4, %7, %bb.3111 $d0 = COPY %3112 RET_ReallyLR implicit $d0113 114 bb.3.for.body:115 successors: %bb.2, %bb.3116 117 %4:gpr64sp = PHI %2, %bb.1, %9, %bb.3118 %5:gpr64sp = PHI %11, %bb.1, %8, %bb.3119 %6:fpr64 = PHI %15, %bb.1, %7, %bb.3120 early-clobber %17:gpr64sp, %18:fpr64 = LDRDpost %5, 8 :: (load (s64) from %ir.lsr.iv)121 %19:fpr64 = nofpexcept FMADDDrrr %0, %18, %0, implicit $fpcr122 %20:fpr64 = nofpexcept FMADDDrrr %19, %18, %19, implicit $fpcr123 %21:fpr64 = nofpexcept FMADDDrrr %20, %18, %20, implicit $fpcr124 %22:fpr64 = nofpexcept FMADDDrrr %21, %18, %21, implicit $fpcr125 %23:fpr64 = nofpexcept FMADDDrrr %22, %18, %22, implicit $fpcr126 %24:fpr64 = nofpexcept FMADDDrrr %23, %18, %23, implicit $fpcr127 %25:fpr64 = nofpexcept FMADDDrrr %24, %18, %24, implicit $fpcr128 %26:fpr64 = nofpexcept FMADDDrrr %25, %18, %25, implicit $fpcr129 %27:fpr64 = nofpexcept FMADDDrrr %26, %18, %26, implicit $fpcr130 %28:fpr64 = nofpexcept FMADDDrrr %27, %18, %27, implicit $fpcr131 %29:fpr64 = nofpexcept FMADDDrrr %28, %18, %28, implicit $fpcr132 %30:fpr64 = nofpexcept FMADDDrrr %29, %18, %29, implicit $fpcr133 %31:fpr64 = nofpexcept FMADDDrrr %30, %18, %30, implicit $fpcr134 %32:fpr64 = nofpexcept FMADDDrrr %31, %18, %31, implicit $fpcr135 %33:fpr64 = nofpexcept FMADDDrrr %32, %18, %32, implicit $fpcr136 %34:fpr64 = nofpexcept FMADDDrrr %33, %18, %33, implicit $fpcr137 %35:fpr64 = nofpexcept FADDDrr %33, %34, implicit $fpcr138 %36:fpr64 = nofpexcept FMADDDrrr %34, %18, killed %35, implicit $fpcr139 %37:fpr64 = nofpexcept FADDDrr %26, killed %36, implicit $fpcr140 %38:fpr64 = nofpexcept FMADDDrrr %19, %18, killed %37, implicit $fpcr141 %39:fpr64 = nofpexcept FADDDrr %27, killed %38, implicit $fpcr142 %40:fpr64 = nofpexcept FMADDDrrr %20, %18, killed %39, implicit $fpcr143 %41:fpr64 = nofpexcept FADDDrr %28, killed %40, implicit $fpcr144 %42:fpr64 = nofpexcept FMADDDrrr %21, %18, killed %41, implicit $fpcr145 %43:fpr64 = nofpexcept FADDDrr %30, %31, implicit $fpcr146 %44:fpr64 = nofpexcept FADDDrr %29, killed %43, implicit $fpcr147 %45:fpr64 = nofpexcept FADDDrr killed %44, killed %42, implicit $fpcr148 %46:fpr64 = nofpexcept FMADDDrrr %22, %18, killed %45, implicit $fpcr149 %47:fpr64 = nofpexcept FMULDrr %18, %23, implicit $fpcr150 %48:fpr64 = nofpexcept FMULDrr %1, killed %47, implicit $fpcr151 %49:fpr64 = nofpexcept FMADDDrrr killed %48, %25, killed %46, implicit $fpcr152 %50:fpr64 = nofpexcept FMADDDrrr %24, %1, killed %49, implicit $fpcr153 %7:fpr64 = nofpexcept FADDDrr %6, killed %50, implicit $fpcr154 %8:gpr64all = COPY %17155 %51:gpr64 = nsw SUBSXri %4, 1, 0, implicit-def $nzcv156 %9:gpr64all = COPY %51157 Bcc 0, %bb.2, implicit $nzcv158 B %bb.3159 160...161