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1# RUN: llc --verify-machineinstrs -mtriple=aarch64 -run-pass=pipeliner -o - %s -aarch64-enable-pipeliner -pipeliner-enable-copytophi=12 3--- |4 target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"5 6 @glb = internal unnamed_addr global { [256 x i32], [256 x i32], [256 x i32] } zeroinitializer7 8 ; Function Attrs: nounwind vscale_range(1,16)9 define internal void @f(i32 %0, i32 %1) #0 {10 entry:11 %reass.sub = sub i32 %1, %012 %invariant.op = add i32 %0, 113 %invariant.op3 = add i32 %0, 214 %omp_loop.cmp5.not = icmp eq i32 %reass.sub, -115 br i1 %omp_loop.cmp5.not, label %exit, label %preheader16 17 preheader: ; preds = %entry18 %2 = add i32 %1, 119 %3 = icmp slt i32 %2, %invariant.op20 br i1 %3, label %body.preheader, label %vector.ph21 22 body.preheader: ; preds = %preheader23 %4 = add i32 %1, 124 %5 = sub i32 %4, %025 br label %body26 27 vector.ph: ; preds = %preheader28 %6 = add i32 %1, 129 %7 = sub i32 %6, %030 %8 = tail call i32 @llvm.vscale.i32()31 %9 = shl nuw nsw i32 %8, 232 %10 = tail call i32 @llvm.vscale.i32()33 %11 = shl nuw nsw i32 %10, 234 %12 = call i32 @llvm.usub.sat.i32(i32 %7, i32 %11)35 %active.lane.mask.entry = call <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i32(i32 0, i32 %7)36 %13 = tail call <vscale x 4 x i32> @llvm.stepvector.nxv4i32()37 %.splatinsert = insertelement <vscale x 4 x i32> poison, i32 %9, i64 038 %.splat = shufflevector <vscale x 4 x i32> %.splatinsert, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer39 %broadcast.splatinsert = insertelement <vscale x 4 x i32> poison, i32 %invariant.op, i64 040 %broadcast.splat = shufflevector <vscale x 4 x i32> %broadcast.splatinsert, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer41 %broadcast.splatinsert7 = insertelement <vscale x 4 x i32> poison, i32 %invariant.op3, i64 042 %broadcast.splat8 = shufflevector <vscale x 4 x i32> %broadcast.splatinsert7, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer43 br label %vector.body44 45 vector.body: ; preds = %vector.body, %vector.ph46 %index = phi i32 [ 0, %vector.ph ], [ %index.next, %vector.body ]47 %active.lane.mask = phi <vscale x 4 x i1> [ %active.lane.mask.entry, %vector.ph ], [ %active.lane.mask.next, %vector.body ]48 %vec.ind = phi <vscale x 4 x i32> [ %13, %vector.ph ], [ %vec.ind.next, %vector.body ]49 %14 = add <vscale x 4 x i32> %vec.ind, %broadcast.splat50 %15 = extractelement <vscale x 4 x i32> %14, i64 051 %16 = sext i32 %15 to i6452 %17 = add nsw i64 %16, -153 %18 = getelementptr i32, ptr @glb, i64 %1754 call void @llvm.masked.store.nxv4i32.p0(<vscale x 4 x i32> %14, ptr %18, i32 4, <vscale x 4 x i1> %active.lane.mask)55 %19 = add <vscale x 4 x i32> %vec.ind, %broadcast.splat856 %20 = mul <vscale x 4 x i32> %14, %1957 %21 = sdiv <vscale x 4 x i32> %20, splat (i32 2)58 %22 = getelementptr i32, ptr getelementptr inbounds nuw (i8, ptr @glb, i64 1024), i64 %1759 call void @llvm.masked.store.nxv4i32.p0(<vscale x 4 x i32> %21, ptr %22, i32 4, <vscale x 4 x i1> %active.lane.mask)60 %23 = getelementptr i32, ptr getelementptr inbounds nuw (i8, ptr @glb, i64 2048), i64 %1761 %wide.masked.load = call <vscale x 4 x i32> @llvm.masked.load.nxv4i32.p0(ptr %23, i32 4, <vscale x 4 x i1> %active.lane.mask, <vscale x 4 x i32> poison)62 %24 = add <vscale x 4 x i32> %wide.masked.load, %2163 call void @llvm.masked.store.nxv4i32.p0(<vscale x 4 x i32> %24, ptr %23, i32 4, <vscale x 4 x i1> %active.lane.mask)64 %25 = tail call i32 @llvm.vscale.i32()65 %26 = shl nuw nsw i32 %25, 266 %index.next = add i32 %index, %2667 %active.lane.mask.next = call <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i32(i32 %index, i32 %12)68 %vec.ind.next = add <vscale x 4 x i32> %vec.ind, %.splat69 %27 = extractelement <vscale x 4 x i1> %active.lane.mask.next, i64 070 br i1 %27, label %vector.body, label %exit71 72 exit: ; preds = %vector.body, %body, %entry73 ret void74 75 body: ; preds = %body.preheader, %body76 %lsr.iv2 = phi i32 [ %invariant.op3, %body.preheader ], [ %lsr.iv.next3, %body ]77 %lsr.iv = phi i32 [ %5, %body.preheader ], [ %lsr.iv.next, %body ]78 %28 = add i32 %lsr.iv2, -179 %29 = sext i32 %28 to i6480 %30 = add nsw i64 %29, -181 %31 = getelementptr i32, ptr @glb, i64 %3082 store i32 %28, ptr %31, align 483 %32 = mul i32 %28, %lsr.iv284 %33 = sdiv i32 %32, 285 %34 = getelementptr i32, ptr getelementptr inbounds nuw (i8, ptr @glb, i64 1024), i64 %3086 store i32 %33, ptr %34, align 487 %35 = getelementptr i32, ptr getelementptr inbounds nuw (i8, ptr @glb, i64 2048), i64 %3088 %36 = load i32, ptr %35, align 489 %37 = add i32 %36, %3390 store i32 %37, ptr %35, align 491 %lsr.iv.next = add i32 %lsr.iv, -192 %lsr.iv.next3 = add i32 %lsr.iv2, 193 %exitcond.not = icmp eq i32 %lsr.iv.next, 094 br i1 %exitcond.not, label %exit, label %body95 }96 97 ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)98 declare <vscale x 4 x i32> @llvm.stepvector.nxv4i32() #199 100 ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)101 declare i32 @llvm.vscale.i32() #1102 103 ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(none)104 declare <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i32(i32, i32) #1105 106 ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)107 declare void @llvm.masked.store.nxv4i32.p0(<vscale x 4 x i32>, ptr captures(none), i32 immarg, <vscale x 4 x i1>) #2108 109 ; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: read)110 declare <vscale x 4 x i32> @llvm.masked.load.nxv4i32.p0(ptr captures(none), i32 immarg, <vscale x 4 x i1>, <vscale x 4 x i32>) #3111 112 ; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)113 declare i32 @llvm.usub.sat.i32(i32, i32) #4114 115 attributes #0 = { nounwind vscale_range(1,16) "frame-pointer"="non-leaf" "target-cpu"="neoverse-v1" "target-features"="+sve" }116 attributes #1 = { nocallback nofree nosync nounwind willreturn memory(none) }117 attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }118 attributes #3 = { nocallback nofree nosync nounwind willreturn memory(argmem: read) }119 attributes #4 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }120 121...122---123name: f124tracksRegLiveness: true125body: |126 bb.0.entry:127 successors: %bb.5(0x30000000), %bb.1(0x50000000)128 liveins: $w0, $w1129 130 %20:gpr32common = COPY $w1131 %19:gpr32common = COPY $w0132 %21:gpr32common = SUBWrr %20, %19133 dead $wzr = ADDSWri %21, 1, 0, implicit-def $nzcv134 Bcc 0, %bb.5, implicit $nzcv135 B %bb.1136 137 bb.1.preheader:138 successors: %bb.2(0x40000000), %bb.3(0x40000000)139 140 %22:gpr32common = ADDWri %19, 1, 0141 %23:gpr32sp = ADDWri %19, 2, 0142 %25:gpr32common = ADDWri %20, 1, 0143 dead $wzr = SUBSWrr killed %25, %22, implicit-def $nzcv144 Bcc 10, %bb.3, implicit $nzcv145 B %bb.2146 147 bb.2.body.preheader:148 successors: %bb.6(0x80000000)149 150 %1:gpr32sp = COPY %23151 %55:gpr32sp = ADDWri %21, 1, 0152 %2:gpr32all = COPY %55153 %57:gpr64common = MOVaddr target-flags(aarch64-page) @glb, target-flags(aarch64-pageoff, aarch64-nc) @glb154 B %bb.6155 156 bb.3.vector.ph:157 successors: %bb.4(0x80000000)158 159 %29:gpr32common = ADDWri %21, 1, 0160 %30:gpr64 = CNTW_XPiI 31, 1, implicit $vg161 %31:gpr32common = COPY %30.sub_32162 %32:gpr32 = SUBSWrr %29, %31, implicit-def $nzcv163 %33:gpr32 = COPY $wzr164 %34:gpr32 = CSELWr %33, killed %32, 3, implicit $nzcv165 %4:ppr = WHILELO_PWW_S %33, %29, implicit-def dead $nzcv166 %5:zpr = INDEX_II_S 0, 1, implicit $vg167 %6:zpr = DUP_ZR_S %31168 %7:zpr = DUP_ZR_S %22169 %8:zpr = DUP_ZR_S %23170 %27:gpr32all = COPY %33171 %37:gpr64common = MOVaddr target-flags(aarch64-page) @glb, target-flags(aarch64-pageoff, aarch64-nc) @glb172 %39:gpr64common = MOVi64imm -1173 %41:ppr_3b = PTRUE_S 31, implicit $vg174 %44:gpr64common = MOVi64imm 255175 %45:gpr64common = MOVi64imm 511176 177 bb.4.vector.body:178 successors: %bb.4(0x7c000000), %bb.5(0x04000000)179 180 %9:gpr32 = PHI %27, %bb.3, %12, %bb.4181 %10:ppr_3b = PHI %4, %bb.3, %13, %bb.4182 %11:zpr = PHI %5, %bb.3, %14, %bb.4183 %35:zpr = ADD_ZZZ_S %11, %7184 %36:gpr32 = COPY %35.ssub185 %38:gpr64sp = ADDXrx %37, killed %36, 50186 ST1W %35, %10, %38, %39 :: (store unknown-size into %ir.18, align 4)187 %40:zpr = ADD_ZZZ_S %11, %8188 %42:zpr = MUL_ZPZZ_S_UNDEF %41, %35, killed %40189 %43:zpr = ASRD_ZPmI_S %41, %42, 1190 ST1W %43, %10, %38, %44 :: (store unknown-size into %ir.22, align 4)191 %46:zpr = LD1W %10, %38, %45 :: (load unknown-size from %ir.23, align 4)192 %47:zpr = ADD_ZZZ_S killed %46, %43193 ST1W killed %47, %10, %38, %45 :: (store unknown-size into %ir.23, align 4)194 %50:gpr32 = ADDWrr %9, %31195 %12:gpr32all = COPY %50196 %13:ppr = WHILELO_PWW_S %9, %34, implicit-def $nzcv197 %14:zpr = ADD_ZZZ_S %11, %6198 Bcc 4, %bb.4, implicit $nzcv199 B %bb.5200 201 bb.5.exit:202 RET_ReallyLR203 204 bb.6.body:205 successors: %bb.5(0x04000000), %bb.6(0x7c000000)206 207 %15:gpr32common = PHI %1, %bb.2, %18, %bb.6208 %16:gpr32sp = PHI %2, %bb.2, %17, %bb.6209 %56:gpr32common = SUBWri %15, 1, 0210 %58:gpr64sp = ADDXrx %57, %56, 50211 STURWi %56, %58, -4 :: (store (s32) into %ir.31)212 %59:gpr32 = MADDWrrr %56, %15, $wzr213 %60:gpr32 = ADDWrs %59, %59, 95214 %61:gpr32 = SBFMWri killed %60, 1, 31215 STRWui %61, %58, 255 :: (store (s32) into %ir.34)216 %62:gpr32 = LDRWui %58, 511 :: (load (s32) from %ir.35)217 %63:gpr32 = ADDWrr killed %62, %61218 STRWui killed %63, %58, 511 :: (store (s32) into %ir.35)219 %64:gpr32 = SUBSWri %16, 1, 0, implicit-def $nzcv220 %17:gpr32all = COPY %64221 %65:gpr32sp = ADDWri %15, 1, 0222 %18:gpr32all = COPY %65223 Bcc 0, %bb.5, implicit $nzcv224 B %bb.6225 226...227