153 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=aarch64-linux-gnu | FileCheck %s3 4define i32 @func(i32 %x, i32 %y) nounwind {5; CHECK-LABEL: func:6; CHECK: // %bb.0:7; CHECK-NEXT: smull x8, w0, w18; CHECK-NEXT: lsr x9, x8, #329; CHECK-NEXT: extr w0, w9, w8, #210; CHECK-NEXT: ret11 %tmp = call i32 @llvm.smul.fix.i32(i32 %x, i32 %y, i32 2)12 ret i32 %tmp13}14 15define i64 @func2(i64 %x, i64 %y) {16; CHECK-LABEL: func2:17; CHECK: // %bb.0:18; CHECK-NEXT: mul x8, x0, x119; CHECK-NEXT: smulh x9, x0, x120; CHECK-NEXT: extr x0, x9, x8, #221; CHECK-NEXT: ret22 %tmp = call i64 @llvm.smul.fix.i64(i64 %x, i64 %y, i32 2)23 ret i64 %tmp24}25 26define i4 @func3(i4 %x, i4 %y) nounwind {27; CHECK-LABEL: func3:28; CHECK: // %bb.0:29; CHECK-NEXT: sbfx w8, w1, #0, #430; CHECK-NEXT: sbfx w9, w0, #0, #431; CHECK-NEXT: smull x8, w9, w832; CHECK-NEXT: lsr x9, x8, #3233; CHECK-NEXT: extr w0, w9, w8, #234; CHECK-NEXT: ret35 %tmp = call i4 @llvm.smul.fix.i4(i4 %x, i4 %y, i32 2)36 ret i4 %tmp37}38 39;; These result in regular integer multiplication40define i32 @func4(i32 %x, i32 %y) nounwind {41; CHECK-LABEL: func4:42; CHECK: // %bb.0:43; CHECK-NEXT: mul w0, w0, w144; CHECK-NEXT: ret45 %tmp = call i32 @llvm.smul.fix.i32(i32 %x, i32 %y, i32 0)46 ret i32 %tmp47}48 49define i64 @func5(i64 %x, i64 %y) {50; CHECK-LABEL: func5:51; CHECK: // %bb.0:52; CHECK-NEXT: mul x0, x0, x153; CHECK-NEXT: ret54 %tmp = call i64 @llvm.smul.fix.i64(i64 %x, i64 %y, i32 0)55 ret i64 %tmp56}57 58define i4 @func6(i4 %x, i4 %y) nounwind {59; CHECK-LABEL: func6:60; CHECK: // %bb.0:61; CHECK-NEXT: sbfx w8, w1, #0, #462; CHECK-NEXT: sbfx w9, w0, #0, #463; CHECK-NEXT: mul w0, w9, w864; CHECK-NEXT: ret65 %tmp = call i4 @llvm.smul.fix.i4(i4 %x, i4 %y, i32 0)66 ret i4 %tmp67}68 69define i64 @func7(i64 %x, i64 %y) nounwind {70; CHECK-LABEL: func7:71; CHECK: // %bb.0:72; CHECK-NEXT: mul x8, x0, x173; CHECK-NEXT: smulh x9, x0, x174; CHECK-NEXT: extr x0, x9, x8, #3275; CHECK-NEXT: ret76 %tmp = call i64 @llvm.smul.fix.i64(i64 %x, i64 %y, i32 32)77 ret i64 %tmp78}79 80define i64 @func8(i64 %x, i64 %y) nounwind {81; CHECK-LABEL: func8:82; CHECK: // %bb.0:83; CHECK-NEXT: mul x8, x0, x184; CHECK-NEXT: smulh x9, x0, x185; CHECK-NEXT: extr x0, x9, x8, #6386; CHECK-NEXT: ret87 %tmp = call i64 @llvm.smul.fix.i64(i64 %x, i64 %y, i32 63)88 ret i64 %tmp89}90 91define <2 x i32> @vec(<2 x i32> %x, <2 x i32> %y) nounwind {92; CHECK-LABEL: vec:93; CHECK: // %bb.0:94; CHECK-NEXT: mul v0.2s, v0.2s, v1.2s95; CHECK-NEXT: ret96 %tmp = call <2 x i32> @llvm.smul.fix.v2i32(<2 x i32> %x, <2 x i32> %y, i32 0)97 ret <2 x i32> %tmp98}99 100define <4 x i32> @vec2(<4 x i32> %x, <4 x i32> %y) nounwind {101; CHECK-LABEL: vec2:102; CHECK: // %bb.0:103; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s104; CHECK-NEXT: ret105 %tmp = call <4 x i32> @llvm.smul.fix.v4i32(<4 x i32> %x, <4 x i32> %y, i32 0)106 ret <4 x i32> %tmp107}108 109define <4 x i64> @vec3(<4 x i64> %x, <4 x i64> %y) nounwind {110; CHECK-LABEL: vec3:111; CHECK: // %bb.0:112; CHECK-NEXT: mov x8, v2.d[1]113; CHECK-NEXT: mov x9, v0.d[1]114; CHECK-NEXT: fmov x10, d2115; CHECK-NEXT: fmov x11, d0116; CHECK-NEXT: mov x14, v3.d[1]117; CHECK-NEXT: mov x15, v1.d[1]118; CHECK-NEXT: mul x12, x11, x10119; CHECK-NEXT: mul x13, x9, x8120; CHECK-NEXT: smulh x8, x9, x8121; CHECK-NEXT: smulh x9, x11, x10122; CHECK-NEXT: fmov x10, d3123; CHECK-NEXT: fmov x11, d1124; CHECK-NEXT: mul x16, x11, x10125; CHECK-NEXT: extr x8, x8, x13, #32126; CHECK-NEXT: smulh x10, x11, x10127; CHECK-NEXT: extr x9, x9, x12, #32128; CHECK-NEXT: mul x11, x15, x14129; CHECK-NEXT: fmov d0, x9130; CHECK-NEXT: smulh x14, x15, x14131; CHECK-NEXT: extr x10, x10, x16, #32132; CHECK-NEXT: mov v0.d[1], x8133; CHECK-NEXT: fmov d1, x10134; CHECK-NEXT: extr x11, x14, x11, #32135; CHECK-NEXT: mov v1.d[1], x11136; CHECK-NEXT: ret137 %tmp = call <4 x i64> @llvm.smul.fix.v4i64(<4 x i64> %x, <4 x i64> %y, i32 32)138 ret <4 x i64> %tmp139}140 141define <4 x i16> @widemul(<4 x i16> %x, <4 x i16> %y) nounwind {142; CHECK-LABEL: widemul:143; CHECK: // %bb.0:144; CHECK-NEXT: smull v0.4s, v0.4h, v1.4h145; CHECK-NEXT: shrn v1.4h, v0.4s, #16146; CHECK-NEXT: xtn v2.4h, v0.4s147; CHECK-NEXT: shl v0.4h, v1.4h, #14148; CHECK-NEXT: usra v0.4h, v2.4h, #2149; CHECK-NEXT: ret150 %tmp = call <4 x i16> @llvm.smul.fix.v4i16(<4 x i16> %x, <4 x i16> %y, i32 2)151 ret <4 x i16> %tmp152}153