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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=aarch64-linux-gnu | FileCheck %s3 4define i32 @func(i32 %x, i32 %y) nounwind {5; CHECK-LABEL: func:6; CHECK: // %bb.0:7; CHECK-NEXT: smull x9, w0, w18; CHECK-NEXT: mov w8, #2147483647 // =0x7fffffff9; CHECK-NEXT: lsr x10, x9, #3210; CHECK-NEXT: extr w9, w10, w9, #211; CHECK-NEXT: cmp w10, #112; CHECK-NEXT: csel w8, w8, w9, gt13; CHECK-NEXT: cmn w10, #214; CHECK-NEXT: mov w9, #-2147483648 // =0x8000000015; CHECK-NEXT: csel w0, w9, w8, lt16; CHECK-NEXT: ret17 %tmp = call i32 @llvm.smul.fix.sat.i32(i32 %x, i32 %y, i32 2)18 ret i32 %tmp19}20 21define i64 @func2(i64 %x, i64 %y) nounwind {22; CHECK-LABEL: func2:23; CHECK: // %bb.0:24; CHECK-NEXT: mul x9, x0, x125; CHECK-NEXT: mov x8, #9223372036854775807 // =0x7fffffffffffffff26; CHECK-NEXT: smulh x10, x0, x127; CHECK-NEXT: extr x9, x10, x9, #228; CHECK-NEXT: cmp x10, #129; CHECK-NEXT: csel x8, x8, x9, gt30; CHECK-NEXT: cmn x10, #231; CHECK-NEXT: mov x9, #-9223372036854775808 // =0x800000000000000032; CHECK-NEXT: csel x0, x9, x8, lt33; CHECK-NEXT: ret34 %tmp = call i64 @llvm.smul.fix.sat.i64(i64 %x, i64 %y, i32 2)35 ret i64 %tmp36}37 38define i4 @func3(i4 %x, i4 %y) nounwind {39; CHECK-LABEL: func3:40; CHECK: // %bb.0:41; CHECK-NEXT: sbfx w9, w1, #0, #442; CHECK-NEXT: lsl w10, w0, #2843; CHECK-NEXT: mov w8, #2147483647 // =0x7fffffff44; CHECK-NEXT: smull x9, w10, w945; CHECK-NEXT: lsr x10, x9, #3246; CHECK-NEXT: extr w9, w10, w9, #247; CHECK-NEXT: cmp w10, #148; CHECK-NEXT: csel w8, w8, w9, gt49; CHECK-NEXT: cmn w10, #250; CHECK-NEXT: mov w9, #-2147483648 // =0x8000000051; CHECK-NEXT: csel w8, w9, w8, lt52; CHECK-NEXT: asr w0, w8, #2853; CHECK-NEXT: ret54 %tmp = call i4 @llvm.smul.fix.sat.i4(i4 %x, i4 %y, i32 2)55 ret i4 %tmp56}57 58;; These result in regular integer multiplication with a saturation check.59define i32 @func4(i32 %x, i32 %y) nounwind {60; CHECK-LABEL: func4:61; CHECK: // %bb.0:62; CHECK-NEXT: smull x9, w0, w163; CHECK-NEXT: eor w10, w0, w164; CHECK-NEXT: mov w8, #-2147483648 // =0x8000000065; CHECK-NEXT: cmp w10, #066; CHECK-NEXT: cinv w8, w8, pl67; CHECK-NEXT: cmp x9, w9, sxtw68; CHECK-NEXT: csel w0, w8, w9, ne69; CHECK-NEXT: ret70 %tmp = call i32 @llvm.smul.fix.sat.i32(i32 %x, i32 %y, i32 0)71 ret i32 %tmp72}73 74define i64 @func5(i64 %x, i64 %y) {75; CHECK-LABEL: func5:76; CHECK: // %bb.0:77; CHECK-NEXT: mul x9, x0, x178; CHECK-NEXT: eor x11, x0, x179; CHECK-NEXT: mov x8, #-9223372036854775808 // =0x800000000000000080; CHECK-NEXT: cmp x11, #081; CHECK-NEXT: smulh x10, x0, x182; CHECK-NEXT: cinv x8, x8, pl83; CHECK-NEXT: cmp x10, x9, asr #6384; CHECK-NEXT: csel x0, x8, x9, ne85; CHECK-NEXT: ret86 %tmp = call i64 @llvm.smul.fix.sat.i64(i64 %x, i64 %y, i32 0)87 ret i64 %tmp88}89 90define i4 @func6(i4 %x, i4 %y) nounwind {91; CHECK-LABEL: func6:92; CHECK: // %bb.0:93; CHECK-NEXT: sbfx w9, w1, #0, #494; CHECK-NEXT: lsl w10, w0, #2895; CHECK-NEXT: mov w8, #-2147483648 // =0x8000000096; CHECK-NEXT: smull x11, w10, w997; CHECK-NEXT: eor w9, w10, w998; CHECK-NEXT: cmp w9, #099; CHECK-NEXT: cinv w8, w8, pl100; CHECK-NEXT: cmp x11, w11, sxtw101; CHECK-NEXT: csel w8, w8, w11, ne102; CHECK-NEXT: asr w0, w8, #28103; CHECK-NEXT: ret104 %tmp = call i4 @llvm.smul.fix.sat.i4(i4 %x, i4 %y, i32 0)105 ret i4 %tmp106}107 108define i64 @func7(i64 %x, i64 %y) nounwind {109; CHECK-LABEL: func7:110; CHECK: // %bb.0:111; CHECK-NEXT: mul x9, x0, x1112; CHECK-NEXT: mov w8, #2147483647 // =0x7fffffff113; CHECK-NEXT: mov x11, #-2147483648 // =0xffffffff80000000114; CHECK-NEXT: smulh x10, x0, x1115; CHECK-NEXT: extr x9, x10, x9, #32116; CHECK-NEXT: cmp x10, x8117; CHECK-NEXT: mov x8, #9223372036854775807 // =0x7fffffffffffffff118; CHECK-NEXT: csel x8, x8, x9, gt119; CHECK-NEXT: cmp x10, x11120; CHECK-NEXT: mov x9, #-9223372036854775808 // =0x8000000000000000121; CHECK-NEXT: csel x0, x9, x8, lt122; CHECK-NEXT: ret123 %tmp = call i64 @llvm.smul.fix.sat.i64(i64 %x, i64 %y, i32 32)124 ret i64 %tmp125}126 127define i64 @func8(i64 %x, i64 %y) nounwind {128; CHECK-LABEL: func8:129; CHECK: // %bb.0:130; CHECK-NEXT: mul x9, x0, x1131; CHECK-NEXT: mov x8, #4611686018427387903 // =0x3fffffffffffffff132; CHECK-NEXT: mov x11, #-4611686018427387904 // =0xc000000000000000133; CHECK-NEXT: smulh x10, x0, x1134; CHECK-NEXT: extr x9, x10, x9, #63135; CHECK-NEXT: cmp x10, x8136; CHECK-NEXT: mov x8, #9223372036854775807 // =0x7fffffffffffffff137; CHECK-NEXT: csel x8, x8, x9, gt138; CHECK-NEXT: cmp x10, x11139; CHECK-NEXT: mov x9, #-9223372036854775808 // =0x8000000000000000140; CHECK-NEXT: csel x0, x9, x8, lt141; CHECK-NEXT: ret142 %tmp = call i64 @llvm.smul.fix.sat.i64(i64 %x, i64 %y, i32 63)143 ret i64 %tmp144}145 146define <2 x i32> @vec(<2 x i32> %x, <2 x i32> %y) nounwind {147; CHECK-LABEL: vec:148; CHECK: // %bb.0:149; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1150; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0151; CHECK-NEXT: mov w9, v1.s[1]152; CHECK-NEXT: mov w10, v0.s[1]153; CHECK-NEXT: mov w8, #-2147483648 // =0x80000000154; CHECK-NEXT: fmov w12, s0155; CHECK-NEXT: smull x11, w10, w9156; CHECK-NEXT: eor w9, w10, w9157; CHECK-NEXT: fmov w10, s1158; CHECK-NEXT: cmp w9, #0159; CHECK-NEXT: smull x9, w12, w10160; CHECK-NEXT: eor w10, w12, w10161; CHECK-NEXT: cinv w12, w8, pl162; CHECK-NEXT: cmp x11, w11, sxtw163; CHECK-NEXT: csel w11, w12, w11, ne164; CHECK-NEXT: cmp w10, #0165; CHECK-NEXT: cinv w8, w8, pl166; CHECK-NEXT: cmp x9, w9, sxtw167; CHECK-NEXT: csel w8, w8, w9, ne168; CHECK-NEXT: fmov s0, w8169; CHECK-NEXT: mov v0.s[1], w11170; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0171; CHECK-NEXT: ret172 %tmp = call <2 x i32> @llvm.smul.fix.sat.v2i32(<2 x i32> %x, <2 x i32> %y, i32 0)173 ret <2 x i32> %tmp174}175 176define <4 x i32> @vec2(<4 x i32> %x, <4 x i32> %y) nounwind {177; CHECK-LABEL: vec2:178; CHECK: // %bb.0:179; CHECK-NEXT: mov w9, v1.s[1]180; CHECK-NEXT: mov w10, v0.s[1]181; CHECK-NEXT: mov w8, #-2147483648 // =0x80000000182; CHECK-NEXT: fmov w12, s1183; CHECK-NEXT: fmov w13, s0184; CHECK-NEXT: mov w14, v0.s[2]185; CHECK-NEXT: eor w11, w10, w9186; CHECK-NEXT: smull x9, w10, w9187; CHECK-NEXT: mov w10, v1.s[2]188; CHECK-NEXT: cmp w11, #0189; CHECK-NEXT: smull x11, w13, w12190; CHECK-NEXT: eor w12, w13, w12191; CHECK-NEXT: cinv w13, w8, pl192; CHECK-NEXT: cmp x9, w9, sxtw193; CHECK-NEXT: csel w9, w13, w9, ne194; CHECK-NEXT: cmp w12, #0195; CHECK-NEXT: mov w13, v1.s[3]196; CHECK-NEXT: cinv w12, w8, pl197; CHECK-NEXT: cmp x11, w11, sxtw198; CHECK-NEXT: csel w11, w12, w11, ne199; CHECK-NEXT: mov w12, v0.s[3]200; CHECK-NEXT: fmov s0, w11201; CHECK-NEXT: smull x11, w14, w10202; CHECK-NEXT: mov v0.s[1], w9203; CHECK-NEXT: eor w9, w14, w10204; CHECK-NEXT: smull x10, w12, w13205; CHECK-NEXT: cmp w9, #0206; CHECK-NEXT: cinv w9, w8, pl207; CHECK-NEXT: cmp x11, w11, sxtw208; CHECK-NEXT: csel w9, w9, w11, ne209; CHECK-NEXT: mov v0.s[2], w9210; CHECK-NEXT: eor w9, w12, w13211; CHECK-NEXT: cmp w9, #0212; CHECK-NEXT: cinv w8, w8, pl213; CHECK-NEXT: cmp x10, w10, sxtw214; CHECK-NEXT: csel w8, w8, w10, ne215; CHECK-NEXT: mov v0.s[3], w8216; CHECK-NEXT: ret217 %tmp = call <4 x i32> @llvm.smul.fix.sat.v4i32(<4 x i32> %x, <4 x i32> %y, i32 0)218 ret <4 x i32> %tmp219}220 221define <4 x i64> @vec3(<4 x i64> %x, <4 x i64> %y) nounwind {222; CHECK-LABEL: vec3:223; CHECK: // %bb.0:224; CHECK-NEXT: mov x8, v2.d[1]225; CHECK-NEXT: mov x9, v0.d[1]226; CHECK-NEXT: mov w16, #2147483647 // =0x7fffffff227; CHECK-NEXT: fmov x10, d2228; CHECK-NEXT: fmov x11, d0229; CHECK-NEXT: mov x18, #9223372036854775807 // =0x7fffffffffffffff230; CHECK-NEXT: mov x14, v3.d[1]231; CHECK-NEXT: mov x15, v1.d[1]232; CHECK-NEXT: mul x13, x9, x8233; CHECK-NEXT: smulh x8, x9, x8234; CHECK-NEXT: mul x12, x11, x10235; CHECK-NEXT: smulh x9, x11, x10236; CHECK-NEXT: extr x13, x8, x13, #32237; CHECK-NEXT: cmp x8, x16238; CHECK-NEXT: mul x10, x15, x14239; CHECK-NEXT: csel x13, x18, x13, gt240; CHECK-NEXT: smulh x11, x15, x14241; CHECK-NEXT: fmov x14, d3242; CHECK-NEXT: fmov x15, d1243; CHECK-NEXT: extr x12, x9, x12, #32244; CHECK-NEXT: mul x17, x15, x14245; CHECK-NEXT: smulh x14, x15, x14246; CHECK-NEXT: mov x15, #-2147483648 // =0xffffffff80000000247; CHECK-NEXT: cmp x8, x15248; CHECK-NEXT: mov x8, #-9223372036854775808 // =0x8000000000000000249; CHECK-NEXT: csel x13, x8, x13, lt250; CHECK-NEXT: cmp x9, x16251; CHECK-NEXT: csel x12, x18, x12, gt252; CHECK-NEXT: cmp x9, x15253; CHECK-NEXT: extr x9, x11, x10, #32254; CHECK-NEXT: csel x10, x8, x12, lt255; CHECK-NEXT: cmp x11, x16256; CHECK-NEXT: csel x9, x18, x9, gt257; CHECK-NEXT: cmp x11, x15258; CHECK-NEXT: extr x11, x14, x17, #32259; CHECK-NEXT: csel x9, x8, x9, lt260; CHECK-NEXT: cmp x14, x16261; CHECK-NEXT: fmov d0, x10262; CHECK-NEXT: csel x11, x18, x11, gt263; CHECK-NEXT: cmp x14, x15264; CHECK-NEXT: csel x8, x8, x11, lt265; CHECK-NEXT: fmov d1, x8266; CHECK-NEXT: mov v0.d[1], x13267; CHECK-NEXT: mov v1.d[1], x9268; CHECK-NEXT: ret269 %tmp = call <4 x i64> @llvm.smul.fix.sat.v4i64(<4 x i64> %x, <4 x i64> %y, i32 32)270 ret <4 x i64> %tmp271}272