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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu | FileCheck %s3 4define i128 @ldp_single_csdb(ptr %p) speculative_load_hardening {5; CHECK-LABEL: ldp_single_csdb:6; CHECK: // %bb.0: // %entry7; CHECK-NEXT: ldp x8, x1, [x0]8; CHECK-NEXT: cmp sp, #09; CHECK-NEXT: csetm x16, ne10; CHECK-NEXT: and x8, x8, x1611; CHECK-NEXT: and x1, x1, x1612; CHECK-NEXT: csdb13; CHECK-NEXT: mov x2, sp14; CHECK-NEXT: mov x0, x815; CHECK-NEXT: and x2, x2, x1616; CHECK-NEXT: mov sp, x217; CHECK-NEXT: ret18entry:19 %0 = load i128, ptr %p, align 1620 ret i128 %021}22 23; Checking that the address loaded from is masked for a floating point load.24define double @ld_double(ptr %p) speculative_load_hardening {25; CHECK-LABEL: ld_double:26; CHECK: // %bb.0: // %entry27; CHECK-NEXT: cmp sp, #028; CHECK-NEXT: csetm x16, ne29; CHECK-NEXT: and x0, x0, x1630; CHECK-NEXT: csdb31; CHECK-NEXT: ldr d0, [x0]32; CHECK-NEXT: mov x0, sp33; CHECK-NEXT: and x0, x0, x1634; CHECK-NEXT: mov sp, x035; CHECK-NEXT: ret36entry:37 %0 = load double, ptr %p, align 838 ret double %039}40 41; Checking that the address loaded from is masked for a floating point load.42; csdb instruction must occur before the add instruction with w8 as operand.43define i32 @csdb_emitted_for_subreg_use(ptr %p, i32 %b) speculative_load_hardening {44; CHECK-LABEL: csdb_emitted_for_subreg_use:45; CHECK: // %bb.0: // %entry46; CHECK-NEXT: cmp sp, #047; CHECK-NEXT: ldr x8, [x0]48; CHECK-NEXT: csetm x16, ne49; CHECK-NEXT: and x8, x8, x1650; CHECK-NEXT: csdb51; CHECK-NEXT: add w9, w1, w852; CHECK-NEXT: cmp x8, #053; CHECK-NEXT: csel w0, w1, w9, eq54; CHECK-NEXT: mov x1, sp55; CHECK-NEXT: and x1, x1, x1656; CHECK-NEXT: mov sp, x157; CHECK-NEXT: ret58entry:59 %X = load i64, ptr %p, align 860 %X_trunc = trunc i64 %X to i3261 %add = add i32 %b, %X_trunc62 %iszero = icmp eq i64 %X, 063 %ret = select i1 %iszero, i32 %b, i32 %add64 ret i32 %ret65}66 67; Checking that the address loaded from is masked for a floating point load.68; csdb instruction must occur before the add instruction with x8 as operand.69define i64 @csdb_emitted_for_superreg_use(ptr %p, i64 %b) speculative_load_hardening {70; CHECK-LABEL: csdb_emitted_for_superreg_use:71; CHECK: // %bb.0: // %entry72; CHECK-NEXT: cmp sp, #073; CHECK-NEXT: ldr w8, [x0]74; CHECK-NEXT: csetm x16, ne75; CHECK-NEXT: and w8, w8, w1676; CHECK-NEXT: csdb77; CHECK-NEXT: add x9, x1, x878; CHECK-NEXT: cmp w8, #079; CHECK-NEXT: csel x0, x1, x9, eq80; CHECK-NEXT: mov x1, sp81; CHECK-NEXT: and x1, x1, x1682; CHECK-NEXT: mov sp, x183; CHECK-NEXT: ret84entry:85 %X = load i32, ptr %p, align 486 %X_ext = zext i32 %X to i6487 %add = add i64 %b, %X_ext88 %iszero = icmp eq i32 %X, 089 %ret = select i1 %iszero, i64 %b, i64 %add90 ret i64 %ret91}92 93define i64 @no_masking_with_full_control_flow_barriers(i64 %a, i64 %b, ptr %p) speculative_load_hardening {94; CHECK-LABEL: no_masking_with_full_control_flow_barriers:95; CHECK: // %bb.0: // %entry96; CHECK-NEXT: dsb sy97; CHECK-NEXT: isb98; CHECK-NEXT: ldr x8, [x2]99; CHECK-NEXT: mov x17, x0100; CHECK-NEXT: mov x16, x1101; CHECK-NEXT: //APP102; CHECK-NEXT: hint #12103; CHECK-NEXT: //NO_APP104; CHECK-NEXT: add x0, x8, x17105; CHECK-NEXT: ret106entry:107 %0 = tail call i64 asm "hint #12", "={x17},{x16},0"(i64 %b, i64 %a)108 %X = load i64, ptr %p, align 8109 %ret = add i64 %X, %0110 ret i64 %ret111}112 113define void @f_implicitdef_vector_load(ptr %dst, ptr %src) speculative_load_hardening {114; CHECK-LABEL: f_implicitdef_vector_load:115; CHECK: // %bb.0: // %entry116; CHECK-NEXT: cmp sp, #0117; CHECK-NEXT: csetm x16, ne118; CHECK-NEXT: and x1, x1, x16119; CHECK-NEXT: csdb120; CHECK-NEXT: ldr d0, [x1]121; CHECK-NEXT: mov v0.d[1], v0.d[0]122; CHECK-NEXT: str q0, [x0]123; CHECK-NEXT: mov x0, sp124; CHECK-NEXT: and x0, x0, x16125; CHECK-NEXT: mov sp, x0126; CHECK-NEXT: ret127entry:128 %0 = load <2 x i32>, ptr %src, align 8129 %shuffle = shufflevector <2 x i32> %0, <2 x i32> undef, <4 x i32> <i32 0, i32 1, i32 0, i32 1>130 store <4 x i32> %shuffle, ptr %dst, align 4131 ret void132}133 134define <2 x double> @f_usedefvectorload(ptr %a, ptr %b) speculative_load_hardening {135; CHECK-LABEL: f_usedefvectorload:136; CHECK: // %bb.0: // %entry137; CHECK-NEXT: cmp sp, #0138; CHECK-NEXT: csetm x16, ne139; CHECK-NEXT: and x1, x1, x16140; CHECK-NEXT: csdb141; CHECK-NEXT: mov x0, sp142; CHECK-NEXT: ldr d0, [x1]143; CHECK-NEXT: and x0, x0, x16144; CHECK-NEXT: mov sp, x0145; CHECK-NEXT: ret146entry:147 %0 = load double, ptr %b, align 16148 %vld1_lane = insertelement <2 x double> <double undef, double 0.000000e+00>, double %0, i32 0149 ret <2 x double> %vld1_lane150}151 152define i32 @deadload() speculative_load_hardening uwtable {153; CHECK-LABEL: deadload:154; CHECK: // %bb.0: // %entry155; CHECK-NEXT: cmp sp, #0156; CHECK-NEXT: csetm x16, ne157; CHECK-NEXT: sub sp, sp, #16158; CHECK-NEXT: .cfi_def_cfa_offset 16159; CHECK-NEXT: ldr w8, [sp, #12]160; CHECK-NEXT: add sp, sp, #16161; CHECK-NEXT: .cfi_def_cfa_offset 0162; CHECK-NEXT: mov x0, sp163; CHECK-NEXT: and x0, x0, x16164; CHECK-NEXT: mov sp, x0165; CHECK-NEXT: ret166entry:167 %a = alloca i32, align 4168 %val = load volatile i32, ptr %a, align 4169 ret i32 undef170}171