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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc < %s -mtriple=aarch64 -mattr=+sve2 -aarch64-stack-hazard-in-non-streaming -aarch64-split-sve-objects -aarch64-streaming-hazard-size=1024 | FileCheck %s3; RUN: llc < %s -mtriple=aarch64 -mattr=+sve2 -aarch64-stack-hazard-in-non-streaming -aarch64-split-sve-objects -aarch64-streaming-hazard-size=1024 -pass-remarks-analysis=stack-frame-layout 2>&1 >/dev/null | FileCheck %s --check-prefixes=CHECK-FRAMELAYOUT4 5; CHECK-FRAMELAYOUT-LABEL: Function: zpr_and_ppr_local6; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-16], Type: Spill, Align: 16, Size: 87; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-16-2 x vscale], Type: Variable, Align: 2, Size: vscale x 28; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-1040-32 x vscale], Type: Variable, Align: 16, Size: vscale x 169; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-2064-32 x vscale], Type: Variable, Align: 16, Size: 102410 11; <GPRs>12; %ppr_local sp+2048+30*vscale (= #15, mul vl for str/ldr PPR)13; 14 x vscale bytes of padding sp+2048+16*vscale14; <hazard padding> sp+1024+16*vscale15; %zpr_local sp+102416; <hazard padding>17; -> sp18define void @zpr_and_ppr_local(<vscale x 16 x i1> %pred, <vscale x 16 x i8> %vector) "aarch64_pstate_sm_compatible" {19; CHECK-LABEL: zpr_and_ppr_local:20; CHECK: // %bb.0:21; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill22; CHECK-NEXT: sub sp, sp, #204823; CHECK-NEXT: addvl sp, sp, #-224; CHECK-NEXT: .cfi_escape 0x0f, 0x09, 0x8f, 0x90, 0x10, 0x92, 0x2e, 0x00, 0x40, 0x1e, 0x22 // sp + 2064 + 16 * VG25; CHECK-NEXT: .cfi_offset w29, -1626; CHECK-NEXT: add x8, sp, #204827; CHECK-NEXT: str p0, [x8, #15, mul vl]28; CHECK-NEXT: add x8, sp, #102429; CHECK-NEXT: str z0, [x8]30; CHECK-NEXT: add sp, sp, #204831; CHECK-NEXT: addvl sp, sp, #232; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload33; CHECK-NEXT: ret34 %ppr_local = alloca <vscale x 16 x i1>35 %zpr_local = alloca <vscale x 16 x i8>36 store volatile <vscale x 16 x i1> %pred, ptr %ppr_local37 store volatile <vscale x 16 x i8> %vector, ptr %zpr_local38 ret void39}40 41; CHECK-FRAMELAYOUT-LABEL: Function: zpr_and_ppr_local_fp42; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-8], Type: Spill, Align: 8, Size: 843; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-16], Type: Spill, Align: 8, Size: 844; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-16-2 x vscale], Type: Variable, Align: 2, Size: vscale x 245; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-1040-32 x vscale], Type: Variable, Align: 16, Size: vscale x 1646; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-2064-32 x vscale], Type: Variable, Align: 16, Size: 102447 48; <GPRs>49; -> fp50; %ppr_local fp-2*vscale (= #-1, mul vl for str/ldr PPR)51; 14 x vscale bytes of padding fp-16*vscale52; <hazard padding> fp-1024-16*vscale53; %zpr_local fp-1024-32*vscale (= #-2, mul vl for str/ldr ZPR)54; <hazard padding>55; -> sp56define void @zpr_and_ppr_local_fp(<vscale x 16 x i1> %pred, <vscale x 16 x i8> %vector) "aarch64_pstate_sm_compatible" "frame-pointer"="all" {57; CHECK-LABEL: zpr_and_ppr_local_fp:58; CHECK: // %bb.0:59; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill60; CHECK-NEXT: mov x29, sp61; CHECK-NEXT: sub sp, sp, #204862; CHECK-NEXT: addvl sp, sp, #-263; CHECK-NEXT: .cfi_def_cfa w29, 1664; CHECK-NEXT: .cfi_offset w30, -865; CHECK-NEXT: .cfi_offset w29, -1666; CHECK-NEXT: sub x8, x29, #102467; CHECK-NEXT: str p0, [x29, #-1, mul vl]68; CHECK-NEXT: str z0, [x8, #-2, mul vl]69; CHECK-NEXT: add sp, sp, #204870; CHECK-NEXT: addvl sp, sp, #271; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload72; CHECK-NEXT: ret73 %ppr_local = alloca <vscale x 16 x i1>74 %zpr_local = alloca <vscale x 16 x i8>75 store volatile <vscale x 16 x i1> %pred, ptr %ppr_local76 store volatile <vscale x 16 x i8> %vector, ptr %zpr_local77 ret void78}79 80; CHECK-FRAMELAYOUT-LABEL: Function: fpr_and_ppr_local81; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-16], Type: Spill, Align: 16, Size: 882; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-16-2 x vscale], Type: Variable, Align: 2, Size: vscale x 283; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-1048-16 x vscale], Type: Variable, Align: 8, Size: 884; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-2080-16 x vscale], Type: Variable, Align: 16, Size: 102485 86; <GPRs>87; %ppr_local sp+2064+14*vscale (= #7, mul vl for str/ldr PPR)88; 14 x vscale bytes of padding sp+206489; <hazard padding> sp+104090; %fpr_local sp+103291; 8 bytes of padding sp+102492; <hazard padding>93; -> sp94define void @fpr_and_ppr_local(<vscale x 16 x i1> %pred, double %double) "aarch64_pstate_sm_compatible" {95; CHECK-LABEL: fpr_and_ppr_local:96; CHECK: // %bb.0:97; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill98; CHECK-NEXT: sub sp, sp, #206499; CHECK-NEXT: addvl sp, sp, #-1100; CHECK-NEXT: .cfi_escape 0x0f, 0x09, 0x8f, 0xa0, 0x10, 0x92, 0x2e, 0x00, 0x38, 0x1e, 0x22 // sp + 2080 + 8 * VG101; CHECK-NEXT: .cfi_offset w29, -16102; CHECK-NEXT: add x8, sp, #2064103; CHECK-NEXT: str p0, [x8, #7, mul vl]104; CHECK-NEXT: str d0, [sp, #1032]105; CHECK-NEXT: add sp, sp, #2064106; CHECK-NEXT: addvl sp, sp, #1107; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload108; CHECK-NEXT: ret109 %ppr_local = alloca <vscale x 16 x i1>110 %fpr_local = alloca double111 store volatile <vscale x 16 x i1> %pred, ptr %ppr_local112 store volatile double %double, ptr %fpr_local113 ret void114}115 116; CHECK-FRAMELAYOUT-LABEL: Function: fpr_and_ppr_local_fp117; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-8], Type: Spill, Align: 8, Size: 8118; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-16], Type: Spill, Align: 8, Size: 8119; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-16-2 x vscale], Type: Variable, Align: 2, Size: vscale x 2120; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-1048-16 x vscale], Type: Variable, Align: 8, Size: 8121; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-2080-16 x vscale], Type: Variable, Align: 16, Size: 1024122 123; <GPRs>124; -> fp125; %ppr_local fp-2*vscale (= #-1, mul vl for str/ldr PPR)126; 14 x vscale bytes of padding127; <hazard padding>128; %fpr_local sp+1032129; 8 bytes of padding sp+1024130; <hazard padding>131; -> sp132define void @fpr_and_ppr_local_fp(<vscale x 16 x i1> %pred, double %double) "aarch64_pstate_sm_compatible" "frame-pointer"="all" {133; CHECK-LABEL: fpr_and_ppr_local_fp:134; CHECK: // %bb.0:135; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill136; CHECK-NEXT: mov x29, sp137; CHECK-NEXT: sub sp, sp, #2064138; CHECK-NEXT: addvl sp, sp, #-1139; CHECK-NEXT: .cfi_def_cfa w29, 16140; CHECK-NEXT: .cfi_offset w30, -8141; CHECK-NEXT: .cfi_offset w29, -16142; CHECK-NEXT: str p0, [x29, #-1, mul vl]143; CHECK-NEXT: str d0, [sp, #1032]144; CHECK-NEXT: add sp, sp, #2064145; CHECK-NEXT: addvl sp, sp, #1146; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload147; CHECK-NEXT: ret148 %ppr_local = alloca <vscale x 16 x i1>149 %fpr_local = alloca double150 store volatile <vscale x 16 x i1> %pred, ptr %ppr_local151 store volatile double %double, ptr %fpr_local152 ret void153}154 155; CHECK-FRAMELAYOUT-LABEL: Function: gpr_and_ppr_local156; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-16], Type: Spill, Align: 16, Size: 8157; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-16-2 x vscale], Type: Variable, Align: 2, Size: vscale x 2158; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-1040-32 x vscale], Type: Spill, Align: 16, Size: vscale x 16159; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-2064-32 x vscale], Type: Variable, Align: 16, Size: 1024160; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-2072-32 x vscale], Type: Variable, Align: 8, Size: 8161 162; <CS GPRs>163; %ppr_local sp+2064+30*vscale (= #15, mul vl for str/ldr PPR)164; 14 x vscale bytes of padding165; <hazard padding> sp+1040+16*vscale166; <fpr callee save: z8> sp+1040167; <hazard padding> sp+16168; %gpr_local sp+8169; 8 bytes of padding170; -> sp171define void @gpr_and_ppr_local(<vscale x 16 x i1> %pred, i64 %int) "aarch64_pstate_sm_compatible" {172; CHECK-LABEL: gpr_and_ppr_local:173; CHECK: // %bb.0:174; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill175; CHECK-NEXT: sub sp, sp, #1024176; CHECK-NEXT: addvl sp, sp, #-2177; CHECK-NEXT: str z8, [sp] // 16-byte Folded Spill178; CHECK-NEXT: sub sp, sp, #1040179; CHECK-NEXT: .cfi_escape 0x0f, 0x09, 0x8f, 0xa0, 0x10, 0x92, 0x2e, 0x00, 0x40, 0x1e, 0x22 // sp + 2080 + 16 * VG180; CHECK-NEXT: .cfi_offset w29, -16181; CHECK-NEXT: .cfi_escape 0x10, 0x48, 0x0b, 0x92, 0x2e, 0x00, 0x11, 0x70, 0x1e, 0x22, 0x11, 0xf0, 0x77, 0x22 // $d8 @ cfa - 16 * VG - 1040182; CHECK-NEXT: add x8, sp, #2064183; CHECK-NEXT: //APP184; CHECK-NEXT: //NO_APP185; CHECK-NEXT: str p0, [x8, #15, mul vl]186; CHECK-NEXT: str x0, [sp, #8]187; CHECK-NEXT: add sp, sp, #1040188; CHECK-NEXT: ldr z8, [sp] // 16-byte Folded Reload189; CHECK-NEXT: add sp, sp, #1024190; CHECK-NEXT: addvl sp, sp, #2191; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload192; CHECK-NEXT: ret193 tail call void asm sideeffect "", "~{d8}"() #1 ; Spill an FPR so hazard padding is needed194 %ppr_local = alloca <vscale x 16 x i1>195 %gpr_local = alloca i64196 store volatile <vscale x 16 x i1> %pred, ptr %ppr_local197 store volatile i64 %int, ptr %gpr_local198 ret void199}200 201; CHECK-FRAMELAYOUT-LABEL: Function: gpr_and_ppr_local_fp202; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-8], Type: Spill, Align: 8, Size: 8203; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-16], Type: Spill, Align: 8, Size: 8204; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-16-2 x vscale], Type: Variable, Align: 2, Size: vscale x 2205; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-1040-32 x vscale], Type: Spill, Align: 16, Size: vscale x 16206; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-2064-32 x vscale], Type: Variable, Align: 16, Size: 1024207; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-2072-32 x vscale], Type: Variable, Align: 8, Size: 8208 209; <CS GPRs>210; -> fp211; %ppr_local fp-2*vscale (= #-1, mul vl for str/ldr PPR)212; 14 x vscale bytes of padding213; <hazard padding>214; <fpr callee save: z8>215; <hazard padding>216; %gpr_local sp+8217; 8 bytes of padding218; -> sp219define void @gpr_and_ppr_local_fp(<vscale x 16 x i1> %pred, i64 %int) "aarch64_pstate_sm_compatible" "frame-pointer"="all" {220; CHECK-LABEL: gpr_and_ppr_local_fp:221; CHECK: // %bb.0:222; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill223; CHECK-NEXT: mov x29, sp224; CHECK-NEXT: sub sp, sp, #1024225; CHECK-NEXT: addvl sp, sp, #-2226; CHECK-NEXT: str z8, [sp] // 16-byte Folded Spill227; CHECK-NEXT: sub sp, sp, #1040228; CHECK-NEXT: .cfi_def_cfa w29, 16229; CHECK-NEXT: .cfi_offset w30, -8230; CHECK-NEXT: .cfi_offset w29, -16231; CHECK-NEXT: .cfi_escape 0x10, 0x48, 0x0b, 0x92, 0x2e, 0x00, 0x11, 0x70, 0x1e, 0x22, 0x11, 0xf0, 0x77, 0x22 // $d8 @ cfa - 16 * VG - 1040232; CHECK-NEXT: //APP233; CHECK-NEXT: //NO_APP234; CHECK-NEXT: str p0, [x29, #-1, mul vl]235; CHECK-NEXT: str x0, [sp, #8]236; CHECK-NEXT: add sp, sp, #1040237; CHECK-NEXT: ldr z8, [sp] // 16-byte Folded Reload238; CHECK-NEXT: add sp, sp, #1024239; CHECK-NEXT: addvl sp, sp, #2240; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload241; CHECK-NEXT: ret242 tail call void asm sideeffect "", "~{d8}"() #1 ; Spill an FPR so hazard padding is needed243 %ppr_local = alloca <vscale x 16 x i1>244 %gpr_local = alloca i64245 store volatile <vscale x 16 x i1> %pred, ptr %ppr_local246 store volatile i64 %int, ptr %gpr_local247 ret void248}249 250; CHECK-FRAMELAYOUT-LABEL: Function: all_stack_areas251; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-8], Type: Spill, Align: 8, Size: 8252; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-16], Type: Spill, Align: 8, Size: 8253; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-16-2 x vscale], Type: Spill, Align: 2, Size: vscale x 2254; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-16-4 x vscale], Type: Spill, Align: 2, Size: vscale x 2255; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-16-6 x vscale], Type: Spill, Align: 2, Size: vscale x 2256; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-16-8 x vscale], Type: Spill, Align: 2, Size: vscale x 2257; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-16-10 x vscale], Type: Spill, Align: 2, Size: vscale x 2258; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-16-12 x vscale], Type: Spill, Align: 2, Size: vscale x 2259; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-16-14 x vscale], Type: Spill, Align: 2, Size: vscale x 2260; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-16-16 x vscale], Type: Spill, Align: 2, Size: vscale x 2261; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-16-18 x vscale], Type: Spill, Align: 2, Size: vscale x 2262; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-16-20 x vscale], Type: Spill, Align: 2, Size: vscale x 2263; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-16-22 x vscale], Type: Spill, Align: 2, Size: vscale x 2264; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-16-24 x vscale], Type: Spill, Align: 2, Size: vscale x 2265; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-16-34 x vscale], Type: Variable, Align: 2, Size: vscale x 2266; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-1040-64 x vscale], Type: Spill, Align: 16, Size: vscale x 16267; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-1040-80 x vscale], Type: Spill, Align: 16, Size: vscale x 16268; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-1040-96 x vscale], Type: Spill, Align: 16, Size: vscale x 16269; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-1040-112 x vscale], Type: Spill, Align: 16, Size: vscale x 16270; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-1040-128 x vscale], Type: Spill, Align: 16, Size: vscale x 16271; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-1040-144 x vscale], Type: Spill, Align: 16, Size: vscale x 16272; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-1040-160 x vscale], Type: Spill, Align: 16, Size: vscale x 16273; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-1040-176 x vscale], Type: Spill, Align: 16, Size: vscale x 16274; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-1040-192 x vscale], Type: Spill, Align: 16, Size: vscale x 16275; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-1040-208 x vscale], Type: Spill, Align: 16, Size: vscale x 16276; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-1040-224 x vscale], Type: Spill, Align: 16, Size: vscale x 16277; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-1040-240 x vscale], Type: Spill, Align: 16, Size: vscale x 16278; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-1040-256 x vscale], Type: Spill, Align: 16, Size: vscale x 16279; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-1040-272 x vscale], Type: Spill, Align: 16, Size: vscale x 16280; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-1040-288 x vscale], Type: Spill, Align: 16, Size: vscale x 16281; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-1040-304 x vscale], Type: Spill, Align: 16, Size: vscale x 16282; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-1040-320 x vscale], Type: Variable, Align: 16, Size: vscale x 16283; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-1048-320 x vscale], Type: Variable, Align: 8, Size: 8284; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-2080-320 x vscale], Type: Variable, Align: 16, Size: 1024285; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-2088-320 x vscale], Type: Variable, Align: 8, Size: 8286 287; <CS GPRs>288; <CS PPRs>289; %ppr_local sp+2080+286*vscale (addvl #17, addpl #7)290; 14 * vscale bytes of padding sp+2080+272*vscale291; <hazard padding> sp+1056+272*vscale292; <CS ZPRs> sp+1056+16*vscale293; %zpr_local sp+1056294; %fpr_local sp+1048295; 8 bytes of padding sp+1040296; <hazard padding> sp+16297; %gpr_local sp+8298; 8 bytes of padding sp299; -> sp300define void @all_stack_areas(<vscale x 16 x i1> %pred, double %fp) {301; CHECK-LABEL: all_stack_areas:302; CHECK: // %bb.0:303; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill304; CHECK-NEXT: addvl sp, sp, #-2305; CHECK-NEXT: str p15, [sp, #4, mul vl] // 2-byte Spill306; CHECK-NEXT: str p14, [sp, #5, mul vl] // 2-byte Spill307; CHECK-NEXT: str p13, [sp, #6, mul vl] // 2-byte Spill308; CHECK-NEXT: str p12, [sp, #7, mul vl] // 2-byte Spill309; CHECK-NEXT: str p11, [sp, #8, mul vl] // 2-byte Spill310; CHECK-NEXT: str p10, [sp, #9, mul vl] // 2-byte Spill311; CHECK-NEXT: str p9, [sp, #10, mul vl] // 2-byte Spill312; CHECK-NEXT: str p8, [sp, #11, mul vl] // 2-byte Spill313; CHECK-NEXT: str p7, [sp, #12, mul vl] // 2-byte Spill314; CHECK-NEXT: str p6, [sp, #13, mul vl] // 2-byte Spill315; CHECK-NEXT: str p5, [sp, #14, mul vl] // 2-byte Spill316; CHECK-NEXT: str p4, [sp, #15, mul vl] // 2-byte Spill317; CHECK-NEXT: sub sp, sp, #1024318; CHECK-NEXT: addvl sp, sp, #-17319; CHECK-NEXT: str z23, [sp] // 16-byte Folded Spill320; CHECK-NEXT: str z22, [sp, #1, mul vl] // 16-byte Folded Spill321; CHECK-NEXT: str z21, [sp, #2, mul vl] // 16-byte Folded Spill322; CHECK-NEXT: str z20, [sp, #3, mul vl] // 16-byte Folded Spill323; CHECK-NEXT: str z19, [sp, #4, mul vl] // 16-byte Folded Spill324; CHECK-NEXT: str z18, [sp, #5, mul vl] // 16-byte Folded Spill325; CHECK-NEXT: str z17, [sp, #6, mul vl] // 16-byte Folded Spill326; CHECK-NEXT: str z16, [sp, #7, mul vl] // 16-byte Folded Spill327; CHECK-NEXT: str z15, [sp, #8, mul vl] // 16-byte Folded Spill328; CHECK-NEXT: str z14, [sp, #9, mul vl] // 16-byte Folded Spill329; CHECK-NEXT: str z13, [sp, #10, mul vl] // 16-byte Folded Spill330; CHECK-NEXT: str z12, [sp, #11, mul vl] // 16-byte Folded Spill331; CHECK-NEXT: str z11, [sp, #12, mul vl] // 16-byte Folded Spill332; CHECK-NEXT: str z10, [sp, #13, mul vl] // 16-byte Folded Spill333; CHECK-NEXT: str z9, [sp, #14, mul vl] // 16-byte Folded Spill334; CHECK-NEXT: str z8, [sp, #15, mul vl] // 16-byte Folded Spill335; CHECK-NEXT: sub sp, sp, #1056336; CHECK-NEXT: addvl sp, sp, #-1337; CHECK-NEXT: .cfi_escape 0x0f, 0x0b, 0x8f, 0xb0, 0x10, 0x92, 0x2e, 0x00, 0x11, 0xa0, 0x01, 0x1e, 0x22 // sp + 2096 + 160 * VG338; CHECK-NEXT: .cfi_offset w30, -8339; CHECK-NEXT: .cfi_offset w29, -16340; CHECK-NEXT: .cfi_escape 0x10, 0x48, 0x0b, 0x92, 0x2e, 0x00, 0x11, 0x60, 0x1e, 0x22, 0x11, 0xf0, 0x77, 0x22 // $d8 @ cfa - 32 * VG - 1040341; CHECK-NEXT: .cfi_escape 0x10, 0x49, 0x0b, 0x92, 0x2e, 0x00, 0x11, 0x58, 0x1e, 0x22, 0x11, 0xf0, 0x77, 0x22 // $d9 @ cfa - 40 * VG - 1040342; CHECK-NEXT: .cfi_escape 0x10, 0x4a, 0x0b, 0x92, 0x2e, 0x00, 0x11, 0x50, 0x1e, 0x22, 0x11, 0xf0, 0x77, 0x22 // $d10 @ cfa - 48 * VG - 1040343; CHECK-NEXT: .cfi_escape 0x10, 0x4b, 0x0b, 0x92, 0x2e, 0x00, 0x11, 0x48, 0x1e, 0x22, 0x11, 0xf0, 0x77, 0x22 // $d11 @ cfa - 56 * VG - 1040344; CHECK-NEXT: .cfi_escape 0x10, 0x4c, 0x0b, 0x92, 0x2e, 0x00, 0x11, 0x40, 0x1e, 0x22, 0x11, 0xf0, 0x77, 0x22 // $d12 @ cfa - 64 * VG - 1040345; CHECK-NEXT: .cfi_escape 0x10, 0x4d, 0x0c, 0x92, 0x2e, 0x00, 0x11, 0xb8, 0x7f, 0x1e, 0x22, 0x11, 0xf0, 0x77, 0x22 // $d13 @ cfa - 72 * VG - 1040346; CHECK-NEXT: .cfi_escape 0x10, 0x4e, 0x0c, 0x92, 0x2e, 0x00, 0x11, 0xb0, 0x7f, 0x1e, 0x22, 0x11, 0xf0, 0x77, 0x22 // $d14 @ cfa - 80 * VG - 1040347; CHECK-NEXT: .cfi_escape 0x10, 0x4f, 0x0c, 0x92, 0x2e, 0x00, 0x11, 0xa8, 0x7f, 0x1e, 0x22, 0x11, 0xf0, 0x77, 0x22 // $d15 @ cfa - 88 * VG - 1040348; CHECK-NEXT: add x0, sp, #2080349; CHECK-NEXT: add x8, sp, #2080350; CHECK-NEXT: add x1, sp, #1056351; CHECK-NEXT: addvl x0, x0, #17352; CHECK-NEXT: add x2, sp, #1048353; CHECK-NEXT: add x3, sp, #8354; CHECK-NEXT: addpl x0, x0, #7355; CHECK-NEXT: str d0, [sp, #1048]356; CHECK-NEXT: str p0, [x8, #143, mul vl]357; CHECK-NEXT: bl foo358; CHECK-NEXT: add sp, sp, #1056359; CHECK-NEXT: addvl sp, sp, #1360; CHECK-NEXT: ldr z23, [sp] // 16-byte Folded Reload361; CHECK-NEXT: ldr z22, [sp, #1, mul vl] // 16-byte Folded Reload362; CHECK-NEXT: ldr z21, [sp, #2, mul vl] // 16-byte Folded Reload363; CHECK-NEXT: ldr z20, [sp, #3, mul vl] // 16-byte Folded Reload364; CHECK-NEXT: ldr z19, [sp, #4, mul vl] // 16-byte Folded Reload365; CHECK-NEXT: ldr z18, [sp, #5, mul vl] // 16-byte Folded Reload366; CHECK-NEXT: ldr z17, [sp, #6, mul vl] // 16-byte Folded Reload367; CHECK-NEXT: ldr z16, [sp, #7, mul vl] // 16-byte Folded Reload368; CHECK-NEXT: ldr z15, [sp, #8, mul vl] // 16-byte Folded Reload369; CHECK-NEXT: ldr z14, [sp, #9, mul vl] // 16-byte Folded Reload370; CHECK-NEXT: ldr z13, [sp, #10, mul vl] // 16-byte Folded Reload371; CHECK-NEXT: ldr z12, [sp, #11, mul vl] // 16-byte Folded Reload372; CHECK-NEXT: ldr z11, [sp, #12, mul vl] // 16-byte Folded Reload373; CHECK-NEXT: ldr z10, [sp, #13, mul vl] // 16-byte Folded Reload374; CHECK-NEXT: ldr z9, [sp, #14, mul vl] // 16-byte Folded Reload375; CHECK-NEXT: ldr z8, [sp, #15, mul vl] // 16-byte Folded Reload376; CHECK-NEXT: add sp, sp, #1024377; CHECK-NEXT: addvl sp, sp, #17378; CHECK-NEXT: ldr p15, [sp, #4, mul vl] // 2-byte Reload379; CHECK-NEXT: ldr p14, [sp, #5, mul vl] // 2-byte Reload380; CHECK-NEXT: ldr p13, [sp, #6, mul vl] // 2-byte Reload381; CHECK-NEXT: ldr p12, [sp, #7, mul vl] // 2-byte Reload382; CHECK-NEXT: ldr p11, [sp, #8, mul vl] // 2-byte Reload383; CHECK-NEXT: ldr p10, [sp, #9, mul vl] // 2-byte Reload384; CHECK-NEXT: ldr p9, [sp, #10, mul vl] // 2-byte Reload385; CHECK-NEXT: ldr p8, [sp, #11, mul vl] // 2-byte Reload386; CHECK-NEXT: ldr p7, [sp, #12, mul vl] // 2-byte Reload387; CHECK-NEXT: ldr p6, [sp, #13, mul vl] // 2-byte Reload388; CHECK-NEXT: ldr p5, [sp, #14, mul vl] // 2-byte Reload389; CHECK-NEXT: ldr p4, [sp, #15, mul vl] // 2-byte Reload390; CHECK-NEXT: addvl sp, sp, #2391; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload392; CHECK-NEXT: ret393 %ppr_local = alloca <vscale x 16 x i1>394 %zpr_local = alloca <vscale x 16 x i8>395 %fpr_local = alloca double396 ; // Needed to sort %fpr_local into the FPR region397 store double %fp, ptr %fpr_local398 ; // Needed to sort %ppr_local into the PPR region399 store <vscale x 16 x i1> %pred, ptr %ppr_local400 %gpr_local = alloca i64401 call void @foo(ptr %ppr_local, ptr %zpr_local, ptr %fpr_local, ptr %gpr_local)402 ret void403}404declare void @foo(ptr, ptr, ptr, ptr)405 406; CHECK-FRAMELAYOUT-LABEL: Function: all_stack_areas_fp407; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-16], Type: Spill, Align: 16, Size: 8408; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-24], Type: Spill, Align: 8, Size: 8409; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-32], Type: Spill, Align: 8, Size: 8410; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-32-2 x vscale], Type: Spill, Align: 2, Size: vscale x 2411; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-32-4 x vscale], Type: Spill, Align: 2, Size: vscale x 2412; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-32-6 x vscale], Type: Spill, Align: 2, Size: vscale x 2413; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-32-8 x vscale], Type: Spill, Align: 2, Size: vscale x 2414; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-32-10 x vscale], Type: Spill, Align: 2, Size: vscale x 2415; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-32-12 x vscale], Type: Spill, Align: 2, Size: vscale x 2416; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-32-14 x vscale], Type: Spill, Align: 2, Size: vscale x 2417; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-32-16 x vscale], Type: Spill, Align: 2, Size: vscale x 2418; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-32-18 x vscale], Type: Spill, Align: 2, Size: vscale x 2419; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-32-20 x vscale], Type: Spill, Align: 2, Size: vscale x 2420; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-32-22 x vscale], Type: Spill, Align: 2, Size: vscale x 2421; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-32-24 x vscale], Type: Spill, Align: 2, Size: vscale x 2422; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-32-34 x vscale], Type: Variable, Align: 2, Size: vscale x 2423; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-1056-64 x vscale], Type: Spill, Align: 16, Size: vscale x 16424; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-1056-80 x vscale], Type: Spill, Align: 16, Size: vscale x 16425; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-1056-96 x vscale], Type: Spill, Align: 16, Size: vscale x 16426; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-1056-112 x vscale], Type: Spill, Align: 16, Size: vscale x 16427; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-1056-128 x vscale], Type: Spill, Align: 16, Size: vscale x 16428; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-1056-144 x vscale], Type: Spill, Align: 16, Size: vscale x 16429; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-1056-160 x vscale], Type: Spill, Align: 16, Size: vscale x 16430; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-1056-176 x vscale], Type: Spill, Align: 16, Size: vscale x 16431; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-1056-192 x vscale], Type: Spill, Align: 16, Size: vscale x 16432; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-1056-208 x vscale], Type: Spill, Align: 16, Size: vscale x 16433; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-1056-224 x vscale], Type: Spill, Align: 16, Size: vscale x 16434; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-1056-240 x vscale], Type: Spill, Align: 16, Size: vscale x 16435; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-1056-256 x vscale], Type: Spill, Align: 16, Size: vscale x 16436; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-1056-272 x vscale], Type: Spill, Align: 16, Size: vscale x 16437; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-1056-288 x vscale], Type: Spill, Align: 16, Size: vscale x 16438; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-1056-304 x vscale], Type: Spill, Align: 16, Size: vscale x 16439; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-1056-320 x vscale], Type: Variable, Align: 16, Size: vscale x 16440; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-1064-320 x vscale], Type: Variable, Align: 8, Size: 8441; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-2096-320 x vscale], Type: Variable, Align: 16, Size: 1024442; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-2104-320 x vscale], Type: Variable, Align: 8, Size: 8443 444; <CS GPRs>445; -> fp446; <CS PPRs> fp-32*vscale447; %ppr_local fp-34*vscale (addpl #-17)448; 14 * vscale bytes of padding fp-48*vscale449; <hazard padding> fp-1024-48*vscale450; <CS ZPRs> fp-1024-304*vscale451; %zpr_local sp-1024-320*vscale (addvl #-20)452; %fpr_local sp+1048453; 8 bytes of padding sp+1040454; <hazard padding> sp+16455; %gpr_local sp+8456; 8 bytes of padding sp457; -> sp458define void @all_stack_areas_fp(<vscale x 16 x i1> %pred, double %fp) "frame-pointer"="all" {459; CHECK-LABEL: all_stack_areas_fp:460; CHECK: // %bb.0:461; CHECK-NEXT: stp x29, x30, [sp, #-32]! // 16-byte Folded Spill462; CHECK-NEXT: str x28, [sp, #16] // 8-byte Spill463; CHECK-NEXT: mov x29, sp464; CHECK-NEXT: addvl sp, sp, #-2465; CHECK-NEXT: str p15, [sp, #4, mul vl] // 2-byte Spill466; CHECK-NEXT: str p14, [sp, #5, mul vl] // 2-byte Spill467; CHECK-NEXT: str p13, [sp, #6, mul vl] // 2-byte Spill468; CHECK-NEXT: str p12, [sp, #7, mul vl] // 2-byte Spill469; CHECK-NEXT: str p11, [sp, #8, mul vl] // 2-byte Spill470; CHECK-NEXT: str p10, [sp, #9, mul vl] // 2-byte Spill471; CHECK-NEXT: str p9, [sp, #10, mul vl] // 2-byte Spill472; CHECK-NEXT: str p8, [sp, #11, mul vl] // 2-byte Spill473; CHECK-NEXT: str p7, [sp, #12, mul vl] // 2-byte Spill474; CHECK-NEXT: str p6, [sp, #13, mul vl] // 2-byte Spill475; CHECK-NEXT: str p5, [sp, #14, mul vl] // 2-byte Spill476; CHECK-NEXT: str p4, [sp, #15, mul vl] // 2-byte Spill477; CHECK-NEXT: sub sp, sp, #1024478; CHECK-NEXT: addvl sp, sp, #-17479; CHECK-NEXT: str z23, [sp] // 16-byte Folded Spill480; CHECK-NEXT: str z22, [sp, #1, mul vl] // 16-byte Folded Spill481; CHECK-NEXT: str z21, [sp, #2, mul vl] // 16-byte Folded Spill482; CHECK-NEXT: str z20, [sp, #3, mul vl] // 16-byte Folded Spill483; CHECK-NEXT: str z19, [sp, #4, mul vl] // 16-byte Folded Spill484; CHECK-NEXT: str z18, [sp, #5, mul vl] // 16-byte Folded Spill485; CHECK-NEXT: str z17, [sp, #6, mul vl] // 16-byte Folded Spill486; CHECK-NEXT: str z16, [sp, #7, mul vl] // 16-byte Folded Spill487; CHECK-NEXT: str z15, [sp, #8, mul vl] // 16-byte Folded Spill488; CHECK-NEXT: str z14, [sp, #9, mul vl] // 16-byte Folded Spill489; CHECK-NEXT: str z13, [sp, #10, mul vl] // 16-byte Folded Spill490; CHECK-NEXT: str z12, [sp, #11, mul vl] // 16-byte Folded Spill491; CHECK-NEXT: str z11, [sp, #12, mul vl] // 16-byte Folded Spill492; CHECK-NEXT: str z10, [sp, #13, mul vl] // 16-byte Folded Spill493; CHECK-NEXT: str z9, [sp, #14, mul vl] // 16-byte Folded Spill494; CHECK-NEXT: str z8, [sp, #15, mul vl] // 16-byte Folded Spill495; CHECK-NEXT: sub sp, sp, #1056496; CHECK-NEXT: addvl sp, sp, #-1497; CHECK-NEXT: .cfi_def_cfa w29, 32498; CHECK-NEXT: .cfi_offset w28, -16499; CHECK-NEXT: .cfi_offset w30, -24500; CHECK-NEXT: .cfi_offset w29, -32501; CHECK-NEXT: .cfi_escape 0x10, 0x48, 0x0b, 0x92, 0x2e, 0x00, 0x11, 0x60, 0x1e, 0x22, 0x11, 0xe0, 0x77, 0x22 // $d8 @ cfa - 32 * VG - 1056502; CHECK-NEXT: .cfi_escape 0x10, 0x49, 0x0b, 0x92, 0x2e, 0x00, 0x11, 0x58, 0x1e, 0x22, 0x11, 0xe0, 0x77, 0x22 // $d9 @ cfa - 40 * VG - 1056503; CHECK-NEXT: .cfi_escape 0x10, 0x4a, 0x0b, 0x92, 0x2e, 0x00, 0x11, 0x50, 0x1e, 0x22, 0x11, 0xe0, 0x77, 0x22 // $d10 @ cfa - 48 * VG - 1056504; CHECK-NEXT: .cfi_escape 0x10, 0x4b, 0x0b, 0x92, 0x2e, 0x00, 0x11, 0x48, 0x1e, 0x22, 0x11, 0xe0, 0x77, 0x22 // $d11 @ cfa - 56 * VG - 1056505; CHECK-NEXT: .cfi_escape 0x10, 0x4c, 0x0b, 0x92, 0x2e, 0x00, 0x11, 0x40, 0x1e, 0x22, 0x11, 0xe0, 0x77, 0x22 // $d12 @ cfa - 64 * VG - 1056506; CHECK-NEXT: .cfi_escape 0x10, 0x4d, 0x0c, 0x92, 0x2e, 0x00, 0x11, 0xb8, 0x7f, 0x1e, 0x22, 0x11, 0xe0, 0x77, 0x22 // $d13 @ cfa - 72 * VG - 1056507; CHECK-NEXT: .cfi_escape 0x10, 0x4e, 0x0c, 0x92, 0x2e, 0x00, 0x11, 0xb0, 0x7f, 0x1e, 0x22, 0x11, 0xe0, 0x77, 0x22 // $d14 @ cfa - 80 * VG - 1056508; CHECK-NEXT: .cfi_escape 0x10, 0x4f, 0x0c, 0x92, 0x2e, 0x00, 0x11, 0xa8, 0x7f, 0x1e, 0x22, 0x11, 0xe0, 0x77, 0x22 // $d15 @ cfa - 88 * VG - 1056509; CHECK-NEXT: sub x1, x29, #1024510; CHECK-NEXT: addpl x0, x29, #-17511; CHECK-NEXT: add x2, sp, #1048512; CHECK-NEXT: addvl x1, x1, #-20513; CHECK-NEXT: add x3, sp, #8514; CHECK-NEXT: str d0, [sp, #1048]515; CHECK-NEXT: str p0, [x29, #-17, mul vl]516; CHECK-NEXT: bl foo517; CHECK-NEXT: add sp, sp, #1056518; CHECK-NEXT: addvl sp, sp, #1519; CHECK-NEXT: ldr z23, [sp] // 16-byte Folded Reload520; CHECK-NEXT: ldr z22, [sp, #1, mul vl] // 16-byte Folded Reload521; CHECK-NEXT: ldr z21, [sp, #2, mul vl] // 16-byte Folded Reload522; CHECK-NEXT: ldr z20, [sp, #3, mul vl] // 16-byte Folded Reload523; CHECK-NEXT: ldr z19, [sp, #4, mul vl] // 16-byte Folded Reload524; CHECK-NEXT: ldr z18, [sp, #5, mul vl] // 16-byte Folded Reload525; CHECK-NEXT: ldr z17, [sp, #6, mul vl] // 16-byte Folded Reload526; CHECK-NEXT: ldr z16, [sp, #7, mul vl] // 16-byte Folded Reload527; CHECK-NEXT: ldr z15, [sp, #8, mul vl] // 16-byte Folded Reload528; CHECK-NEXT: ldr z14, [sp, #9, mul vl] // 16-byte Folded Reload529; CHECK-NEXT: ldr z13, [sp, #10, mul vl] // 16-byte Folded Reload530; CHECK-NEXT: ldr z12, [sp, #11, mul vl] // 16-byte Folded Reload531; CHECK-NEXT: ldr z11, [sp, #12, mul vl] // 16-byte Folded Reload532; CHECK-NEXT: ldr z10, [sp, #13, mul vl] // 16-byte Folded Reload533; CHECK-NEXT: ldr z9, [sp, #14, mul vl] // 16-byte Folded Reload534; CHECK-NEXT: ldr z8, [sp, #15, mul vl] // 16-byte Folded Reload535; CHECK-NEXT: add sp, sp, #1024536; CHECK-NEXT: addvl sp, sp, #17537; CHECK-NEXT: ldr p15, [sp, #4, mul vl] // 2-byte Reload538; CHECK-NEXT: ldr p14, [sp, #5, mul vl] // 2-byte Reload539; CHECK-NEXT: ldr p13, [sp, #6, mul vl] // 2-byte Reload540; CHECK-NEXT: ldr p12, [sp, #7, mul vl] // 2-byte Reload541; CHECK-NEXT: ldr p11, [sp, #8, mul vl] // 2-byte Reload542; CHECK-NEXT: ldr p10, [sp, #9, mul vl] // 2-byte Reload543; CHECK-NEXT: ldr p9, [sp, #10, mul vl] // 2-byte Reload544; CHECK-NEXT: ldr p8, [sp, #11, mul vl] // 2-byte Reload545; CHECK-NEXT: ldr p7, [sp, #12, mul vl] // 2-byte Reload546; CHECK-NEXT: ldr p6, [sp, #13, mul vl] // 2-byte Reload547; CHECK-NEXT: ldr p5, [sp, #14, mul vl] // 2-byte Reload548; CHECK-NEXT: ldr p4, [sp, #15, mul vl] // 2-byte Reload549; CHECK-NEXT: addvl sp, sp, #2550; CHECK-NEXT: ldr x28, [sp, #16] // 8-byte Reload551; CHECK-NEXT: ldp x29, x30, [sp], #32 // 16-byte Folded Reload552; CHECK-NEXT: ret553 %ppr_local = alloca <vscale x 16 x i1>554 %zpr_local = alloca <vscale x 16 x i8>555 %fpr_local = alloca double556 ; // Needed to sort %fpr_local into the FPR region557 store double %fp, ptr %fpr_local558 ; // Needed to sort %ppr_local into the PPR region559 store <vscale x 16 x i1> %pred, ptr %ppr_local560 %gpr_local = alloca i64561 call void @foo(ptr %ppr_local, ptr %zpr_local, ptr %fpr_local, ptr %gpr_local)562 ret void563}564 565; CHECK-FRAMELAYOUT-LABEL: Function: svecc_call566; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-8], Type: Spill, Align: 8, Size: 8567; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-16], Type: Spill, Align: 8, Size: 8568; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-24], Type: Spill, Align: 8, Size: 8569; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-32], Type: Spill, Align: 8, Size: 8570; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-48], Type: Spill, Align: 16, Size: 8571; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-56], Type: Spill, Align: 8, Size: 8572; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-64], Type: Spill, Align: 8, Size: 8573; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-64-2 x vscale], Type: Spill, Align: 2, Size: vscale x 2574; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-64-4 x vscale], Type: Spill, Align: 2, Size: vscale x 2575; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-64-6 x vscale], Type: Spill, Align: 2, Size: vscale x 2576; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-64-8 x vscale], Type: Spill, Align: 2, Size: vscale x 2577; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-64-10 x vscale], Type: Spill, Align: 2, Size: vscale x 2578; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-64-12 x vscale], Type: Spill, Align: 2, Size: vscale x 2579; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-64-14 x vscale], Type: Spill, Align: 2, Size: vscale x 2580; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-64-16 x vscale], Type: Spill, Align: 2, Size: vscale x 2581; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-64-18 x vscale], Type: Spill, Align: 2, Size: vscale x 2582; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-64-20 x vscale], Type: Spill, Align: 2, Size: vscale x 2583; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-64-22 x vscale], Type: Spill, Align: 2, Size: vscale x 2584; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-64-24 x vscale], Type: Spill, Align: 2, Size: vscale x 2585; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-1088-48 x vscale], Type: Spill, Align: 16, Size: vscale x 16586; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-1088-64 x vscale], Type: Spill, Align: 16, Size: vscale x 16587; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-1088-80 x vscale], Type: Spill, Align: 16, Size: vscale x 16588; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-1088-96 x vscale], Type: Spill, Align: 16, Size: vscale x 16589; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-1088-112 x vscale], Type: Spill, Align: 16, Size: vscale x 16590; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-1088-128 x vscale], Type: Spill, Align: 16, Size: vscale x 16591; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-1088-144 x vscale], Type: Spill, Align: 16, Size: vscale x 16592; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-1088-160 x vscale], Type: Spill, Align: 16, Size: vscale x 16593; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-1088-176 x vscale], Type: Spill, Align: 16, Size: vscale x 16594; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-1088-192 x vscale], Type: Spill, Align: 16, Size: vscale x 16595; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-1088-208 x vscale], Type: Spill, Align: 16, Size: vscale x 16596; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-1088-224 x vscale], Type: Spill, Align: 16, Size: vscale x 16597; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-1088-240 x vscale], Type: Spill, Align: 16, Size: vscale x 16598; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-1088-256 x vscale], Type: Spill, Align: 16, Size: vscale x 16599; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-1088-272 x vscale], Type: Spill, Align: 16, Size: vscale x 16600; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-1088-288 x vscale], Type: Spill, Align: 16, Size: vscale x 16601; CHECK-FRAMELAYOUT-NEXT: Offset: [SP-2112-288 x vscale], Type: Variable, Align: 16, Size: 1024602 603define i32 @svecc_call(<4 x i16> %P0, ptr %P1, i32 %P2, <vscale x 16 x i8> %P3, i16 %P4) "aarch64_pstate_sm_compatible" {604; CHECK-LABEL: svecc_call:605; CHECK: // %bb.0: // %entry606; CHECK-NEXT: stp x29, x30, [sp, #-64]! // 16-byte Folded Spill607; CHECK-NEXT: .cfi_def_cfa_offset 64608; CHECK-NEXT: cntd x9609; CHECK-NEXT: stp x28, x27, [sp, #32] // 16-byte Folded Spill610; CHECK-NEXT: str x9, [sp, #16] // 8-byte Spill611; CHECK-NEXT: stp x26, x19, [sp, #48] // 16-byte Folded Spill612; CHECK-NEXT: mov x29, sp613; CHECK-NEXT: .cfi_def_cfa w29, 64614; CHECK-NEXT: .cfi_offset w19, -8615; CHECK-NEXT: .cfi_offset w26, -16616; CHECK-NEXT: .cfi_offset w27, -24617; CHECK-NEXT: .cfi_offset w28, -32618; CHECK-NEXT: .cfi_offset vg, -48619; CHECK-NEXT: .cfi_offset w30, -56620; CHECK-NEXT: .cfi_offset w29, -64621; CHECK-NEXT: addvl sp, sp, #-2622; CHECK-NEXT: str p15, [sp, #4, mul vl] // 2-byte Spill623; CHECK-NEXT: str p14, [sp, #5, mul vl] // 2-byte Spill624; CHECK-NEXT: str p13, [sp, #6, mul vl] // 2-byte Spill625; CHECK-NEXT: str p12, [sp, #7, mul vl] // 2-byte Spill626; CHECK-NEXT: str p11, [sp, #8, mul vl] // 2-byte Spill627; CHECK-NEXT: str p10, [sp, #9, mul vl] // 2-byte Spill628; CHECK-NEXT: str p9, [sp, #10, mul vl] // 2-byte Spill629; CHECK-NEXT: str p8, [sp, #11, mul vl] // 2-byte Spill630; CHECK-NEXT: str p7, [sp, #12, mul vl] // 2-byte Spill631; CHECK-NEXT: str p6, [sp, #13, mul vl] // 2-byte Spill632; CHECK-NEXT: str p5, [sp, #14, mul vl] // 2-byte Spill633; CHECK-NEXT: str p4, [sp, #15, mul vl] // 2-byte Spill634; CHECK-NEXT: sub sp, sp, #1024635; CHECK-NEXT: addvl sp, sp, #-16636; CHECK-NEXT: str z23, [sp] // 16-byte Folded Spill637; CHECK-NEXT: str z22, [sp, #1, mul vl] // 16-byte Folded Spill638; CHECK-NEXT: str z21, [sp, #2, mul vl] // 16-byte Folded Spill639; CHECK-NEXT: str z20, [sp, #3, mul vl] // 16-byte Folded Spill640; CHECK-NEXT: str z19, [sp, #4, mul vl] // 16-byte Folded Spill641; CHECK-NEXT: str z18, [sp, #5, mul vl] // 16-byte Folded Spill642; CHECK-NEXT: str z17, [sp, #6, mul vl] // 16-byte Folded Spill643; CHECK-NEXT: str z16, [sp, #7, mul vl] // 16-byte Folded Spill644; CHECK-NEXT: str z15, [sp, #8, mul vl] // 16-byte Folded Spill645; CHECK-NEXT: str z14, [sp, #9, mul vl] // 16-byte Folded Spill646; CHECK-NEXT: str z13, [sp, #10, mul vl] // 16-byte Folded Spill647; CHECK-NEXT: str z12, [sp, #11, mul vl] // 16-byte Folded Spill648; CHECK-NEXT: str z11, [sp, #12, mul vl] // 16-byte Folded Spill649; CHECK-NEXT: str z10, [sp, #13, mul vl] // 16-byte Folded Spill650; CHECK-NEXT: str z9, [sp, #14, mul vl] // 16-byte Folded Spill651; CHECK-NEXT: str z8, [sp, #15, mul vl] // 16-byte Folded Spill652; CHECK-NEXT: .cfi_escape 0x10, 0x48, 0x0d, 0x12, 0x11, 0x50, 0x22, 0x06, 0x11, 0x68, 0x1e, 0x22, 0x11, 0xc0, 0x77, 0x22 // $d8 @ cfa - 24 * IncomingVG - 1088653; CHECK-NEXT: .cfi_escape 0x10, 0x49, 0x0d, 0x12, 0x11, 0x50, 0x22, 0x06, 0x11, 0x60, 0x1e, 0x22, 0x11, 0xc0, 0x77, 0x22 // $d9 @ cfa - 32 * IncomingVG - 1088654; CHECK-NEXT: .cfi_escape 0x10, 0x4a, 0x0d, 0x12, 0x11, 0x50, 0x22, 0x06, 0x11, 0x58, 0x1e, 0x22, 0x11, 0xc0, 0x77, 0x22 // $d10 @ cfa - 40 * IncomingVG - 1088655; CHECK-NEXT: .cfi_escape 0x10, 0x4b, 0x0d, 0x12, 0x11, 0x50, 0x22, 0x06, 0x11, 0x50, 0x1e, 0x22, 0x11, 0xc0, 0x77, 0x22 // $d11 @ cfa - 48 * IncomingVG - 1088656; CHECK-NEXT: .cfi_escape 0x10, 0x4c, 0x0d, 0x12, 0x11, 0x50, 0x22, 0x06, 0x11, 0x48, 0x1e, 0x22, 0x11, 0xc0, 0x77, 0x22 // $d12 @ cfa - 56 * IncomingVG - 1088657; CHECK-NEXT: .cfi_escape 0x10, 0x4d, 0x0d, 0x12, 0x11, 0x50, 0x22, 0x06, 0x11, 0x40, 0x1e, 0x22, 0x11, 0xc0, 0x77, 0x22 // $d13 @ cfa - 64 * IncomingVG - 1088658; CHECK-NEXT: .cfi_escape 0x10, 0x4e, 0x0e, 0x12, 0x11, 0x50, 0x22, 0x06, 0x11, 0xb8, 0x7f, 0x1e, 0x22, 0x11, 0xc0, 0x77, 0x22 // $d14 @ cfa - 72 * IncomingVG - 1088659; CHECK-NEXT: .cfi_escape 0x10, 0x4f, 0x0e, 0x12, 0x11, 0x50, 0x22, 0x06, 0x11, 0xb0, 0x7f, 0x1e, 0x22, 0x11, 0xc0, 0x77, 0x22 // $d15 @ cfa - 80 * IncomingVG - 1088660; CHECK-NEXT: sub sp, sp, #1024661; CHECK-NEXT: mov x8, x0662; CHECK-NEXT: bl __arm_sme_state663; CHECK-NEXT: mov x19, x0664; CHECK-NEXT: //APP665; CHECK-NEXT: //NO_APP666; CHECK-NEXT: tbz w19, #0, .LBB8_2667; CHECK-NEXT: // %bb.1: // %entry668; CHECK-NEXT: smstop sm669; CHECK-NEXT: .LBB8_2: // %entry670; CHECK-NEXT: mov x0, x8671; CHECK-NEXT: mov w1, #45 // =0x2d672; CHECK-NEXT: mov w2, #37 // =0x25673; CHECK-NEXT: bl memset674; CHECK-NEXT: tbz w19, #0, .LBB8_4675; CHECK-NEXT: // %bb.3: // %entry676; CHECK-NEXT: smstart sm677; CHECK-NEXT: .LBB8_4: // %entry678; CHECK-NEXT: mov w0, #22647 // =0x5877679; CHECK-NEXT: movk w0, #59491, lsl #16680; CHECK-NEXT: add sp, sp, #1024681; CHECK-NEXT: ldr z23, [sp] // 16-byte Folded Reload682; CHECK-NEXT: ldr z22, [sp, #1, mul vl] // 16-byte Folded Reload683; CHECK-NEXT: ldr z21, [sp, #2, mul vl] // 16-byte Folded Reload684; CHECK-NEXT: ldr z20, [sp, #3, mul vl] // 16-byte Folded Reload685; CHECK-NEXT: ldr z19, [sp, #4, mul vl] // 16-byte Folded Reload686; CHECK-NEXT: ldr z18, [sp, #5, mul vl] // 16-byte Folded Reload687; CHECK-NEXT: ldr z17, [sp, #6, mul vl] // 16-byte Folded Reload688; CHECK-NEXT: ldr z16, [sp, #7, mul vl] // 16-byte Folded Reload689; CHECK-NEXT: ldr z15, [sp, #8, mul vl] // 16-byte Folded Reload690; CHECK-NEXT: ldr z14, [sp, #9, mul vl] // 16-byte Folded Reload691; CHECK-NEXT: ldr z13, [sp, #10, mul vl] // 16-byte Folded Reload692; CHECK-NEXT: ldr z12, [sp, #11, mul vl] // 16-byte Folded Reload693; CHECK-NEXT: ldr z11, [sp, #12, mul vl] // 16-byte Folded Reload694; CHECK-NEXT: ldr z10, [sp, #13, mul vl] // 16-byte Folded Reload695; CHECK-NEXT: ldr z9, [sp, #14, mul vl] // 16-byte Folded Reload696; CHECK-NEXT: ldr z8, [sp, #15, mul vl] // 16-byte Folded Reload697; CHECK-NEXT: add sp, sp, #1024698; CHECK-NEXT: addvl sp, sp, #16699; CHECK-NEXT: .cfi_restore z8700; CHECK-NEXT: .cfi_restore z9701; CHECK-NEXT: .cfi_restore z10702; CHECK-NEXT: .cfi_restore z11703; CHECK-NEXT: .cfi_restore z12704; CHECK-NEXT: .cfi_restore z13705; CHECK-NEXT: .cfi_restore z14706; CHECK-NEXT: .cfi_restore z15707; CHECK-NEXT: ldr p15, [sp, #4, mul vl] // 2-byte Reload708; CHECK-NEXT: ldr p14, [sp, #5, mul vl] // 2-byte Reload709; CHECK-NEXT: ldr p13, [sp, #6, mul vl] // 2-byte Reload710; CHECK-NEXT: ldr p12, [sp, #7, mul vl] // 2-byte Reload711; CHECK-NEXT: ldr p11, [sp, #8, mul vl] // 2-byte Reload712; CHECK-NEXT: ldr p10, [sp, #9, mul vl] // 2-byte Reload713; CHECK-NEXT: ldr p9, [sp, #10, mul vl] // 2-byte Reload714; CHECK-NEXT: ldr p8, [sp, #11, mul vl] // 2-byte Reload715; CHECK-NEXT: ldr p7, [sp, #12, mul vl] // 2-byte Reload716; CHECK-NEXT: ldr p6, [sp, #13, mul vl] // 2-byte Reload717; CHECK-NEXT: ldr p5, [sp, #14, mul vl] // 2-byte Reload718; CHECK-NEXT: ldr p4, [sp, #15, mul vl] // 2-byte Reload719; CHECK-NEXT: addvl sp, sp, #2720; CHECK-NEXT: .cfi_def_cfa wsp, 64721; CHECK-NEXT: ldp x26, x19, [sp, #48] // 16-byte Folded Reload722; CHECK-NEXT: ldp x28, x27, [sp, #32] // 16-byte Folded Reload723; CHECK-NEXT: ldp x29, x30, [sp], #64 // 16-byte Folded Reload724; CHECK-NEXT: .cfi_def_cfa_offset 0725; CHECK-NEXT: .cfi_restore w19726; CHECK-NEXT: .cfi_restore w26727; CHECK-NEXT: .cfi_restore w27728; CHECK-NEXT: .cfi_restore w28729; CHECK-NEXT: .cfi_restore vg730; CHECK-NEXT: .cfi_restore w30731; CHECK-NEXT: .cfi_restore w29732; CHECK-NEXT: ret733entry:734 tail call void asm sideeffect "", "~{x0},~{x28},~{x27},~{x3}"() #2735 %call = call ptr @memset(ptr noundef nonnull %P1, i32 noundef 45, i32 noundef 37)736 ret i32 -396142473737}738declare ptr @memset(ptr, i32, i32)739 740define void @zpr_and_ppr_local_realignment(<vscale x 16 x i1> %pred, <vscale x 16 x i8> %vector, i64 %gpr) "aarch64_pstate_sm_compatible" {741; CHECK-LABEL: zpr_and_ppr_local_realignment:742; CHECK: // %bb.0:743; CHECK-NEXT: stp x29, x30, [sp, #-16]! // 16-byte Folded Spill744; CHECK-NEXT: sub x9, sp, #2064745; CHECK-NEXT: mov x29, sp746; CHECK-NEXT: addvl x9, x9, #-2747; CHECK-NEXT: and sp, x9, #0xffffffffffffffe0748; CHECK-NEXT: .cfi_def_cfa w29, 16749; CHECK-NEXT: .cfi_offset w30, -8750; CHECK-NEXT: .cfi_offset w29, -16751; CHECK-NEXT: sub x8, x29, #1024752; CHECK-NEXT: str p0, [x29, #-1, mul vl]753; CHECK-NEXT: str z0, [x8, #-2, mul vl]754; CHECK-NEXT: str x0, [sp]755; CHECK-NEXT: mov sp, x29756; CHECK-NEXT: ldp x29, x30, [sp], #16 // 16-byte Folded Reload757; CHECK-NEXT: ret758 %ppr_local = alloca <vscale x 16 x i1>759 %zpr_local = alloca <vscale x 16 x i8>760 %gpr_local = alloca i64, align 32761 store volatile <vscale x 16 x i1> %pred, ptr %ppr_local762 store volatile <vscale x 16 x i8> %vector, ptr %zpr_local763 store volatile i64 %gpr, ptr %gpr_local764 ret void765}766 767define void @zpr_and_ppr_local_stack_probing(<vscale x 16 x i1> %pred, <vscale x 16 x i8> %vector, i64 %gpr)768; CHECK-LABEL: zpr_and_ppr_local_stack_probing:769; CHECK: // %bb.0:770; CHECK-NEXT: str x29, [sp, #-16]! // 8-byte Folded Spill771; CHECK-NEXT: sub sp, sp, #2848772; CHECK-NEXT: addvl sp, sp, #-2773; CHECK-NEXT: str xzr, [sp]774; CHECK-NEXT: .cfi_escape 0x0f, 0x09, 0x8f, 0xb0, 0x16, 0x92, 0x2e, 0x00, 0x40, 0x1e, 0x22 // sp + 2864 + 16 * VG775; CHECK-NEXT: .cfi_offset w29, -16776; CHECK-NEXT: add x8, sp, #2848777; CHECK-NEXT: str p0, [x8, #15, mul vl]778; CHECK-NEXT: add x8, sp, #1824779; CHECK-NEXT: str z0, [x8]780; CHECK-NEXT: str x0, [sp]781; CHECK-NEXT: add sp, sp, #2848782; CHECK-NEXT: addvl sp, sp, #2783; CHECK-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload784; CHECK-NEXT: ret785 "probe-stack"="inline-asm" "stack-probe-size"="4096" "frame-pointer"="none" "aarch64_pstate_sm_compatible"786{787 %ppr_local = alloca <vscale x 16 x i1>788 %zpr_local = alloca <vscale x 16 x i8>789 %gpr_local = alloca i64, i64 100, align 8790 store volatile <vscale x 16 x i1> %pred, ptr %ppr_local791 store volatile <vscale x 16 x i8> %vector, ptr %zpr_local792 store volatile i64 %gpr, ptr %gpr_local793 ret void794}795 796; Only PPR callee-saves + a VLA797; Expect: No hazard padding. Frame pointer (x29), p4-p6 callee saves allocated798; with `addvl #-1`, PPR saves restored using frame pointer `addvl sp, x29, #-1`.799define aarch64_sve_vector_pcs void @only_ppr_csr_vla(i64 %n) {800; CHECK-LABEL: only_ppr_csr_vla:801; CHECK: // %bb.0:802; CHECK-NEXT: stp x29, x30, [sp, #-32]! // 16-byte Folded Spill803; CHECK-NEXT: str x19, [sp, #16] // 8-byte Spill804; CHECK-NEXT: mov x29, sp805; CHECK-NEXT: addvl sp, sp, #-1806; CHECK-NEXT: str p6, [sp, #5, mul vl] // 2-byte Spill807; CHECK-NEXT: str p5, [sp, #6, mul vl] // 2-byte Spill808; CHECK-NEXT: str p4, [sp, #7, mul vl] // 2-byte Spill809; CHECK-NEXT: mov x19, sp810; CHECK-NEXT: .cfi_def_cfa w29, 32811; CHECK-NEXT: .cfi_offset w19, -16812; CHECK-NEXT: .cfi_offset w30, -24813; CHECK-NEXT: .cfi_offset w29, -32814; CHECK-NEXT: add x9, x0, #15815; CHECK-NEXT: mov x8, sp816; CHECK-NEXT: and x9, x9, #0xfffffffffffffff0817; CHECK-NEXT: sub x8, x8, x9818; CHECK-NEXT: mov sp, x8819; CHECK-NEXT: // fake_use: $x8820; CHECK-NEXT: //APP821; CHECK-NEXT: //NO_APP822; CHECK-NEXT: addvl sp, x29, #-1823; CHECK-NEXT: ldr p6, [sp, #5, mul vl] // 2-byte Reload824; CHECK-NEXT: ldr p5, [sp, #6, mul vl] // 2-byte Reload825; CHECK-NEXT: ldr p4, [sp, #7, mul vl] // 2-byte Reload826; CHECK-NEXT: mov sp, x29827; CHECK-NEXT: ldr x19, [sp, #16] // 8-byte Reload828; CHECK-NEXT: ldp x29, x30, [sp], #32 // 16-byte Folded Reload829; CHECK-NEXT: ret830 %alloc = alloca i8, i64 %n, align 1831 call void (...) @llvm.fake.use(ptr %alloc)832 tail call void asm sideeffect "", "~{p4},~{p5},~{p6}"()833 ret void834}835 836; Only ZPR callee-saves + a VLA837; Expect: Hazard padding, Frame pointer (x29), z8-z10 callee saves allocated838; with `addvl #-3`. ZPR saves restored from `FP - 1024 + addvl #-3`.839define aarch64_sve_vector_pcs void @only_zpr_csr_vla(i64 %n) {840; CHECK-LABEL: only_zpr_csr_vla:841; CHECK: // %bb.0:842; CHECK-NEXT: stp x29, x30, [sp, #-32]! // 16-byte Folded Spill843; CHECK-NEXT: str x19, [sp, #16] // 8-byte Spill844; CHECK-NEXT: mov x29, sp845; CHECK-NEXT: sub sp, sp, #1024846; CHECK-NEXT: addvl sp, sp, #-3847; CHECK-NEXT: str z10, [sp] // 16-byte Folded Spill848; CHECK-NEXT: str z9, [sp, #1, mul vl] // 16-byte Folded Spill849; CHECK-NEXT: str z8, [sp, #2, mul vl] // 16-byte Folded Spill850; CHECK-NEXT: sub sp, sp, #1024851; CHECK-NEXT: mov x19, sp852; CHECK-NEXT: .cfi_def_cfa w29, 32853; CHECK-NEXT: .cfi_offset w19, -16854; CHECK-NEXT: .cfi_offset w30, -24855; CHECK-NEXT: .cfi_offset w29, -32856; CHECK-NEXT: .cfi_escape 0x10, 0x48, 0x0b, 0x92, 0x2e, 0x00, 0x11, 0x78, 0x1e, 0x22, 0x11, 0xe0, 0x77, 0x22 // $d8 @ cfa - 8 * VG - 1056857; CHECK-NEXT: .cfi_escape 0x10, 0x49, 0x0b, 0x92, 0x2e, 0x00, 0x11, 0x70, 0x1e, 0x22, 0x11, 0xe0, 0x77, 0x22 // $d9 @ cfa - 16 * VG - 1056858; CHECK-NEXT: .cfi_escape 0x10, 0x4a, 0x0b, 0x92, 0x2e, 0x00, 0x11, 0x68, 0x1e, 0x22, 0x11, 0xe0, 0x77, 0x22 // $d10 @ cfa - 24 * VG - 1056859; CHECK-NEXT: add x9, x0, #15860; CHECK-NEXT: mov x8, sp861; CHECK-NEXT: and x9, x9, #0xfffffffffffffff0862; CHECK-NEXT: sub x8, x8, x9863; CHECK-NEXT: mov sp, x8864; CHECK-NEXT: // fake_use: $x8865; CHECK-NEXT: sub x8, x29, #1024866; CHECK-NEXT: //APP867; CHECK-NEXT: //NO_APP868; CHECK-NEXT: addvl sp, x8, #-3869; CHECK-NEXT: ldr z10, [sp] // 16-byte Folded Reload870; CHECK-NEXT: ldr z9, [sp, #1, mul vl] // 16-byte Folded Reload871; CHECK-NEXT: ldr z8, [sp, #2, mul vl] // 16-byte Folded Reload872; CHECK-NEXT: mov sp, x29873; CHECK-NEXT: ldr x19, [sp, #16] // 8-byte Reload874; CHECK-NEXT: ldp x29, x30, [sp], #32 // 16-byte Folded Reload875; CHECK-NEXT: ret876 %alloc = alloca i8, i64 %n, align 1877 call void (...) @llvm.fake.use(ptr %alloc)878 tail call void asm sideeffect "", "~{z8},~{z9},~{z10}"()879 ret void880}881 882; PPR+ZPR callee-saves + a VLA883; Expect: Hazard padding, Frame pointer (x29), PPR (p4-p6) and ZPR (z8-z10)884; callee-saves allocated separately, with hazard padding of 1024 between the885; areas. ZPR callee saves restored by `FP - 1024 + addvl #-4`, PPR callee saves886; restored by `FP + addvl #-1`.887define aarch64_sve_vector_pcs void @zpr_ppr_csr_vla(i64 %n) {888; CHECK-LABEL: zpr_ppr_csr_vla:889; CHECK: // %bb.0:890; CHECK-NEXT: stp x29, x30, [sp, #-32]! // 16-byte Folded Spill891; CHECK-NEXT: str x19, [sp, #16] // 8-byte Spill892; CHECK-NEXT: mov x29, sp893; CHECK-NEXT: addvl sp, sp, #-1894; CHECK-NEXT: str p6, [sp, #5, mul vl] // 2-byte Spill895; CHECK-NEXT: str p5, [sp, #6, mul vl] // 2-byte Spill896; CHECK-NEXT: str p4, [sp, #7, mul vl] // 2-byte Spill897; CHECK-NEXT: sub sp, sp, #1024898; CHECK-NEXT: addvl sp, sp, #-3899; CHECK-NEXT: str z10, [sp] // 16-byte Folded Spill900; CHECK-NEXT: str z9, [sp, #1, mul vl] // 16-byte Folded Spill901; CHECK-NEXT: str z8, [sp, #2, mul vl] // 16-byte Folded Spill902; CHECK-NEXT: sub sp, sp, #1024903; CHECK-NEXT: mov x19, sp904; CHECK-NEXT: .cfi_def_cfa w29, 32905; CHECK-NEXT: .cfi_offset w19, -16906; CHECK-NEXT: .cfi_offset w30, -24907; CHECK-NEXT: .cfi_offset w29, -32908; CHECK-NEXT: .cfi_escape 0x10, 0x48, 0x0b, 0x92, 0x2e, 0x00, 0x11, 0x70, 0x1e, 0x22, 0x11, 0xe0, 0x77, 0x22 // $d8 @ cfa - 16 * VG - 1056909; CHECK-NEXT: .cfi_escape 0x10, 0x49, 0x0b, 0x92, 0x2e, 0x00, 0x11, 0x68, 0x1e, 0x22, 0x11, 0xe0, 0x77, 0x22 // $d9 @ cfa - 24 * VG - 1056910; CHECK-NEXT: .cfi_escape 0x10, 0x4a, 0x0b, 0x92, 0x2e, 0x00, 0x11, 0x60, 0x1e, 0x22, 0x11, 0xe0, 0x77, 0x22 // $d10 @ cfa - 32 * VG - 1056911; CHECK-NEXT: add x9, x0, #15912; CHECK-NEXT: mov x8, sp913; CHECK-NEXT: and x9, x9, #0xfffffffffffffff0914; CHECK-NEXT: sub x8, x8, x9915; CHECK-NEXT: mov sp, x8916; CHECK-NEXT: // fake_use: $x8917; CHECK-NEXT: sub x8, x29, #1024918; CHECK-NEXT: //APP919; CHECK-NEXT: //NO_APP920; CHECK-NEXT: addvl sp, x8, #-4921; CHECK-NEXT: ldr z10, [sp] // 16-byte Folded Reload922; CHECK-NEXT: ldr z9, [sp, #1, mul vl] // 16-byte Folded Reload923; CHECK-NEXT: ldr z8, [sp, #2, mul vl] // 16-byte Folded Reload924; CHECK-NEXT: addvl sp, x29, #-1925; CHECK-NEXT: ldr p6, [sp, #5, mul vl] // 2-byte Reload926; CHECK-NEXT: ldr p5, [sp, #6, mul vl] // 2-byte Reload927; CHECK-NEXT: ldr p4, [sp, #7, mul vl] // 2-byte Reload928; CHECK-NEXT: mov sp, x29929; CHECK-NEXT: ldr x19, [sp, #16] // 8-byte Reload930; CHECK-NEXT: ldp x29, x30, [sp], #32 // 16-byte Folded Reload931; CHECK-NEXT: ret932 %alloc = alloca i8, i64 %n, align 1933 call void (...) @llvm.fake.use(ptr %alloc)934 tail call void asm sideeffect "", "~{p4},~{p5},~{p6},~{z8},~{z9},~{z10}"()935 ret void936}937 938; Only PPR callee-saves (and ZPR/PPR locals) + a VLA939; Expect: Hazard padding, Frame pointer (x29), PPR (p4-p6) callee-saves, with940; hazard padding after the PPR callee saves (1024) and after the FPR local area941; (1024) -- coeleased to 2048. Only PPRs restored by moving the SP to942; `FP + addvl #-1`.943define void @sve_locals_only_ppr_csr_vla(i64 %n, <vscale x 16 x i1> %pred, <vscale x 16 x i8> %vector) {944; CHECK-LABEL: sve_locals_only_ppr_csr_vla:945; CHECK: // %bb.0:946; CHECK-NEXT: stp x29, x30, [sp, #-32]! // 16-byte Folded Spill947; CHECK-NEXT: str x19, [sp, #16] // 8-byte Spill948; CHECK-NEXT: mov x29, sp949; CHECK-NEXT: addvl sp, sp, #-1950; CHECK-NEXT: str p6, [sp, #5, mul vl] // 2-byte Spill951; CHECK-NEXT: str p5, [sp, #6, mul vl] // 2-byte Spill952; CHECK-NEXT: str p4, [sp, #7, mul vl] // 2-byte Spill953; CHECK-NEXT: sub sp, sp, #2048954; CHECK-NEXT: addvl sp, sp, #-2955; CHECK-NEXT: mov x19, sp956; CHECK-NEXT: .cfi_def_cfa w29, 32957; CHECK-NEXT: .cfi_offset w19, -16958; CHECK-NEXT: .cfi_offset w30, -24959; CHECK-NEXT: .cfi_offset w29, -32960; CHECK-NEXT: add x9, x0, #15961; CHECK-NEXT: mov x8, sp962; CHECK-NEXT: and x9, x9, #0xfffffffffffffff0963; CHECK-NEXT: sub x8, x8, x9964; CHECK-NEXT: mov sp, x8965; CHECK-NEXT: // fake_use: $x8966; CHECK-NEXT: sub x8, x29, #1024967; CHECK-NEXT: //APP968; CHECK-NEXT: //NO_APP969; CHECK-NEXT: str p0, [x29, #-9, mul vl]970; CHECK-NEXT: str z0, [x8, #-3, mul vl]971; CHECK-NEXT: addvl sp, x29, #-1972; CHECK-NEXT: ldr p6, [sp, #5, mul vl] // 2-byte Reload973; CHECK-NEXT: ldr p5, [sp, #6, mul vl] // 2-byte Reload974; CHECK-NEXT: ldr p4, [sp, #7, mul vl] // 2-byte Reload975; CHECK-NEXT: mov sp, x29976; CHECK-NEXT: ldr x19, [sp, #16] // 8-byte Reload977; CHECK-NEXT: ldp x29, x30, [sp], #32 // 16-byte Folded Reload978; CHECK-NEXT: ret979 %alloc = alloca i8, i64 %n, align 1980 %ppr_local = alloca <vscale x 16 x i1>981 %zpr_local = alloca <vscale x 16 x i8>982 tail call void asm sideeffect "", "~{p4},~{p5},~{p6}"()983 call void (...) @llvm.fake.use(ptr %alloc)984 store volatile <vscale x 16 x i1> %pred, ptr %ppr_local985 store volatile <vscale x 16 x i8> %vector, ptr %zpr_local986 ret void987}988 989; Only ZPR callee-saves (and ZPR/PPR locals) + a VLA990; Expect: Hazard padding, Frame pointer (x29), ZPR (z8-z10) callee-saves, with991; hazard padding before the ZPR callee saves (1024) and after the ZPR local area992; (1024). Only ZPRs restored by moving the SP to `FP - 1024 + addvl #-4`.993define void @sve_locals_only_zpr_csr_vla(i64 %n, <vscale x 16 x i1> %pred, <vscale x 16 x i8> %vector) {994; CHECK-LABEL: sve_locals_only_zpr_csr_vla:995; CHECK: // %bb.0:996; CHECK-NEXT: stp x29, x30, [sp, #-32]! // 16-byte Folded Spill997; CHECK-NEXT: str x19, [sp, #16] // 8-byte Spill998; CHECK-NEXT: mov x29, sp999; CHECK-NEXT: sub sp, sp, #10241000; CHECK-NEXT: addvl sp, sp, #-41001; CHECK-NEXT: str z10, [sp] // 16-byte Folded Spill1002; CHECK-NEXT: str z9, [sp, #1, mul vl] // 16-byte Folded Spill1003; CHECK-NEXT: str z8, [sp, #2, mul vl] // 16-byte Folded Spill1004; CHECK-NEXT: sub sp, sp, #10241005; CHECK-NEXT: addvl sp, sp, #-11006; CHECK-NEXT: mov x19, sp1007; CHECK-NEXT: .cfi_def_cfa w29, 321008; CHECK-NEXT: .cfi_offset w19, -161009; CHECK-NEXT: .cfi_offset w30, -241010; CHECK-NEXT: .cfi_offset w29, -321011; CHECK-NEXT: .cfi_escape 0x10, 0x48, 0x0b, 0x92, 0x2e, 0x00, 0x11, 0x70, 0x1e, 0x22, 0x11, 0xe0, 0x77, 0x22 // $d8 @ cfa - 16 * VG - 10561012; CHECK-NEXT: .cfi_escape 0x10, 0x49, 0x0b, 0x92, 0x2e, 0x00, 0x11, 0x68, 0x1e, 0x22, 0x11, 0xe0, 0x77, 0x22 // $d9 @ cfa - 24 * VG - 10561013; CHECK-NEXT: .cfi_escape 0x10, 0x4a, 0x0b, 0x92, 0x2e, 0x00, 0x11, 0x60, 0x1e, 0x22, 0x11, 0xe0, 0x77, 0x22 // $d10 @ cfa - 32 * VG - 10561014; CHECK-NEXT: add x9, x0, #151015; CHECK-NEXT: mov x8, sp1016; CHECK-NEXT: and x9, x9, #0xfffffffffffffff01017; CHECK-NEXT: sub x8, x8, x91018; CHECK-NEXT: mov sp, x81019; CHECK-NEXT: // fake_use: $x81020; CHECK-NEXT: sub x8, x29, #10241021; CHECK-NEXT: //APP1022; CHECK-NEXT: //NO_APP1023; CHECK-NEXT: str p0, [x29, #-1, mul vl]1024; CHECK-NEXT: str z0, [x8, #-5, mul vl]1025; CHECK-NEXT: addvl sp, x8, #-41026; CHECK-NEXT: ldr z10, [sp] // 16-byte Folded Reload1027; CHECK-NEXT: ldr z9, [sp, #1, mul vl] // 16-byte Folded Reload1028; CHECK-NEXT: ldr z8, [sp, #2, mul vl] // 16-byte Folded Reload1029; CHECK-NEXT: mov sp, x291030; CHECK-NEXT: ldr x19, [sp, #16] // 8-byte Reload1031; CHECK-NEXT: ldp x29, x30, [sp], #32 // 16-byte Folded Reload1032; CHECK-NEXT: ret1033 %alloc = alloca i8, i64 %n, align 11034 %ppr_local = alloca <vscale x 16 x i1>1035 %zpr_local = alloca <vscale x 16 x i8>1036 tail call void asm sideeffect "", "~{z8},~{z9},~{z10}"()1037 call void (...) @llvm.fake.use(ptr %alloc)1038 store volatile <vscale x 16 x i1> %pred, ptr %ppr_local1039 store volatile <vscale x 16 x i8> %vector, ptr %zpr_local1040 ret void1041}1042 1043; PPR+ZPR callee-saves (and ZPR/PPR locals) + a VLA1044; Expect: Hazard padding, Frame pointer (x29), PPR (p4-p6) and ZPR (z8-z10)1045; callee-saves, with hazard padding before the ZPR callee saves (1024) and after1046; the ZPR local area (1024). ZPRs restored by moving the SP to1047; `FP - 1024 + addvl #-5`, PPRs restored by moving SP to `FP + addvl #-1`.1048define void @sve_locals_zpr_ppr_csr_vla(i64 %n, <vscale x 16 x i1> %pred, <vscale x 16 x i8> %vector) {1049; CHECK-LABEL: sve_locals_zpr_ppr_csr_vla:1050; CHECK: // %bb.0:1051; CHECK-NEXT: stp x29, x30, [sp, #-32]! // 16-byte Folded Spill1052; CHECK-NEXT: str x19, [sp, #16] // 8-byte Spill1053; CHECK-NEXT: mov x29, sp1054; CHECK-NEXT: addvl sp, sp, #-11055; CHECK-NEXT: str p6, [sp, #5, mul vl] // 2-byte Spill1056; CHECK-NEXT: str p5, [sp, #6, mul vl] // 2-byte Spill1057; CHECK-NEXT: str p4, [sp, #7, mul vl] // 2-byte Spill1058; CHECK-NEXT: sub sp, sp, #10241059; CHECK-NEXT: addvl sp, sp, #-41060; CHECK-NEXT: str z10, [sp] // 16-byte Folded Spill1061; CHECK-NEXT: str z9, [sp, #1, mul vl] // 16-byte Folded Spill1062; CHECK-NEXT: str z8, [sp, #2, mul vl] // 16-byte Folded Spill1063; CHECK-NEXT: sub sp, sp, #10241064; CHECK-NEXT: addvl sp, sp, #-11065; CHECK-NEXT: mov x19, sp1066; CHECK-NEXT: .cfi_def_cfa w29, 321067; CHECK-NEXT: .cfi_offset w19, -161068; CHECK-NEXT: .cfi_offset w30, -241069; CHECK-NEXT: .cfi_offset w29, -321070; CHECK-NEXT: .cfi_escape 0x10, 0x48, 0x0b, 0x92, 0x2e, 0x00, 0x11, 0x68, 0x1e, 0x22, 0x11, 0xe0, 0x77, 0x22 // $d8 @ cfa - 24 * VG - 10561071; CHECK-NEXT: .cfi_escape 0x10, 0x49, 0x0b, 0x92, 0x2e, 0x00, 0x11, 0x60, 0x1e, 0x22, 0x11, 0xe0, 0x77, 0x22 // $d9 @ cfa - 32 * VG - 10561072; CHECK-NEXT: .cfi_escape 0x10, 0x4a, 0x0b, 0x92, 0x2e, 0x00, 0x11, 0x58, 0x1e, 0x22, 0x11, 0xe0, 0x77, 0x22 // $d10 @ cfa - 40 * VG - 10561073; CHECK-NEXT: add x9, x0, #151074; CHECK-NEXT: mov x8, sp1075; CHECK-NEXT: and x9, x9, #0xfffffffffffffff01076; CHECK-NEXT: sub x8, x8, x91077; CHECK-NEXT: mov sp, x81078; CHECK-NEXT: // fake_use: $x81079; CHECK-NEXT: sub x8, x29, #10241080; CHECK-NEXT: //APP1081; CHECK-NEXT: //NO_APP1082; CHECK-NEXT: str p0, [x29, #-9, mul vl]1083; CHECK-NEXT: str z0, [x8, #-6, mul vl]1084; CHECK-NEXT: addvl sp, x8, #-51085; CHECK-NEXT: ldr z10, [sp] // 16-byte Folded Reload1086; CHECK-NEXT: ldr z9, [sp, #1, mul vl] // 16-byte Folded Reload1087; CHECK-NEXT: ldr z8, [sp, #2, mul vl] // 16-byte Folded Reload1088; CHECK-NEXT: addvl sp, x29, #-11089; CHECK-NEXT: ldr p6, [sp, #5, mul vl] // 2-byte Reload1090; CHECK-NEXT: ldr p5, [sp, #6, mul vl] // 2-byte Reload1091; CHECK-NEXT: ldr p4, [sp, #7, mul vl] // 2-byte Reload1092; CHECK-NEXT: mov sp, x291093; CHECK-NEXT: ldr x19, [sp, #16] // 8-byte Reload1094; CHECK-NEXT: ldp x29, x30, [sp], #32 // 16-byte Folded Reload1095; CHECK-NEXT: ret1096 %alloc = alloca i8, i64 %n, align 11097 %ppr_local = alloca <vscale x 16 x i1>1098 %zpr_local = alloca <vscale x 16 x i8>1099 tail call void asm sideeffect "", "~{p4},~{p5},~{p6},~{z8},~{z9},~{z10}"()1100 call void (...) @llvm.fake.use(ptr %alloc)1101 store volatile <vscale x 16 x i1> %pred, ptr %ppr_local1102 store volatile <vscale x 16 x i8> %vector, ptr %zpr_local1103 ret void1104}1105