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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s3 4define i32 @fold_srem_positive_odd(i32 %x) {5; CHECK-LABEL: fold_srem_positive_odd:6; CHECK: // %bb.0:7; CHECK-NEXT: mov w8, #37253 // =0x91858; CHECK-NEXT: // kill: def $w0 killed $w0 def $x09; CHECK-NEXT: movk w8, #44150, lsl #1610; CHECK-NEXT: smull x8, w0, w811; CHECK-NEXT: add x8, x0, x8, lsr #3212; CHECK-NEXT: asr w9, w8, #613; CHECK-NEXT: add w8, w9, w8, lsr #3114; CHECK-NEXT: mov w9, #95 // =0x5f15; CHECK-NEXT: msub w0, w8, w9, w016; CHECK-NEXT: ret17 %1 = srem i32 %x, 9518 ret i32 %119}20 21 22define i32 @fold_srem_positive_even(i32 %x) {23; CHECK-LABEL: fold_srem_positive_even:24; CHECK: // %bb.0:25; CHECK-NEXT: mov w8, #36849 // =0x8ff126; CHECK-NEXT: mov w9, #1060 // =0x42427; CHECK-NEXT: movk w8, #15827, lsl #1628; CHECK-NEXT: smull x8, w0, w829; CHECK-NEXT: asr x8, x8, #4030; CHECK-NEXT: add w8, w8, w8, lsr #3131; CHECK-NEXT: msub w0, w8, w9, w032; CHECK-NEXT: ret33 %1 = srem i32 %x, 106034 ret i32 %135}36 37 38define i32 @fold_srem_negative_odd(i32 %x) {39; CHECK-LABEL: fold_srem_negative_odd:40; CHECK: // %bb.0:41; CHECK-NEXT: mov w8, #65445 // =0xffa542; CHECK-NEXT: mov w9, #-723 // =0xfffffd2d43; CHECK-NEXT: movk w8, #42330, lsl #1644; CHECK-NEXT: smull x8, w0, w845; CHECK-NEXT: asr x8, x8, #4046; CHECK-NEXT: add w8, w8, w8, lsr #3147; CHECK-NEXT: msub w0, w8, w9, w048; CHECK-NEXT: ret49 %1 = srem i32 %x, -72350 ret i32 %151}52 53 54define i32 @fold_srem_negative_even(i32 %x) {55; CHECK-LABEL: fold_srem_negative_even:56; CHECK: // %bb.0:57; CHECK-NEXT: mov w8, #62439 // =0xf3e758; CHECK-NEXT: mov w9, #-22981 // =0xffffa63b59; CHECK-NEXT: movk w8, #64805, lsl #1660; CHECK-NEXT: smull x8, w0, w861; CHECK-NEXT: asr x8, x8, #4062; CHECK-NEXT: add w8, w8, w8, lsr #3163; CHECK-NEXT: msub w0, w8, w9, w064; CHECK-NEXT: ret65 %1 = srem i32 %x, -2298166 ret i32 %167}68 69 70; Don't fold if we can combine srem with sdiv.71define i32 @combine_srem_sdiv(i32 %x) {72; CHECK-LABEL: combine_srem_sdiv:73; CHECK: // %bb.0:74; CHECK-NEXT: mov w8, #37253 // =0x918575; CHECK-NEXT: // kill: def $w0 killed $w0 def $x076; CHECK-NEXT: movk w8, #44150, lsl #1677; CHECK-NEXT: smull x8, w0, w878; CHECK-NEXT: add x8, x0, x8, lsr #3279; CHECK-NEXT: asr w9, w8, #680; CHECK-NEXT: add w8, w9, w8, lsr #3181; CHECK-NEXT: mov w9, #95 // =0x5f82; CHECK-NEXT: msub w9, w8, w9, w083; CHECK-NEXT: add w0, w9, w884; CHECK-NEXT: ret85 %1 = srem i32 %x, 9586 %2 = sdiv i32 %x, 9587 %3 = add i32 %1, %288 ret i32 %389}90 91; Don't fold i64 srem92define i64 @dont_fold_srem_i64(i64 %x) {93; CHECK-LABEL: dont_fold_srem_i64:94; CHECK: // %bb.0:95; CHECK-NEXT: mov x8, #58849 // =0xe5e196; CHECK-NEXT: movk x8, #48148, lsl #1697; CHECK-NEXT: movk x8, #33436, lsl #3298; CHECK-NEXT: movk x8, #21399, lsl #4899; CHECK-NEXT: smulh x8, x0, x8100; CHECK-NEXT: asr x9, x8, #5101; CHECK-NEXT: add x8, x9, x8, lsr #63102; CHECK-NEXT: mov w9, #98 // =0x62103; CHECK-NEXT: msub x0, x8, x9, x0104; CHECK-NEXT: ret105 %1 = srem i64 %x, 98106 ret i64 %1107}108