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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s3 4; Odd+Even divisors5define <4 x i32> @test_srem_odd_even(<4 x i32> %X) nounwind {6; CHECK-LABEL: test_srem_odd_even:7; CHECK: // %bb.0:8; CHECK-NEXT: adrp x8, .LCPI0_09; CHECK-NEXT: adrp x9, .LCPI0_110; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI0_0]11; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI0_1]12; CHECK-NEXT: adrp x8, .LCPI0_213; CHECK-NEXT: adrp x9, .LCPI0_314; CHECK-NEXT: mla v2.4s, v0.4s, v1.4s15; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI0_2]16; CHECK-NEXT: ldr q1, [x9, :lo12:.LCPI0_3]17; CHECK-NEXT: adrp x8, .LCPI0_418; CHECK-NEXT: ushl v0.4s, v2.4s, v0.4s19; CHECK-NEXT: ushl v1.4s, v2.4s, v1.4s20; CHECK-NEXT: movi v2.4s, #121; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b22; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI0_4]23; CHECK-NEXT: cmhs v0.4s, v1.4s, v0.4s24; CHECK-NEXT: and v0.16b, v0.16b, v2.16b25; CHECK-NEXT: ret26 %srem = srem <4 x i32> %X, <i32 5, i32 14, i32 25, i32 100>27 %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>28 %ret = zext <4 x i1> %cmp to <4 x i32>29 ret <4 x i32> %ret30}31 32;==============================================================================;33 34; One all-ones divisor in odd divisor35define <4 x i32> @test_srem_odd_allones_eq(<4 x i32> %X) nounwind {36; CHECK-LABEL: test_srem_odd_allones_eq:37; CHECK: // %bb.0:38; CHECK-NEXT: movi v1.16b, #15339; CHECK-NEXT: mov w8, #52429 // =0xcccd40; CHECK-NEXT: movk w8, #52428, lsl #1641; CHECK-NEXT: dup v2.4s, w842; CHECK-NEXT: adrp x8, .LCPI1_043; CHECK-NEXT: fneg v1.4s, v1.4s44; CHECK-NEXT: mla v1.4s, v0.4s, v2.4s45; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI1_0]46; CHECK-NEXT: movi v2.4s, #147; CHECK-NEXT: cmhs v0.4s, v0.4s, v1.4s48; CHECK-NEXT: and v0.16b, v0.16b, v2.16b49; CHECK-NEXT: ret50 %srem = srem <4 x i32> %X, <i32 5, i32 5, i32 4294967295, i32 5>51 %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>52 %ret = zext <4 x i1> %cmp to <4 x i32>53 ret <4 x i32> %ret54}55define <4 x i32> @test_srem_odd_allones_ne(<4 x i32> %X) nounwind {56; CHECK-LABEL: test_srem_odd_allones_ne:57; CHECK: // %bb.0:58; CHECK-NEXT: movi v1.16b, #15359; CHECK-NEXT: mov w8, #52429 // =0xcccd60; CHECK-NEXT: movk w8, #52428, lsl #1661; CHECK-NEXT: dup v2.4s, w862; CHECK-NEXT: adrp x8, .LCPI2_063; CHECK-NEXT: fneg v1.4s, v1.4s64; CHECK-NEXT: mla v1.4s, v0.4s, v2.4s65; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI2_0]66; CHECK-NEXT: movi v2.4s, #167; CHECK-NEXT: cmhi v0.4s, v1.4s, v0.4s68; CHECK-NEXT: and v0.16b, v0.16b, v2.16b69; CHECK-NEXT: ret70 %srem = srem <4 x i32> %X, <i32 5, i32 5, i32 4294967295, i32 5>71 %cmp = icmp ne <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>72 %ret = zext <4 x i1> %cmp to <4 x i32>73 ret <4 x i32> %ret74}75 76; One all-ones divisor in even divisor77define <4 x i32> @test_srem_even_allones_eq(<4 x i32> %X) nounwind {78; CHECK-LABEL: test_srem_even_allones_eq:79; CHECK: // %bb.0:80; CHECK-NEXT: mov w8, #28087 // =0x6db781; CHECK-NEXT: mov w9, #9362 // =0x249282; CHECK-NEXT: movk w8, #46811, lsl #1683; CHECK-NEXT: movk w9, #4681, lsl #1684; CHECK-NEXT: dup v1.4s, w885; CHECK-NEXT: dup v2.4s, w986; CHECK-NEXT: adrp x8, .LCPI3_087; CHECK-NEXT: mla v2.4s, v0.4s, v1.4s88; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI3_0]89; CHECK-NEXT: shl v0.4s, v2.4s, #3190; CHECK-NEXT: usra v0.4s, v2.4s, #191; CHECK-NEXT: movi v2.4s, #192; CHECK-NEXT: cmhs v0.4s, v1.4s, v0.4s93; CHECK-NEXT: and v0.16b, v0.16b, v2.16b94; CHECK-NEXT: ret95 %srem = srem <4 x i32> %X, <i32 14, i32 14, i32 4294967295, i32 14>96 %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>97 %ret = zext <4 x i1> %cmp to <4 x i32>98 ret <4 x i32> %ret99}100define <4 x i32> @test_srem_even_allones_ne(<4 x i32> %X) nounwind {101; CHECK-LABEL: test_srem_even_allones_ne:102; CHECK: // %bb.0:103; CHECK-NEXT: mov w8, #28087 // =0x6db7104; CHECK-NEXT: mov w9, #9362 // =0x2492105; CHECK-NEXT: movk w8, #46811, lsl #16106; CHECK-NEXT: movk w9, #4681, lsl #16107; CHECK-NEXT: dup v1.4s, w8108; CHECK-NEXT: dup v2.4s, w9109; CHECK-NEXT: adrp x8, .LCPI4_0110; CHECK-NEXT: mla v2.4s, v0.4s, v1.4s111; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI4_0]112; CHECK-NEXT: shl v0.4s, v2.4s, #31113; CHECK-NEXT: usra v0.4s, v2.4s, #1114; CHECK-NEXT: movi v2.4s, #1115; CHECK-NEXT: cmhi v0.4s, v0.4s, v1.4s116; CHECK-NEXT: and v0.16b, v0.16b, v2.16b117; CHECK-NEXT: ret118 %srem = srem <4 x i32> %X, <i32 14, i32 14, i32 4294967295, i32 14>119 %cmp = icmp ne <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>120 %ret = zext <4 x i1> %cmp to <4 x i32>121 ret <4 x i32> %ret122}123 124; One all-ones divisor in odd+even divisor125define <4 x i32> @test_srem_odd_even_allones_eq(<4 x i32> %X) nounwind {126; CHECK-LABEL: test_srem_odd_even_allones_eq:127; CHECK: // %bb.0:128; CHECK-NEXT: adrp x8, .LCPI5_0129; CHECK-NEXT: adrp x9, .LCPI5_1130; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI5_0]131; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI5_1]132; CHECK-NEXT: adrp x8, .LCPI5_2133; CHECK-NEXT: adrp x9, .LCPI5_3134; CHECK-NEXT: mla v2.4s, v0.4s, v1.4s135; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI5_2]136; CHECK-NEXT: ldr q1, [x9, :lo12:.LCPI5_3]137; CHECK-NEXT: adrp x8, .LCPI5_4138; CHECK-NEXT: ushl v0.4s, v2.4s, v0.4s139; CHECK-NEXT: ushl v1.4s, v2.4s, v1.4s140; CHECK-NEXT: movi v2.4s, #1141; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b142; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI5_4]143; CHECK-NEXT: cmhs v0.4s, v1.4s, v0.4s144; CHECK-NEXT: and v0.16b, v0.16b, v2.16b145; CHECK-NEXT: ret146 %srem = srem <4 x i32> %X, <i32 5, i32 14, i32 4294967295, i32 100>147 %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>148 %ret = zext <4 x i1> %cmp to <4 x i32>149 ret <4 x i32> %ret150}151define <4 x i32> @test_srem_odd_even_allones_ne(<4 x i32> %X) nounwind {152; CHECK-LABEL: test_srem_odd_even_allones_ne:153; CHECK: // %bb.0:154; CHECK-NEXT: adrp x8, .LCPI6_0155; CHECK-NEXT: adrp x9, .LCPI6_1156; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI6_0]157; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI6_1]158; CHECK-NEXT: adrp x8, .LCPI6_2159; CHECK-NEXT: adrp x9, .LCPI6_3160; CHECK-NEXT: mla v2.4s, v0.4s, v1.4s161; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI6_2]162; CHECK-NEXT: ldr q1, [x9, :lo12:.LCPI6_3]163; CHECK-NEXT: adrp x8, .LCPI6_4164; CHECK-NEXT: ushl v0.4s, v2.4s, v0.4s165; CHECK-NEXT: ushl v1.4s, v2.4s, v1.4s166; CHECK-NEXT: movi v2.4s, #1167; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b168; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI6_4]169; CHECK-NEXT: cmhi v0.4s, v0.4s, v1.4s170; CHECK-NEXT: and v0.16b, v0.16b, v2.16b171; CHECK-NEXT: ret172 %srem = srem <4 x i32> %X, <i32 5, i32 14, i32 4294967295, i32 100>173 %cmp = icmp ne <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>174 %ret = zext <4 x i1> %cmp to <4 x i32>175 ret <4 x i32> %ret176}177 178;------------------------------------------------------------------------------;179 180; One power-of-two divisor in odd divisor181define <4 x i32> @test_srem_odd_poweroftwo(<4 x i32> %X) nounwind {182; CHECK-LABEL: test_srem_odd_poweroftwo:183; CHECK: // %bb.0:184; CHECK-NEXT: adrp x8, .LCPI7_0185; CHECK-NEXT: adrp x9, .LCPI7_1186; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI7_0]187; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI7_1]188; CHECK-NEXT: adrp x8, .LCPI7_2189; CHECK-NEXT: adrp x9, .LCPI7_3190; CHECK-NEXT: mla v2.4s, v0.4s, v1.4s191; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI7_2]192; CHECK-NEXT: ldr q1, [x9, :lo12:.LCPI7_3]193; CHECK-NEXT: adrp x8, .LCPI7_4194; CHECK-NEXT: ushl v0.4s, v2.4s, v0.4s195; CHECK-NEXT: ushl v1.4s, v2.4s, v1.4s196; CHECK-NEXT: movi v2.4s, #1197; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b198; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI7_4]199; CHECK-NEXT: cmhs v0.4s, v1.4s, v0.4s200; CHECK-NEXT: and v0.16b, v0.16b, v2.16b201; CHECK-NEXT: ret202 %srem = srem <4 x i32> %X, <i32 5, i32 5, i32 16, i32 5>203 %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>204 %ret = zext <4 x i1> %cmp to <4 x i32>205 ret <4 x i32> %ret206}207 208; One power-of-two divisor in even divisor209define <4 x i32> @test_srem_even_poweroftwo(<4 x i32> %X) nounwind {210; CHECK-LABEL: test_srem_even_poweroftwo:211; CHECK: // %bb.0:212; CHECK-NEXT: adrp x8, .LCPI8_0213; CHECK-NEXT: adrp x9, .LCPI8_1214; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI8_0]215; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI8_1]216; CHECK-NEXT: adrp x8, .LCPI8_2217; CHECK-NEXT: adrp x9, .LCPI8_3218; CHECK-NEXT: mla v2.4s, v0.4s, v1.4s219; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI8_2]220; CHECK-NEXT: ldr q1, [x9, :lo12:.LCPI8_3]221; CHECK-NEXT: adrp x8, .LCPI8_4222; CHECK-NEXT: ushl v0.4s, v2.4s, v0.4s223; CHECK-NEXT: ushl v1.4s, v2.4s, v1.4s224; CHECK-NEXT: movi v2.4s, #1225; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b226; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI8_4]227; CHECK-NEXT: cmhs v0.4s, v1.4s, v0.4s228; CHECK-NEXT: and v0.16b, v0.16b, v2.16b229; CHECK-NEXT: ret230 %srem = srem <4 x i32> %X, <i32 14, i32 14, i32 16, i32 14>231 %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>232 %ret = zext <4 x i1> %cmp to <4 x i32>233 ret <4 x i32> %ret234}235 236; One power-of-two divisor in odd+even divisor237define <4 x i32> @test_srem_odd_even_poweroftwo(<4 x i32> %X) nounwind {238; CHECK-LABEL: test_srem_odd_even_poweroftwo:239; CHECK: // %bb.0:240; CHECK-NEXT: adrp x8, .LCPI9_0241; CHECK-NEXT: adrp x9, .LCPI9_1242; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI9_0]243; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI9_1]244; CHECK-NEXT: adrp x8, .LCPI9_2245; CHECK-NEXT: adrp x9, .LCPI9_3246; CHECK-NEXT: mla v2.4s, v0.4s, v1.4s247; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI9_2]248; CHECK-NEXT: ldr q1, [x9, :lo12:.LCPI9_3]249; CHECK-NEXT: adrp x8, .LCPI9_4250; CHECK-NEXT: ushl v0.4s, v2.4s, v0.4s251; CHECK-NEXT: ushl v1.4s, v2.4s, v1.4s252; CHECK-NEXT: movi v2.4s, #1253; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b254; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI9_4]255; CHECK-NEXT: cmhs v0.4s, v1.4s, v0.4s256; CHECK-NEXT: and v0.16b, v0.16b, v2.16b257; CHECK-NEXT: ret258 %srem = srem <4 x i32> %X, <i32 5, i32 14, i32 16, i32 100>259 %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>260 %ret = zext <4 x i1> %cmp to <4 x i32>261 ret <4 x i32> %ret262}263 264;------------------------------------------------------------------------------;265 266; One one divisor in odd divisor267define <4 x i32> @test_srem_odd_one(<4 x i32> %X) nounwind {268; CHECK-LABEL: test_srem_odd_one:269; CHECK: // %bb.0:270; CHECK-NEXT: movi v1.16b, #153271; CHECK-NEXT: mov w8, #52429 // =0xcccd272; CHECK-NEXT: movk w8, #52428, lsl #16273; CHECK-NEXT: dup v2.4s, w8274; CHECK-NEXT: adrp x8, .LCPI10_0275; CHECK-NEXT: fneg v1.4s, v1.4s276; CHECK-NEXT: mla v1.4s, v0.4s, v2.4s277; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI10_0]278; CHECK-NEXT: movi v2.4s, #1279; CHECK-NEXT: cmhs v0.4s, v0.4s, v1.4s280; CHECK-NEXT: and v0.16b, v0.16b, v2.16b281; CHECK-NEXT: ret282 %srem = srem <4 x i32> %X, <i32 5, i32 5, i32 1, i32 5>283 %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>284 %ret = zext <4 x i1> %cmp to <4 x i32>285 ret <4 x i32> %ret286}287 288; One one divisor in even divisor289define <4 x i32> @test_srem_even_one(<4 x i32> %X) nounwind {290; CHECK-LABEL: test_srem_even_one:291; CHECK: // %bb.0:292; CHECK-NEXT: mov w8, #28087 // =0x6db7293; CHECK-NEXT: mov w9, #9362 // =0x2492294; CHECK-NEXT: movk w8, #46811, lsl #16295; CHECK-NEXT: movk w9, #4681, lsl #16296; CHECK-NEXT: dup v1.4s, w8297; CHECK-NEXT: dup v2.4s, w9298; CHECK-NEXT: adrp x8, .LCPI11_0299; CHECK-NEXT: mla v2.4s, v0.4s, v1.4s300; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI11_0]301; CHECK-NEXT: shl v0.4s, v2.4s, #31302; CHECK-NEXT: usra v0.4s, v2.4s, #1303; CHECK-NEXT: movi v2.4s, #1304; CHECK-NEXT: cmhs v0.4s, v1.4s, v0.4s305; CHECK-NEXT: and v0.16b, v0.16b, v2.16b306; CHECK-NEXT: ret307 %srem = srem <4 x i32> %X, <i32 14, i32 14, i32 1, i32 14>308 %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>309 %ret = zext <4 x i1> %cmp to <4 x i32>310 ret <4 x i32> %ret311}312 313; One one divisor in odd+even divisor314define <4 x i32> @test_srem_odd_even_one(<4 x i32> %X) nounwind {315; CHECK-LABEL: test_srem_odd_even_one:316; CHECK: // %bb.0:317; CHECK-NEXT: adrp x8, .LCPI12_0318; CHECK-NEXT: adrp x9, .LCPI12_1319; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI12_0]320; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI12_1]321; CHECK-NEXT: adrp x8, .LCPI12_2322; CHECK-NEXT: adrp x9, .LCPI12_3323; CHECK-NEXT: mla v2.4s, v0.4s, v1.4s324; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI12_2]325; CHECK-NEXT: ldr q1, [x9, :lo12:.LCPI12_3]326; CHECK-NEXT: adrp x8, .LCPI12_4327; CHECK-NEXT: ushl v0.4s, v2.4s, v0.4s328; CHECK-NEXT: ushl v1.4s, v2.4s, v1.4s329; CHECK-NEXT: movi v2.4s, #1330; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b331; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI12_4]332; CHECK-NEXT: cmhs v0.4s, v1.4s, v0.4s333; CHECK-NEXT: and v0.16b, v0.16b, v2.16b334; CHECK-NEXT: ret335 %srem = srem <4 x i32> %X, <i32 5, i32 14, i32 1, i32 100>336 %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>337 %ret = zext <4 x i1> %cmp to <4 x i32>338 ret <4 x i32> %ret339}340 341;------------------------------------------------------------------------------;342 343; One INT_MIN divisor in odd divisor344define <4 x i32> @test_srem_odd_INT_MIN(<4 x i32> %X) nounwind {345; CHECK-LABEL: test_srem_odd_INT_MIN:346; CHECK: // %bb.0:347; CHECK-NEXT: adrp x8, .LCPI13_0348; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI13_0]349; CHECK-NEXT: adrp x8, .LCPI13_1350; CHECK-NEXT: smull2 v2.2d, v0.4s, v1.4s351; CHECK-NEXT: smull v1.2d, v0.2s, v1.2s352; CHECK-NEXT: uzp2 v1.4s, v1.4s, v2.4s353; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI13_1]354; CHECK-NEXT: adrp x8, .LCPI13_2355; CHECK-NEXT: mla v1.4s, v0.4s, v2.4s356; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI13_2]357; CHECK-NEXT: adrp x8, .LCPI13_3358; CHECK-NEXT: sshl v2.4s, v1.4s, v2.4s359; CHECK-NEXT: usra v2.4s, v1.4s, #31360; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI13_3]361; CHECK-NEXT: mls v0.4s, v2.4s, v1.4s362; CHECK-NEXT: movi v1.4s, #1363; CHECK-NEXT: cmeq v0.4s, v0.4s, #0364; CHECK-NEXT: and v0.16b, v0.16b, v1.16b365; CHECK-NEXT: ret366 %srem = srem <4 x i32> %X, <i32 5, i32 5, i32 2147483648, i32 5>367 %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>368 %ret = zext <4 x i1> %cmp to <4 x i32>369 ret <4 x i32> %ret370}371 372; One INT_MIN divisor in even divisor373define <4 x i32> @test_srem_even_INT_MIN(<4 x i32> %X) nounwind {374; CHECK-LABEL: test_srem_even_INT_MIN:375; CHECK: // %bb.0:376; CHECK-NEXT: adrp x8, .LCPI14_0377; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI14_0]378; CHECK-NEXT: adrp x8, .LCPI14_1379; CHECK-NEXT: smull2 v2.2d, v0.4s, v1.4s380; CHECK-NEXT: smull v1.2d, v0.2s, v1.2s381; CHECK-NEXT: uzp2 v1.4s, v1.4s, v2.4s382; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI14_1]383; CHECK-NEXT: adrp x8, .LCPI14_2384; CHECK-NEXT: mla v1.4s, v0.4s, v2.4s385; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI14_2]386; CHECK-NEXT: adrp x8, .LCPI14_3387; CHECK-NEXT: sshl v2.4s, v1.4s, v2.4s388; CHECK-NEXT: usra v2.4s, v1.4s, #31389; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI14_3]390; CHECK-NEXT: mls v0.4s, v2.4s, v1.4s391; CHECK-NEXT: movi v1.4s, #1392; CHECK-NEXT: cmeq v0.4s, v0.4s, #0393; CHECK-NEXT: and v0.16b, v0.16b, v1.16b394; CHECK-NEXT: ret395 %srem = srem <4 x i32> %X, <i32 14, i32 14, i32 2147483648, i32 14>396 %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>397 %ret = zext <4 x i1> %cmp to <4 x i32>398 ret <4 x i32> %ret399}400 401; One INT_MIN divisor in odd+even divisor402define <4 x i32> @test_srem_odd_even_INT_MIN(<4 x i32> %X) nounwind {403; CHECK-LABEL: test_srem_odd_even_INT_MIN:404; CHECK: // %bb.0:405; CHECK-NEXT: adrp x8, .LCPI15_0406; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI15_0]407; CHECK-NEXT: adrp x8, .LCPI15_1408; CHECK-NEXT: smull2 v2.2d, v0.4s, v1.4s409; CHECK-NEXT: smull v1.2d, v0.2s, v1.2s410; CHECK-NEXT: uzp2 v1.4s, v1.4s, v2.4s411; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI15_1]412; CHECK-NEXT: adrp x8, .LCPI15_2413; CHECK-NEXT: mla v1.4s, v0.4s, v2.4s414; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI15_2]415; CHECK-NEXT: adrp x8, .LCPI15_3416; CHECK-NEXT: sshl v2.4s, v1.4s, v2.4s417; CHECK-NEXT: usra v2.4s, v1.4s, #31418; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI15_3]419; CHECK-NEXT: mls v0.4s, v2.4s, v1.4s420; CHECK-NEXT: movi v1.4s, #1421; CHECK-NEXT: cmeq v0.4s, v0.4s, #0422; CHECK-NEXT: and v0.16b, v0.16b, v1.16b423; CHECK-NEXT: ret424 %srem = srem <4 x i32> %X, <i32 5, i32 14, i32 2147483648, i32 100>425 %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>426 %ret = zext <4 x i1> %cmp to <4 x i32>427 ret <4 x i32> %ret428}429 430;==============================================================================;431 432; One all-ones divisor and power-of-two divisor divisor in odd divisor433define <4 x i32> @test_srem_odd_allones_and_poweroftwo(<4 x i32> %X) nounwind {434; CHECK-LABEL: test_srem_odd_allones_and_poweroftwo:435; CHECK: // %bb.0:436; CHECK-NEXT: adrp x8, .LCPI16_0437; CHECK-NEXT: adrp x9, .LCPI16_1438; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI16_0]439; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI16_1]440; CHECK-NEXT: adrp x8, .LCPI16_2441; CHECK-NEXT: adrp x9, .LCPI16_3442; CHECK-NEXT: mla v2.4s, v0.4s, v1.4s443; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI16_2]444; CHECK-NEXT: ldr q1, [x9, :lo12:.LCPI16_3]445; CHECK-NEXT: adrp x8, .LCPI16_4446; CHECK-NEXT: ushl v0.4s, v2.4s, v0.4s447; CHECK-NEXT: ushl v1.4s, v2.4s, v1.4s448; CHECK-NEXT: movi v2.4s, #1449; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b450; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI16_4]451; CHECK-NEXT: cmhs v0.4s, v1.4s, v0.4s452; CHECK-NEXT: and v0.16b, v0.16b, v2.16b453; CHECK-NEXT: ret454 %srem = srem <4 x i32> %X, <i32 5, i32 4294967295, i32 16, i32 5>455 %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>456 %ret = zext <4 x i1> %cmp to <4 x i32>457 ret <4 x i32> %ret458}459 460; One all-ones divisor and power-of-two divisor divisor in even divisor461define <4 x i32> @test_srem_even_allones_and_poweroftwo(<4 x i32> %X) nounwind {462; CHECK-LABEL: test_srem_even_allones_and_poweroftwo:463; CHECK: // %bb.0:464; CHECK-NEXT: adrp x8, .LCPI17_0465; CHECK-NEXT: adrp x9, .LCPI17_1466; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI17_0]467; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI17_1]468; CHECK-NEXT: adrp x8, .LCPI17_2469; CHECK-NEXT: adrp x9, .LCPI17_3470; CHECK-NEXT: mla v2.4s, v0.4s, v1.4s471; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI17_2]472; CHECK-NEXT: ldr q1, [x9, :lo12:.LCPI17_3]473; CHECK-NEXT: adrp x8, .LCPI17_4474; CHECK-NEXT: ushl v0.4s, v2.4s, v0.4s475; CHECK-NEXT: ushl v1.4s, v2.4s, v1.4s476; CHECK-NEXT: movi v2.4s, #1477; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b478; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI17_4]479; CHECK-NEXT: cmhs v0.4s, v1.4s, v0.4s480; CHECK-NEXT: and v0.16b, v0.16b, v2.16b481; CHECK-NEXT: ret482 %srem = srem <4 x i32> %X, <i32 14, i32 4294967295, i32 16, i32 14>483 %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>484 %ret = zext <4 x i1> %cmp to <4 x i32>485 ret <4 x i32> %ret486}487 488; One all-ones divisor and power-of-two divisor divisor in odd+even divisor489define <4 x i32> @test_srem_odd_even_allones_and_poweroftwo(<4 x i32> %X) nounwind {490; CHECK-LABEL: test_srem_odd_even_allones_and_poweroftwo:491; CHECK: // %bb.0:492; CHECK-NEXT: adrp x8, .LCPI18_0493; CHECK-NEXT: adrp x9, .LCPI18_1494; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI18_0]495; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI18_1]496; CHECK-NEXT: adrp x8, .LCPI18_2497; CHECK-NEXT: adrp x9, .LCPI18_3498; CHECK-NEXT: mla v2.4s, v0.4s, v1.4s499; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI18_2]500; CHECK-NEXT: ldr q1, [x9, :lo12:.LCPI18_3]501; CHECK-NEXT: adrp x8, .LCPI18_4502; CHECK-NEXT: ushl v0.4s, v2.4s, v0.4s503; CHECK-NEXT: ushl v1.4s, v2.4s, v1.4s504; CHECK-NEXT: movi v2.4s, #1505; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b506; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI18_4]507; CHECK-NEXT: cmhs v0.4s, v1.4s, v0.4s508; CHECK-NEXT: and v0.16b, v0.16b, v2.16b509; CHECK-NEXT: ret510 %srem = srem <4 x i32> %X, <i32 5, i32 4294967295, i32 16, i32 100>511 %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>512 %ret = zext <4 x i1> %cmp to <4 x i32>513 ret <4 x i32> %ret514}515 516;------------------------------------------------------------------------------;517 518; One all-ones divisor and one one divisor in odd divisor519define <4 x i32> @test_srem_odd_allones_and_one(<4 x i32> %X) nounwind {520; CHECK-LABEL: test_srem_odd_allones_and_one:521; CHECK: // %bb.0:522; CHECK-NEXT: movi v1.16b, #153523; CHECK-NEXT: mov w8, #52429 // =0xcccd524; CHECK-NEXT: movk w8, #52428, lsl #16525; CHECK-NEXT: dup v2.4s, w8526; CHECK-NEXT: adrp x8, .LCPI19_0527; CHECK-NEXT: fneg v1.4s, v1.4s528; CHECK-NEXT: mla v1.4s, v0.4s, v2.4s529; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI19_0]530; CHECK-NEXT: movi v2.4s, #1531; CHECK-NEXT: cmhs v0.4s, v0.4s, v1.4s532; CHECK-NEXT: and v0.16b, v0.16b, v2.16b533; CHECK-NEXT: ret534 %srem = srem <4 x i32> %X, <i32 5, i32 4294967295, i32 1, i32 5>535 %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>536 %ret = zext <4 x i1> %cmp to <4 x i32>537 ret <4 x i32> %ret538}539 540; One all-ones divisor and one one divisor in even divisor541define <4 x i32> @test_srem_even_allones_and_one(<4 x i32> %X) nounwind {542; CHECK-LABEL: test_srem_even_allones_and_one:543; CHECK: // %bb.0:544; CHECK-NEXT: mov w8, #28087 // =0x6db7545; CHECK-NEXT: mov w9, #9362 // =0x2492546; CHECK-NEXT: movk w8, #46811, lsl #16547; CHECK-NEXT: movk w9, #4681, lsl #16548; CHECK-NEXT: dup v1.4s, w8549; CHECK-NEXT: dup v2.4s, w9550; CHECK-NEXT: adrp x8, .LCPI20_0551; CHECK-NEXT: mla v2.4s, v0.4s, v1.4s552; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI20_0]553; CHECK-NEXT: shl v0.4s, v2.4s, #31554; CHECK-NEXT: usra v0.4s, v2.4s, #1555; CHECK-NEXT: movi v2.4s, #1556; CHECK-NEXT: cmhs v0.4s, v1.4s, v0.4s557; CHECK-NEXT: and v0.16b, v0.16b, v2.16b558; CHECK-NEXT: ret559 %srem = srem <4 x i32> %X, <i32 14, i32 4294967295, i32 1, i32 14>560 %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>561 %ret = zext <4 x i1> %cmp to <4 x i32>562 ret <4 x i32> %ret563}564 565; One all-ones divisor and one one divisor in odd+even divisor566define <4 x i32> @test_srem_odd_even_allones_and_one(<4 x i32> %X) nounwind {567; CHECK-LABEL: test_srem_odd_even_allones_and_one:568; CHECK: // %bb.0:569; CHECK-NEXT: adrp x8, .LCPI21_0570; CHECK-NEXT: adrp x9, .LCPI21_1571; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI21_0]572; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI21_1]573; CHECK-NEXT: adrp x8, .LCPI21_2574; CHECK-NEXT: adrp x9, .LCPI21_3575; CHECK-NEXT: mla v2.4s, v0.4s, v1.4s576; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI21_2]577; CHECK-NEXT: ldr q1, [x9, :lo12:.LCPI21_3]578; CHECK-NEXT: adrp x8, .LCPI21_4579; CHECK-NEXT: ushl v0.4s, v2.4s, v0.4s580; CHECK-NEXT: ushl v1.4s, v2.4s, v1.4s581; CHECK-NEXT: movi v2.4s, #1582; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b583; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI21_4]584; CHECK-NEXT: cmhs v0.4s, v1.4s, v0.4s585; CHECK-NEXT: and v0.16b, v0.16b, v2.16b586; CHECK-NEXT: ret587 %srem = srem <4 x i32> %X, <i32 5, i32 4294967295, i32 1, i32 100>588 %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>589 %ret = zext <4 x i1> %cmp to <4 x i32>590 ret <4 x i32> %ret591}592 593;------------------------------------------------------------------------------;594 595; One power-of-two divisor divisor and one divisor in odd divisor596define <4 x i32> @test_srem_odd_poweroftwo_and_one(<4 x i32> %X) nounwind {597; CHECK-LABEL: test_srem_odd_poweroftwo_and_one:598; CHECK: // %bb.0:599; CHECK-NEXT: adrp x8, .LCPI22_0600; CHECK-NEXT: adrp x9, .LCPI22_1601; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI22_0]602; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI22_1]603; CHECK-NEXT: adrp x8, .LCPI22_2604; CHECK-NEXT: adrp x9, .LCPI22_3605; CHECK-NEXT: mla v2.4s, v0.4s, v1.4s606; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI22_2]607; CHECK-NEXT: ldr q1, [x9, :lo12:.LCPI22_3]608; CHECK-NEXT: adrp x8, .LCPI22_4609; CHECK-NEXT: ushl v0.4s, v2.4s, v0.4s610; CHECK-NEXT: ushl v1.4s, v2.4s, v1.4s611; CHECK-NEXT: movi v2.4s, #1612; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b613; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI22_4]614; CHECK-NEXT: cmhs v0.4s, v1.4s, v0.4s615; CHECK-NEXT: and v0.16b, v0.16b, v2.16b616; CHECK-NEXT: ret617 %srem = srem <4 x i32> %X, <i32 5, i32 16, i32 1, i32 5>618 %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>619 %ret = zext <4 x i1> %cmp to <4 x i32>620 ret <4 x i32> %ret621}622 623; One power-of-two divisor divisor and one divisor in even divisor624define <4 x i32> @test_srem_even_poweroftwo_and_one(<4 x i32> %X) nounwind {625; CHECK-LABEL: test_srem_even_poweroftwo_and_one:626; CHECK: // %bb.0:627; CHECK-NEXT: adrp x8, .LCPI23_0628; CHECK-NEXT: adrp x9, .LCPI23_1629; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI23_0]630; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI23_1]631; CHECK-NEXT: adrp x8, .LCPI23_2632; CHECK-NEXT: adrp x9, .LCPI23_3633; CHECK-NEXT: mla v2.4s, v0.4s, v1.4s634; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI23_2]635; CHECK-NEXT: ldr q1, [x9, :lo12:.LCPI23_3]636; CHECK-NEXT: adrp x8, .LCPI23_4637; CHECK-NEXT: ushl v0.4s, v2.4s, v0.4s638; CHECK-NEXT: ushl v1.4s, v2.4s, v1.4s639; CHECK-NEXT: movi v2.4s, #1640; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b641; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI23_4]642; CHECK-NEXT: cmhs v0.4s, v1.4s, v0.4s643; CHECK-NEXT: and v0.16b, v0.16b, v2.16b644; CHECK-NEXT: ret645 %srem = srem <4 x i32> %X, <i32 14, i32 16, i32 1, i32 14>646 %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>647 %ret = zext <4 x i1> %cmp to <4 x i32>648 ret <4 x i32> %ret649}650 651; One power-of-two divisor divisor and one divisor in odd+even divisor652define <4 x i32> @test_srem_odd_even_poweroftwo_and_one(<4 x i32> %X) nounwind {653; CHECK-LABEL: test_srem_odd_even_poweroftwo_and_one:654; CHECK: // %bb.0:655; CHECK-NEXT: adrp x8, .LCPI24_0656; CHECK-NEXT: adrp x9, .LCPI24_1657; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI24_0]658; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI24_1]659; CHECK-NEXT: adrp x8, .LCPI24_2660; CHECK-NEXT: adrp x9, .LCPI24_3661; CHECK-NEXT: mla v2.4s, v0.4s, v1.4s662; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI24_2]663; CHECK-NEXT: ldr q1, [x9, :lo12:.LCPI24_3]664; CHECK-NEXT: adrp x8, .LCPI24_4665; CHECK-NEXT: ushl v0.4s, v2.4s, v0.4s666; CHECK-NEXT: ushl v1.4s, v2.4s, v1.4s667; CHECK-NEXT: movi v2.4s, #1668; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b669; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI24_4]670; CHECK-NEXT: cmhs v0.4s, v1.4s, v0.4s671; CHECK-NEXT: and v0.16b, v0.16b, v2.16b672; CHECK-NEXT: ret673 %srem = srem <4 x i32> %X, <i32 5, i32 16, i32 1, i32 100>674 %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>675 %ret = zext <4 x i1> %cmp to <4 x i32>676 ret <4 x i32> %ret677}678 679;------------------------------------------------------------------------------;680 681define <4 x i32> @test_srem_odd_allones_and_poweroftwo_and_one(<4 x i32> %X) nounwind {682; CHECK-LABEL: test_srem_odd_allones_and_poweroftwo_and_one:683; CHECK: // %bb.0:684; CHECK-NEXT: adrp x8, .LCPI25_0685; CHECK-NEXT: adrp x9, .LCPI25_1686; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI25_0]687; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI25_1]688; CHECK-NEXT: adrp x8, .LCPI25_2689; CHECK-NEXT: adrp x9, .LCPI25_3690; CHECK-NEXT: mla v2.4s, v0.4s, v1.4s691; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI25_2]692; CHECK-NEXT: ldr q1, [x9, :lo12:.LCPI25_3]693; CHECK-NEXT: adrp x8, .LCPI25_4694; CHECK-NEXT: ushl v0.4s, v2.4s, v0.4s695; CHECK-NEXT: ushl v1.4s, v2.4s, v1.4s696; CHECK-NEXT: movi v2.4s, #1697; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b698; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI25_4]699; CHECK-NEXT: cmhs v0.4s, v1.4s, v0.4s700; CHECK-NEXT: and v0.16b, v0.16b, v2.16b701; CHECK-NEXT: ret702 %srem = srem <4 x i32> %X, <i32 5, i32 4294967295, i32 16, i32 1>703 %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>704 %ret = zext <4 x i1> %cmp to <4 x i32>705 ret <4 x i32> %ret706}707 708define <4 x i32> @test_srem_even_allones_and_poweroftwo_and_one(<4 x i32> %X) nounwind {709; CHECK-LABEL: test_srem_even_allones_and_poweroftwo_and_one:710; CHECK: // %bb.0:711; CHECK-NEXT: adrp x8, .LCPI26_0712; CHECK-NEXT: adrp x9, .LCPI26_1713; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI26_0]714; CHECK-NEXT: ldr q2, [x9, :lo12:.LCPI26_1]715; CHECK-NEXT: adrp x8, .LCPI26_2716; CHECK-NEXT: adrp x9, .LCPI26_3717; CHECK-NEXT: mla v2.4s, v0.4s, v1.4s718; CHECK-NEXT: ldr q0, [x8, :lo12:.LCPI26_2]719; CHECK-NEXT: ldr q1, [x9, :lo12:.LCPI26_3]720; CHECK-NEXT: adrp x8, .LCPI26_4721; CHECK-NEXT: ushl v0.4s, v2.4s, v0.4s722; CHECK-NEXT: ushl v1.4s, v2.4s, v1.4s723; CHECK-NEXT: movi v2.4s, #1724; CHECK-NEXT: orr v0.16b, v1.16b, v0.16b725; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI26_4]726; CHECK-NEXT: cmhs v0.4s, v1.4s, v0.4s727; CHECK-NEXT: and v0.16b, v0.16b, v2.16b728; CHECK-NEXT: ret729 %srem = srem <4 x i32> %X, <i32 14, i32 4294967295, i32 16, i32 1>730 %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>731 %ret = zext <4 x i1> %cmp to <4 x i32>732 ret <4 x i32> %ret733}734