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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s3 4; Odd divisor5define <4 x i32> @test_srem_odd_25(<4 x i32> %X) nounwind {6; CHECK-LABEL: test_srem_odd_25:7; CHECK: // %bb.0:8; CHECK-NEXT: mov w8, #23593 // =0x5c299; CHECK-NEXT: mov w9, #47185 // =0xb85110; CHECK-NEXT: movk w8, #49807, lsl #1611; CHECK-NEXT: movk w9, #1310, lsl #1612; CHECK-NEXT: dup v1.4s, w813; CHECK-NEXT: dup v2.4s, w914; CHECK-NEXT: mov w8, #28834 // =0x70a215; CHECK-NEXT: movk w8, #2621, lsl #1616; CHECK-NEXT: mla v2.4s, v0.4s, v1.4s17; CHECK-NEXT: dup v0.4s, w818; CHECK-NEXT: movi v1.4s, #119; CHECK-NEXT: cmhs v0.4s, v0.4s, v2.4s20; CHECK-NEXT: and v0.16b, v0.16b, v1.16b21; CHECK-NEXT: ret22 %srem = srem <4 x i32> %X, <i32 25, i32 25, i32 25, i32 25>23 %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>24 %ret = zext <4 x i1> %cmp to <4 x i32>25 ret <4 x i32> %ret26}27 28; Even divisors29define <4 x i32> @test_srem_even_100(<4 x i32> %X) nounwind {30; CHECK-LABEL: test_srem_even_100:31; CHECK: // %bb.0:32; CHECK-NEXT: mov w8, #23593 // =0x5c2933; CHECK-NEXT: mov w9, #47184 // =0xb85034; CHECK-NEXT: movk w8, #49807, lsl #1635; CHECK-NEXT: movk w9, #1310, lsl #1636; CHECK-NEXT: dup v1.4s, w837; CHECK-NEXT: dup v2.4s, w938; CHECK-NEXT: mov w8, #23592 // =0x5c2839; CHECK-NEXT: movk w8, #655, lsl #1640; CHECK-NEXT: mla v2.4s, v0.4s, v1.4s41; CHECK-NEXT: dup v1.4s, w842; CHECK-NEXT: shl v0.4s, v2.4s, #3043; CHECK-NEXT: usra v0.4s, v2.4s, #244; CHECK-NEXT: movi v2.4s, #145; CHECK-NEXT: cmhs v0.4s, v1.4s, v0.4s46; CHECK-NEXT: and v0.16b, v0.16b, v2.16b47; CHECK-NEXT: ret48 %srem = srem <4 x i32> %X, <i32 100, i32 100, i32 100, i32 100>49 %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>50 %ret = zext <4 x i1> %cmp to <4 x i32>51 ret <4 x i32> %ret52}53 54; Negative divisors should be negated, and thus this is still splat vectors.55 56; Odd divisor57define <4 x i32> @test_srem_odd_neg25(<4 x i32> %X) nounwind {58; CHECK-LABEL: test_srem_odd_neg25:59; CHECK: // %bb.0:60; CHECK-NEXT: mov w8, #23593 // =0x5c2961; CHECK-NEXT: mov w9, #47185 // =0xb85162; CHECK-NEXT: movk w8, #49807, lsl #1663; CHECK-NEXT: movk w9, #1310, lsl #1664; CHECK-NEXT: dup v1.4s, w865; CHECK-NEXT: dup v2.4s, w966; CHECK-NEXT: mov w8, #28834 // =0x70a267; CHECK-NEXT: movk w8, #2621, lsl #1668; CHECK-NEXT: mla v2.4s, v0.4s, v1.4s69; CHECK-NEXT: dup v0.4s, w870; CHECK-NEXT: movi v1.4s, #171; CHECK-NEXT: cmhs v0.4s, v0.4s, v2.4s72; CHECK-NEXT: and v0.16b, v0.16b, v1.16b73; CHECK-NEXT: ret74 %srem = srem <4 x i32> %X, <i32 25, i32 -25, i32 -25, i32 25>75 %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>76 %ret = zext <4 x i1> %cmp to <4 x i32>77 ret <4 x i32> %ret78}79 80; Even divisors81define <4 x i32> @test_srem_even_neg100(<4 x i32> %X) nounwind {82; CHECK-LABEL: test_srem_even_neg100:83; CHECK: // %bb.0:84; CHECK-NEXT: mov w8, #23593 // =0x5c2985; CHECK-NEXT: mov w9, #47184 // =0xb85086; CHECK-NEXT: movk w8, #49807, lsl #1687; CHECK-NEXT: movk w9, #1310, lsl #1688; CHECK-NEXT: dup v1.4s, w889; CHECK-NEXT: dup v2.4s, w990; CHECK-NEXT: mov w8, #23592 // =0x5c2891; CHECK-NEXT: movk w8, #655, lsl #1692; CHECK-NEXT: mla v2.4s, v0.4s, v1.4s93; CHECK-NEXT: dup v1.4s, w894; CHECK-NEXT: shl v0.4s, v2.4s, #3095; CHECK-NEXT: usra v0.4s, v2.4s, #296; CHECK-NEXT: movi v2.4s, #197; CHECK-NEXT: cmhs v0.4s, v1.4s, v0.4s98; CHECK-NEXT: and v0.16b, v0.16b, v2.16b99; CHECK-NEXT: ret100 %srem = srem <4 x i32> %X, <i32 -100, i32 100, i32 -100, i32 100>101 %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>102 %ret = zext <4 x i1> %cmp to <4 x i32>103 ret <4 x i32> %ret104}105 106;------------------------------------------------------------------------------;107; Comparison constant has undef elements.108;------------------------------------------------------------------------------;109 110define <4 x i32> @test_srem_odd_undef1(<4 x i32> %X) nounwind {111; CHECK-LABEL: test_srem_odd_undef1:112; CHECK: // %bb.0:113; CHECK-NEXT: mov w8, #34079 // =0x851f114; CHECK-NEXT: movi v3.4s, #25115; CHECK-NEXT: movk w8, #20971, lsl #16116; CHECK-NEXT: dup v1.4s, w8117; CHECK-NEXT: smull2 v2.2d, v0.4s, v1.4s118; CHECK-NEXT: smull v1.2d, v0.2s, v1.2s119; CHECK-NEXT: uzp2 v1.4s, v1.4s, v2.4s120; CHECK-NEXT: sshr v2.4s, v1.4s, #3121; CHECK-NEXT: usra v2.4s, v1.4s, #31122; CHECK-NEXT: movi v1.4s, #1123; CHECK-NEXT: mls v0.4s, v2.4s, v3.4s124; CHECK-NEXT: cmeq v0.4s, v0.4s, #0125; CHECK-NEXT: and v0.16b, v0.16b, v1.16b126; CHECK-NEXT: ret127 %srem = srem <4 x i32> %X, <i32 25, i32 25, i32 25, i32 25>128 %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 undef, i32 0>129 %ret = zext <4 x i1> %cmp to <4 x i32>130 ret <4 x i32> %ret131}132 133define <4 x i32> @test_srem_even_undef1(<4 x i32> %X) nounwind {134; CHECK-LABEL: test_srem_even_undef1:135; CHECK: // %bb.0:136; CHECK-NEXT: mov w8, #34079 // =0x851f137; CHECK-NEXT: movi v3.4s, #100138; CHECK-NEXT: movk w8, #20971, lsl #16139; CHECK-NEXT: dup v1.4s, w8140; CHECK-NEXT: smull2 v2.2d, v0.4s, v1.4s141; CHECK-NEXT: smull v1.2d, v0.2s, v1.2s142; CHECK-NEXT: uzp2 v1.4s, v1.4s, v2.4s143; CHECK-NEXT: sshr v2.4s, v1.4s, #5144; CHECK-NEXT: usra v2.4s, v1.4s, #31145; CHECK-NEXT: movi v1.4s, #1146; CHECK-NEXT: mls v0.4s, v2.4s, v3.4s147; CHECK-NEXT: cmeq v0.4s, v0.4s, #0148; CHECK-NEXT: and v0.16b, v0.16b, v1.16b149; CHECK-NEXT: ret150 %srem = srem <4 x i32> %X, <i32 100, i32 100, i32 100, i32 100>151 %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 undef, i32 0>152 %ret = zext <4 x i1> %cmp to <4 x i32>153 ret <4 x i32> %ret154}155 156;------------------------------------------------------------------------------;157; Negative tests158;------------------------------------------------------------------------------;159 160define <4 x i32> @test_srem_one_eq(<4 x i32> %X) nounwind {161; CHECK-LABEL: test_srem_one_eq:162; CHECK: // %bb.0:163; CHECK-NEXT: movi v0.4s, #1164; CHECK-NEXT: ret165 %srem = srem <4 x i32> %X, <i32 1, i32 1, i32 1, i32 1>166 %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>167 %ret = zext <4 x i1> %cmp to <4 x i32>168 ret <4 x i32> %ret169}170define <4 x i32> @test_srem_one_ne(<4 x i32> %X) nounwind {171; CHECK-LABEL: test_srem_one_ne:172; CHECK: // %bb.0:173; CHECK-NEXT: movi v0.2d, #0000000000000000174; CHECK-NEXT: ret175 %srem = srem <4 x i32> %X, <i32 1, i32 1, i32 1, i32 1>176 %cmp = icmp ne <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>177 %ret = zext <4 x i1> %cmp to <4 x i32>178 ret <4 x i32> %ret179}180 181; We can lower remainder of division by powers of two much better elsewhere.182define <4 x i32> @test_srem_pow2(<4 x i32> %X) nounwind {183; CHECK-LABEL: test_srem_pow2:184; CHECK: // %bb.0:185; CHECK-NEXT: cmlt v1.4s, v0.4s, #0186; CHECK-NEXT: mov v2.16b, v0.16b187; CHECK-NEXT: usra v2.4s, v1.4s, #28188; CHECK-NEXT: movi v1.4s, #1189; CHECK-NEXT: bic v2.4s, #15190; CHECK-NEXT: sub v0.4s, v0.4s, v2.4s191; CHECK-NEXT: cmeq v0.4s, v0.4s, #0192; CHECK-NEXT: and v0.16b, v0.16b, v1.16b193; CHECK-NEXT: ret194 %srem = srem <4 x i32> %X, <i32 16, i32 16, i32 16, i32 16>195 %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>196 %ret = zext <4 x i1> %cmp to <4 x i32>197 ret <4 x i32> %ret198}199 200; We could lower remainder of division by INT_MIN much better elsewhere.201define <4 x i32> @test_srem_int_min(<4 x i32> %X) nounwind {202; CHECK-LABEL: test_srem_int_min:203; CHECK: // %bb.0:204; CHECK-NEXT: cmlt v2.4s, v0.4s, #0205; CHECK-NEXT: mov v3.16b, v0.16b206; CHECK-NEXT: movi v1.4s, #128, lsl #24207; CHECK-NEXT: usra v3.4s, v2.4s, #1208; CHECK-NEXT: and v1.16b, v3.16b, v1.16b209; CHECK-NEXT: add v0.4s, v0.4s, v1.4s210; CHECK-NEXT: movi v1.4s, #1211; CHECK-NEXT: cmeq v0.4s, v0.4s, #0212; CHECK-NEXT: and v0.16b, v0.16b, v1.16b213; CHECK-NEXT: ret214 %srem = srem <4 x i32> %X, <i32 2147483648, i32 2147483648, i32 2147483648, i32 2147483648>215 %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>216 %ret = zext <4 x i1> %cmp to <4 x i32>217 ret <4 x i32> %ret218}219 220; We could lower remainder of division by all-ones much better elsewhere.221define <4 x i32> @test_srem_allones(<4 x i32> %X) nounwind {222; CHECK-LABEL: test_srem_allones:223; CHECK: // %bb.0:224; CHECK-NEXT: movi v0.4s, #1225; CHECK-NEXT: ret226 %srem = srem <4 x i32> %X, <i32 4294967295, i32 4294967295, i32 4294967295, i32 4294967295>227 %cmp = icmp eq <4 x i32> %srem, <i32 0, i32 0, i32 0, i32 0>228 %ret = zext <4 x i1> %cmp to <4 x i32>229 ret <4 x i32> %ret230}231