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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s3 4define <4 x i16> @fold_srem_vec_1(<4 x i16> %x) {5; CHECK-LABEL: fold_srem_vec_1:6; CHECK: // %bb.0:7; CHECK-NEXT: adrp x8, .LCPI0_18; CHECK-NEXT: ldr d1, [x8, :lo12:.LCPI0_1]9; CHECK-NEXT: adrp x8, .LCPI0_010; CHECK-NEXT: ldr d2, [x8, :lo12:.LCPI0_0]11; CHECK-NEXT: adrp x8, .LCPI0_212; CHECK-NEXT: smull v1.4s, v0.4h, v1.4h13; CHECK-NEXT: shrn v1.4h, v1.4s, #1614; CHECK-NEXT: mla v1.4h, v0.4h, v2.4h15; CHECK-NEXT: ldr d2, [x8, :lo12:.LCPI0_2]16; CHECK-NEXT: adrp x8, .LCPI0_317; CHECK-NEXT: sshl v1.4h, v1.4h, v2.4h18; CHECK-NEXT: ldr d2, [x8, :lo12:.LCPI0_3]19; CHECK-NEXT: usra v1.4h, v1.4h, #1520; CHECK-NEXT: mls v0.4h, v1.4h, v2.4h21; CHECK-NEXT: ret22 %1 = srem <4 x i16> %x, <i16 95, i16 -124, i16 98, i16 -1003>23 ret <4 x i16> %124}25 26define <4 x i16> @fold_srem_vec_2(<4 x i16> %x) {27; CHECK-LABEL: fold_srem_vec_2:28; CHECK: // %bb.0:29; CHECK-NEXT: mov w8, #44151 // =0xac7730; CHECK-NEXT: movi v2.4h, #9531; CHECK-NEXT: dup v1.4h, w832; CHECK-NEXT: smull v1.4s, v0.4h, v1.4h33; CHECK-NEXT: shrn v1.4h, v1.4s, #1634; CHECK-NEXT: add v1.4h, v1.4h, v0.4h35; CHECK-NEXT: sshr v1.4h, v1.4h, #636; CHECK-NEXT: usra v1.4h, v1.4h, #1537; CHECK-NEXT: mls v0.4h, v1.4h, v2.4h38; CHECK-NEXT: ret39 %1 = srem <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95>40 ret <4 x i16> %141}42 43 44; Don't fold if we can combine srem with sdiv.45define <4 x i16> @combine_srem_sdiv(<4 x i16> %x) {46; CHECK-LABEL: combine_srem_sdiv:47; CHECK: // %bb.0:48; CHECK-NEXT: mov w8, #44151 // =0xac7749; CHECK-NEXT: movi v2.4h, #9550; CHECK-NEXT: dup v1.4h, w851; CHECK-NEXT: smull v1.4s, v0.4h, v1.4h52; CHECK-NEXT: shrn v1.4h, v1.4s, #1653; CHECK-NEXT: add v1.4h, v1.4h, v0.4h54; CHECK-NEXT: sshr v1.4h, v1.4h, #655; CHECK-NEXT: usra v1.4h, v1.4h, #1556; CHECK-NEXT: mls v0.4h, v1.4h, v2.4h57; CHECK-NEXT: add v0.4h, v0.4h, v1.4h58; CHECK-NEXT: ret59 %1 = srem <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95>60 %2 = sdiv <4 x i16> %x, <i16 95, i16 95, i16 95, i16 95>61 %3 = add <4 x i16> %1, %262 ret <4 x i16> %363}64 65; Don't fold for divisors that are a power of two.66define <4 x i16> @dont_fold_srem_power_of_two(<4 x i16> %x) {67; CHECK-LABEL: dont_fold_srem_power_of_two:68; CHECK: // %bb.0:69; CHECK-NEXT: adrp x8, .LCPI3_070; CHECK-NEXT: ldr d1, [x8, :lo12:.LCPI3_0]71; CHECK-NEXT: adrp x8, .LCPI3_172; CHECK-NEXT: ldr d2, [x8, :lo12:.LCPI3_1]73; CHECK-NEXT: adrp x8, .LCPI3_274; CHECK-NEXT: smull v1.4s, v0.4h, v1.4h75; CHECK-NEXT: shrn v1.4h, v1.4s, #1676; CHECK-NEXT: add v1.4h, v1.4h, v0.4h77; CHECK-NEXT: sshl v1.4h, v1.4h, v2.4h78; CHECK-NEXT: ldr d2, [x8, :lo12:.LCPI3_2]79; CHECK-NEXT: usra v1.4h, v1.4h, #1580; CHECK-NEXT: mls v0.4h, v1.4h, v2.4h81; CHECK-NEXT: ret82 %1 = srem <4 x i16> %x, <i16 64, i16 32, i16 8, i16 95>83 ret <4 x i16> %184}85 86; Don't fold if the divisor is one.87define <4 x i16> @dont_fold_srem_one(<4 x i16> %x) {88; CHECK-LABEL: dont_fold_srem_one:89; CHECK: // %bb.0:90; CHECK-NEXT: adrp x8, .LCPI4_091; CHECK-NEXT: movi d2, #0x00ffff0000ffff92; CHECK-NEXT: ldr d1, [x8, :lo12:.LCPI4_0]93; CHECK-NEXT: adrp x8, .LCPI4_194; CHECK-NEXT: smull v1.4s, v0.4h, v1.4h95; CHECK-NEXT: and v2.8b, v0.8b, v2.8b96; CHECK-NEXT: shrn v1.4h, v1.4s, #1697; CHECK-NEXT: add v1.4h, v1.4h, v2.4h98; CHECK-NEXT: ldr d2, [x8, :lo12:.LCPI4_1]99; CHECK-NEXT: adrp x8, .LCPI4_2100; CHECK-NEXT: sshl v1.4h, v1.4h, v2.4h101; CHECK-NEXT: ushr v2.4h, v1.4h, #15102; CHECK-NEXT: mov v2.h[0], wzr103; CHECK-NEXT: add v1.4h, v1.4h, v2.4h104; CHECK-NEXT: ldr d2, [x8, :lo12:.LCPI4_2]105; CHECK-NEXT: mls v0.4h, v1.4h, v2.4h106; CHECK-NEXT: ret107 %1 = srem <4 x i16> %x, <i16 1, i16 654, i16 23, i16 5423>108 ret <4 x i16> %1109}110 111; Don't fold if the divisor is 2^15.112define <4 x i16> @dont_fold_srem_i16_smax(<4 x i16> %x) {113; CHECK-LABEL: dont_fold_srem_i16_smax:114; CHECK: // %bb.0:115; CHECK-NEXT: adrp x8, .LCPI5_1116; CHECK-NEXT: ldr d1, [x8, :lo12:.LCPI5_1]117; CHECK-NEXT: adrp x8, .LCPI5_0118; CHECK-NEXT: ldr d2, [x8, :lo12:.LCPI5_0]119; CHECK-NEXT: adrp x8, .LCPI5_2120; CHECK-NEXT: smull v1.4s, v0.4h, v1.4h121; CHECK-NEXT: shrn v1.4h, v1.4s, #16122; CHECK-NEXT: mla v1.4h, v0.4h, v2.4h123; CHECK-NEXT: ldr d2, [x8, :lo12:.LCPI5_2]124; CHECK-NEXT: adrp x8, .LCPI5_3125; CHECK-NEXT: sshl v1.4h, v1.4h, v2.4h126; CHECK-NEXT: ushr v2.4h, v1.4h, #15127; CHECK-NEXT: mov v2.h[0], wzr128; CHECK-NEXT: add v1.4h, v1.4h, v2.4h129; CHECK-NEXT: ldr d2, [x8, :lo12:.LCPI5_3]130; CHECK-NEXT: mls v0.4h, v1.4h, v2.4h131; CHECK-NEXT: ret132 %1 = srem <4 x i16> %x, <i16 1, i16 32768, i16 23, i16 5423>133 ret <4 x i16> %1134}135 136; Don't fold i64 srem.137define <4 x i64> @dont_fold_srem_i64(<4 x i64> %x) {138; CHECK-LABEL: dont_fold_srem_i64:139; CHECK: // %bb.0:140; CHECK-NEXT: mov x8, #8549 // =0x2165141; CHECK-NEXT: fmov x10, d1142; CHECK-NEXT: mov x9, v1.d[1]143; CHECK-NEXT: movk x8, #22795, lsl #16144; CHECK-NEXT: mov x12, #6055 // =0x17a7145; CHECK-NEXT: mov x11, v0.d[1]146; CHECK-NEXT: movk x8, #17096, lsl #32147; CHECK-NEXT: movk x12, #58853, lsl #16148; CHECK-NEXT: mov x13, #21445 // =0x53c5149; CHECK-NEXT: movk x8, #45590, lsl #48150; CHECK-NEXT: movk x12, #47142, lsl #32151; CHECK-NEXT: movk x13, #1603, lsl #16152; CHECK-NEXT: smulh x8, x10, x8153; CHECK-NEXT: movk x12, #24749, lsl #48154; CHECK-NEXT: movk x13, #15432, lsl #32155; CHECK-NEXT: movk x13, #25653, lsl #48156; CHECK-NEXT: movi v0.2d, #0000000000000000157; CHECK-NEXT: smulh x12, x9, x12158; CHECK-NEXT: smulh x13, x11, x13159; CHECK-NEXT: add x8, x8, x10160; CHECK-NEXT: asr x14, x8, #4161; CHECK-NEXT: asr x15, x12, #11162; CHECK-NEXT: add x8, x14, x8, lsr #63163; CHECK-NEXT: mov w14, #23 // =0x17164; CHECK-NEXT: add x12, x15, x12, lsr #63165; CHECK-NEXT: msub x8, x8, x14, x10166; CHECK-NEXT: asr x10, x13, #8167; CHECK-NEXT: mov w14, #5423 // =0x152f168; CHECK-NEXT: add x10, x10, x13, lsr #63169; CHECK-NEXT: msub x9, x12, x14, x9170; CHECK-NEXT: mov w12, #654 // =0x28e171; CHECK-NEXT: msub x10, x10, x12, x11172; CHECK-NEXT: fmov d1, x8173; CHECK-NEXT: mov v1.d[1], x9174; CHECK-NEXT: mov v0.d[1], x10175; CHECK-NEXT: ret176 %1 = srem <4 x i64> %x, <i64 1, i64 654, i64 23, i64 5423>177 ret <4 x i64> %1178}179 180define <16 x i8> @fold_srem_v16i8(<16 x i8> %x) {181; CHECK-LABEL: fold_srem_v16i8:182; CHECK: // %bb.0:183; CHECK-NEXT: movi v1.16b, #103184; CHECK-NEXT: smull2 v2.8h, v0.16b, v1.16b185; CHECK-NEXT: smull v1.8h, v0.8b, v1.8b186; CHECK-NEXT: uzp2 v1.16b, v1.16b, v2.16b187; CHECK-NEXT: movi v2.16b, #10188; CHECK-NEXT: sshr v1.16b, v1.16b, #2189; CHECK-NEXT: usra v1.16b, v1.16b, #7190; CHECK-NEXT: mls v0.16b, v1.16b, v2.16b191; CHECK-NEXT: ret192 %1 = srem <16 x i8> %x, <i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10>193 ret <16 x i8> %1194}195 196define <8 x i8> @fold_srem_v8i8(<8 x i8> %x) {197; CHECK-LABEL: fold_srem_v8i8:198; CHECK: // %bb.0:199; CHECK-NEXT: movi v1.8b, #103200; CHECK-NEXT: movi v2.8b, #10201; CHECK-NEXT: smull v1.8h, v0.8b, v1.8b202; CHECK-NEXT: shrn v1.8b, v1.8h, #8203; CHECK-NEXT: sshr v1.8b, v1.8b, #2204; CHECK-NEXT: usra v1.8b, v1.8b, #7205; CHECK-NEXT: mls v0.8b, v1.8b, v2.8b206; CHECK-NEXT: ret207 %1 = srem <8 x i8> %x, <i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10, i8 10>208 ret <8 x i8> %1209}210 211define <8 x i16> @fold_srem_v8i16(<8 x i16> %x) {212; CHECK-LABEL: fold_srem_v8i16:213; CHECK: // %bb.0:214; CHECK-NEXT: mov w8, #26215 // =0x6667215; CHECK-NEXT: dup v1.8h, w8216; CHECK-NEXT: smull2 v2.4s, v0.8h, v1.8h217; CHECK-NEXT: smull v1.4s, v0.4h, v1.4h218; CHECK-NEXT: uzp2 v1.8h, v1.8h, v2.8h219; CHECK-NEXT: movi v2.8h, #10220; CHECK-NEXT: sshr v1.8h, v1.8h, #2221; CHECK-NEXT: usra v1.8h, v1.8h, #15222; CHECK-NEXT: mls v0.8h, v1.8h, v2.8h223; CHECK-NEXT: ret224 %1 = srem <8 x i16> %x, <i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10, i16 10>225 ret <8 x i16> %1226}227 228define <4 x i16> @fold_srem_v4i16(<4 x i16> %x) {229; CHECK-LABEL: fold_srem_v4i16:230; CHECK: // %bb.0:231; CHECK-NEXT: mov w8, #26215 // =0x6667232; CHECK-NEXT: movi v2.4h, #10233; CHECK-NEXT: dup v1.4h, w8234; CHECK-NEXT: smull v1.4s, v0.4h, v1.4h235; CHECK-NEXT: sshr v1.4s, v1.4s, #18236; CHECK-NEXT: xtn v1.4h, v1.4s237; CHECK-NEXT: usra v1.4h, v1.4h, #15238; CHECK-NEXT: mls v0.4h, v1.4h, v2.4h239; CHECK-NEXT: ret240 %1 = srem <4 x i16> %x, <i16 10, i16 10, i16 10, i16 10>241 ret <4 x i16> %1242}243 244define <4 x i32> @fold_srem_v4i32(<4 x i32> %x) {245; CHECK-LABEL: fold_srem_v4i32:246; CHECK: // %bb.0:247; CHECK-NEXT: mov w8, #26215 // =0x6667248; CHECK-NEXT: movi v3.4s, #10249; CHECK-NEXT: movk w8, #26214, lsl #16250; CHECK-NEXT: dup v1.4s, w8251; CHECK-NEXT: smull2 v2.2d, v0.4s, v1.4s252; CHECK-NEXT: smull v1.2d, v0.2s, v1.2s253; CHECK-NEXT: uzp2 v1.4s, v1.4s, v2.4s254; CHECK-NEXT: sshr v2.4s, v1.4s, #2255; CHECK-NEXT: usra v2.4s, v1.4s, #31256; CHECK-NEXT: mls v0.4s, v2.4s, v3.4s257; CHECK-NEXT: ret258 %1 = srem <4 x i32> %x, <i32 10, i32 10, i32 10, i32 10>259 ret <4 x i32> %1260}261 262define <2 x i32> @fold_srem_v2i32(<2 x i32> %x) {263; CHECK-LABEL: fold_srem_v2i32:264; CHECK: // %bb.0:265; CHECK-NEXT: mov w8, #26215 // =0x6667266; CHECK-NEXT: movi v2.2s, #10267; CHECK-NEXT: movk w8, #26214, lsl #16268; CHECK-NEXT: dup v1.2s, w8269; CHECK-NEXT: smull v1.2d, v0.2s, v1.2s270; CHECK-NEXT: sshr v1.2d, v1.2d, #34271; CHECK-NEXT: xtn v1.2s, v1.2d272; CHECK-NEXT: usra v1.2s, v1.2s, #31273; CHECK-NEXT: mls v0.2s, v1.2s, v2.2s274; CHECK-NEXT: ret275 %1 = srem <2 x i32> %x, <i32 10, i32 10>276 ret <2 x i32> %1277}278 279define <2 x i64> @fold_srem_v2i64(<2 x i64> %x) {280; CHECK-LABEL: fold_srem_v2i64:281; CHECK: // %bb.0:282; CHECK-NEXT: fmov x10, d0283; CHECK-NEXT: mov x8, #7378697629483820646 // =0x6666666666666666284; CHECK-NEXT: mov x9, v0.d[1]285; CHECK-NEXT: movk x8, #26215286; CHECK-NEXT: smulh x11, x10, x8287; CHECK-NEXT: smulh x8, x9, x8288; CHECK-NEXT: asr x12, x11, #2289; CHECK-NEXT: add x11, x12, x11, lsr #63290; CHECK-NEXT: asr x13, x8, #2291; CHECK-NEXT: mov w12, #10 // =0xa292; CHECK-NEXT: msub x10, x11, x12, x10293; CHECK-NEXT: add x8, x13, x8, lsr #63294; CHECK-NEXT: msub x8, x8, x12, x9295; CHECK-NEXT: fmov d0, x10296; CHECK-NEXT: mov v0.d[1], x8297; CHECK-NEXT: ret298 %1 = srem <2 x i64> %x, <i64 10, i64 10>299 ret <2 x i64> %1300}301 302define <1 x i64> @fold_srem_v1i64(<1 x i64> %x) {303; CHECK-LABEL: fold_srem_v1i64:304; CHECK: // %bb.0:305; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0306; CHECK-NEXT: fmov x9, d0307; CHECK-NEXT: mov x8, #7378697629483820646 // =0x6666666666666666308; CHECK-NEXT: movk x8, #26215309; CHECK-NEXT: smulh x8, x9, x8310; CHECK-NEXT: asr x10, x8, #2311; CHECK-NEXT: add x8, x10, x8, lsr #63312; CHECK-NEXT: mov w10, #10 // =0xa313; CHECK-NEXT: msub x8, x8, x10, x9314; CHECK-NEXT: fmov d0, x8315; CHECK-NEXT: ret316 %1 = srem <1 x i64> %x, <i64 10>317 ret <1 x i64> %1318}319