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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s --check-prefixes=CHECK,CHECK-SD3; RUN: llc < %s -mtriple=aarch64-- -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI4 5; CHECK-GI: warning: Instruction selection used fallback path for v16i46; CHECK-GI-NEXT: warning: Instruction selection used fallback path for v16i17 8define <16 x i8> @v16i8(<16 x i8> %x, <16 x i8> %y) nounwind {9; CHECK-LABEL: v16i8:10; CHECK: // %bb.0:11; CHECK-NEXT: sqsub v0.16b, v0.16b, v1.16b12; CHECK-NEXT: ret13 %z = call <16 x i8> @llvm.ssub.sat.v16i8(<16 x i8> %x, <16 x i8> %y)14 ret <16 x i8> %z15}16 17define <32 x i8> @v32i8(<32 x i8> %x, <32 x i8> %y) nounwind {18; CHECK-SD-LABEL: v32i8:19; CHECK-SD: // %bb.0:20; CHECK-SD-NEXT: sqsub v1.16b, v1.16b, v3.16b21; CHECK-SD-NEXT: sqsub v0.16b, v0.16b, v2.16b22; CHECK-SD-NEXT: ret23;24; CHECK-GI-LABEL: v32i8:25; CHECK-GI: // %bb.0:26; CHECK-GI-NEXT: sqsub v0.16b, v0.16b, v2.16b27; CHECK-GI-NEXT: sqsub v1.16b, v1.16b, v3.16b28; CHECK-GI-NEXT: ret29 %z = call <32 x i8> @llvm.ssub.sat.v32i8(<32 x i8> %x, <32 x i8> %y)30 ret <32 x i8> %z31}32 33define <64 x i8> @v64i8(<64 x i8> %x, <64 x i8> %y) nounwind {34; CHECK-SD-LABEL: v64i8:35; CHECK-SD: // %bb.0:36; CHECK-SD-NEXT: sqsub v2.16b, v2.16b, v6.16b37; CHECK-SD-NEXT: sqsub v0.16b, v0.16b, v4.16b38; CHECK-SD-NEXT: sqsub v1.16b, v1.16b, v5.16b39; CHECK-SD-NEXT: sqsub v3.16b, v3.16b, v7.16b40; CHECK-SD-NEXT: ret41;42; CHECK-GI-LABEL: v64i8:43; CHECK-GI: // %bb.0:44; CHECK-GI-NEXT: sqsub v0.16b, v0.16b, v4.16b45; CHECK-GI-NEXT: sqsub v1.16b, v1.16b, v5.16b46; CHECK-GI-NEXT: sqsub v2.16b, v2.16b, v6.16b47; CHECK-GI-NEXT: sqsub v3.16b, v3.16b, v7.16b48; CHECK-GI-NEXT: ret49 %z = call <64 x i8> @llvm.ssub.sat.v64i8(<64 x i8> %x, <64 x i8> %y)50 ret <64 x i8> %z51}52 53define <8 x i16> @v8i16(<8 x i16> %x, <8 x i16> %y) nounwind {54; CHECK-LABEL: v8i16:55; CHECK: // %bb.0:56; CHECK-NEXT: sqsub v0.8h, v0.8h, v1.8h57; CHECK-NEXT: ret58 %z = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> %x, <8 x i16> %y)59 ret <8 x i16> %z60}61 62define <16 x i16> @v16i16(<16 x i16> %x, <16 x i16> %y) nounwind {63; CHECK-SD-LABEL: v16i16:64; CHECK-SD: // %bb.0:65; CHECK-SD-NEXT: sqsub v1.8h, v1.8h, v3.8h66; CHECK-SD-NEXT: sqsub v0.8h, v0.8h, v2.8h67; CHECK-SD-NEXT: ret68;69; CHECK-GI-LABEL: v16i16:70; CHECK-GI: // %bb.0:71; CHECK-GI-NEXT: sqsub v0.8h, v0.8h, v2.8h72; CHECK-GI-NEXT: sqsub v1.8h, v1.8h, v3.8h73; CHECK-GI-NEXT: ret74 %z = call <16 x i16> @llvm.ssub.sat.v16i16(<16 x i16> %x, <16 x i16> %y)75 ret <16 x i16> %z76}77 78define <32 x i16> @v32i16(<32 x i16> %x, <32 x i16> %y) nounwind {79; CHECK-SD-LABEL: v32i16:80; CHECK-SD: // %bb.0:81; CHECK-SD-NEXT: sqsub v2.8h, v2.8h, v6.8h82; CHECK-SD-NEXT: sqsub v0.8h, v0.8h, v4.8h83; CHECK-SD-NEXT: sqsub v1.8h, v1.8h, v5.8h84; CHECK-SD-NEXT: sqsub v3.8h, v3.8h, v7.8h85; CHECK-SD-NEXT: ret86;87; CHECK-GI-LABEL: v32i16:88; CHECK-GI: // %bb.0:89; CHECK-GI-NEXT: sqsub v0.8h, v0.8h, v4.8h90; CHECK-GI-NEXT: sqsub v1.8h, v1.8h, v5.8h91; CHECK-GI-NEXT: sqsub v2.8h, v2.8h, v6.8h92; CHECK-GI-NEXT: sqsub v3.8h, v3.8h, v7.8h93; CHECK-GI-NEXT: ret94 %z = call <32 x i16> @llvm.ssub.sat.v32i16(<32 x i16> %x, <32 x i16> %y)95 ret <32 x i16> %z96}97 98define void @v8i8(ptr %px, ptr %py, ptr %pz) nounwind {99; CHECK-LABEL: v8i8:100; CHECK: // %bb.0:101; CHECK-NEXT: ldr d0, [x0]102; CHECK-NEXT: ldr d1, [x1]103; CHECK-NEXT: sqsub v0.8b, v0.8b, v1.8b104; CHECK-NEXT: str d0, [x2]105; CHECK-NEXT: ret106 %x = load <8 x i8>, ptr %px107 %y = load <8 x i8>, ptr %py108 %z = call <8 x i8> @llvm.ssub.sat.v8i8(<8 x i8> %x, <8 x i8> %y)109 store <8 x i8> %z, ptr %pz110 ret void111}112 113define void @v4i8(ptr %px, ptr %py, ptr %pz) nounwind {114; CHECK-SD-LABEL: v4i8:115; CHECK-SD: // %bb.0:116; CHECK-SD-NEXT: ldr s0, [x0]117; CHECK-SD-NEXT: ldr s1, [x1]118; CHECK-SD-NEXT: ushll v0.8h, v0.8b, #0119; CHECK-SD-NEXT: ushll v1.8h, v1.8b, #0120; CHECK-SD-NEXT: shl v1.4h, v1.4h, #8121; CHECK-SD-NEXT: shl v0.4h, v0.4h, #8122; CHECK-SD-NEXT: sqsub v0.4h, v0.4h, v1.4h123; CHECK-SD-NEXT: ushr v0.4h, v0.4h, #8124; CHECK-SD-NEXT: uzp1 v0.8b, v0.8b, v0.8b125; CHECK-SD-NEXT: str s0, [x2]126; CHECK-SD-NEXT: ret127;128; CHECK-GI-LABEL: v4i8:129; CHECK-GI: // %bb.0:130; CHECK-GI-NEXT: ldr w8, [x0]131; CHECK-GI-NEXT: ldr w9, [x1]132; CHECK-GI-NEXT: fmov s0, w8133; CHECK-GI-NEXT: fmov s1, w9134; CHECK-GI-NEXT: mov b2, v0.b[1]135; CHECK-GI-NEXT: mov v3.b[0], v0.b[0]136; CHECK-GI-NEXT: mov b4, v1.b[1]137; CHECK-GI-NEXT: mov v5.b[0], v1.b[0]138; CHECK-GI-NEXT: mov v3.b[1], v2.b[0]139; CHECK-GI-NEXT: mov b2, v0.b[2]140; CHECK-GI-NEXT: mov b0, v0.b[3]141; CHECK-GI-NEXT: mov v5.b[1], v4.b[0]142; CHECK-GI-NEXT: mov b4, v1.b[2]143; CHECK-GI-NEXT: mov b1, v1.b[3]144; CHECK-GI-NEXT: mov v3.b[2], v2.b[0]145; CHECK-GI-NEXT: mov v5.b[2], v4.b[0]146; CHECK-GI-NEXT: mov v3.b[3], v0.b[0]147; CHECK-GI-NEXT: mov v5.b[3], v1.b[0]148; CHECK-GI-NEXT: sqsub v0.8b, v3.8b, v5.8b149; CHECK-GI-NEXT: fmov w8, s0150; CHECK-GI-NEXT: str w8, [x2]151; CHECK-GI-NEXT: ret152 %x = load <4 x i8>, ptr %px153 %y = load <4 x i8>, ptr %py154 %z = call <4 x i8> @llvm.ssub.sat.v4i8(<4 x i8> %x, <4 x i8> %y)155 store <4 x i8> %z, ptr %pz156 ret void157}158 159define void @v2i8(ptr %px, ptr %py, ptr %pz) nounwind {160; CHECK-SD-LABEL: v2i8:161; CHECK-SD: // %bb.0:162; CHECK-SD-NEXT: ldr h0, [x0]163; CHECK-SD-NEXT: ldr h1, [x1]164; CHECK-SD-NEXT: ushll v0.8h, v0.8b, #0165; CHECK-SD-NEXT: ushll v1.8h, v1.8b, #0166; CHECK-SD-NEXT: ushll v0.4s, v0.4h, #0167; CHECK-SD-NEXT: ushll v1.4s, v1.4h, #0168; CHECK-SD-NEXT: shl v1.2s, v1.2s, #24169; CHECK-SD-NEXT: shl v0.2s, v0.2s, #24170; CHECK-SD-NEXT: sqsub v0.2s, v0.2s, v1.2s171; CHECK-SD-NEXT: ushr v0.2s, v0.2s, #24172; CHECK-SD-NEXT: mov s1, v0.s[1]173; CHECK-SD-NEXT: str b0, [x2]174; CHECK-SD-NEXT: stur b1, [x2, #1]175; CHECK-SD-NEXT: ret176;177; CHECK-GI-LABEL: v2i8:178; CHECK-GI: // %bb.0:179; CHECK-GI-NEXT: ldr b0, [x0]180; CHECK-GI-NEXT: ldr b1, [x1]181; CHECK-GI-NEXT: add x8, x0, #1182; CHECK-GI-NEXT: add x9, x1, #1183; CHECK-GI-NEXT: ld1 { v0.b }[1], [x8]184; CHECK-GI-NEXT: ld1 { v1.b }[1], [x9]185; CHECK-GI-NEXT: add x8, x2, #1186; CHECK-GI-NEXT: sqsub v0.8b, v0.8b, v1.8b187; CHECK-GI-NEXT: st1 { v0.b }[0], [x2]188; CHECK-GI-NEXT: st1 { v0.b }[1], [x8]189; CHECK-GI-NEXT: ret190 %x = load <2 x i8>, ptr %px191 %y = load <2 x i8>, ptr %py192 %z = call <2 x i8> @llvm.ssub.sat.v2i8(<2 x i8> %x, <2 x i8> %y)193 store <2 x i8> %z, ptr %pz194 ret void195}196 197define void @v4i16(ptr %px, ptr %py, ptr %pz) nounwind {198; CHECK-LABEL: v4i16:199; CHECK: // %bb.0:200; CHECK-NEXT: ldr d0, [x0]201; CHECK-NEXT: ldr d1, [x1]202; CHECK-NEXT: sqsub v0.4h, v0.4h, v1.4h203; CHECK-NEXT: str d0, [x2]204; CHECK-NEXT: ret205 %x = load <4 x i16>, ptr %px206 %y = load <4 x i16>, ptr %py207 %z = call <4 x i16> @llvm.ssub.sat.v4i16(<4 x i16> %x, <4 x i16> %y)208 store <4 x i16> %z, ptr %pz209 ret void210}211 212define void @v2i16(ptr %px, ptr %py, ptr %pz) nounwind {213; CHECK-SD-LABEL: v2i16:214; CHECK-SD: // %bb.0:215; CHECK-SD-NEXT: ldr s0, [x0]216; CHECK-SD-NEXT: ldr s1, [x1]217; CHECK-SD-NEXT: ushll v0.4s, v0.4h, #0218; CHECK-SD-NEXT: ushll v1.4s, v1.4h, #0219; CHECK-SD-NEXT: shl v1.2s, v1.2s, #16220; CHECK-SD-NEXT: shl v0.2s, v0.2s, #16221; CHECK-SD-NEXT: sqsub v0.2s, v0.2s, v1.2s222; CHECK-SD-NEXT: ushr v0.2s, v0.2s, #16223; CHECK-SD-NEXT: mov s1, v0.s[1]224; CHECK-SD-NEXT: str h0, [x2]225; CHECK-SD-NEXT: str h1, [x2, #2]226; CHECK-SD-NEXT: ret227;228; CHECK-GI-LABEL: v2i16:229; CHECK-GI: // %bb.0:230; CHECK-GI-NEXT: ldr h0, [x0]231; CHECK-GI-NEXT: ldr h1, [x1]232; CHECK-GI-NEXT: add x8, x0, #2233; CHECK-GI-NEXT: add x9, x1, #2234; CHECK-GI-NEXT: ld1 { v0.h }[1], [x8]235; CHECK-GI-NEXT: ld1 { v1.h }[1], [x9]236; CHECK-GI-NEXT: add x8, x2, #2237; CHECK-GI-NEXT: sqsub v0.4h, v0.4h, v1.4h238; CHECK-GI-NEXT: str h0, [x2]239; CHECK-GI-NEXT: st1 { v0.h }[1], [x8]240; CHECK-GI-NEXT: ret241 %x = load <2 x i16>, ptr %px242 %y = load <2 x i16>, ptr %py243 %z = call <2 x i16> @llvm.ssub.sat.v2i16(<2 x i16> %x, <2 x i16> %y)244 store <2 x i16> %z, ptr %pz245 ret void246}247 248define <12 x i8> @v12i8(<12 x i8> %x, <12 x i8> %y) nounwind {249; CHECK-LABEL: v12i8:250; CHECK: // %bb.0:251; CHECK-NEXT: sqsub v0.16b, v0.16b, v1.16b252; CHECK-NEXT: ret253 %z = call <12 x i8> @llvm.ssub.sat.v12i8(<12 x i8> %x, <12 x i8> %y)254 ret <12 x i8> %z255}256 257define void @v12i16(ptr %px, ptr %py, ptr %pz) nounwind {258; CHECK-SD-LABEL: v12i16:259; CHECK-SD: // %bb.0:260; CHECK-SD-NEXT: ldp q0, q3, [x1]261; CHECK-SD-NEXT: ldp q1, q2, [x0]262; CHECK-SD-NEXT: sqsub v0.8h, v1.8h, v0.8h263; CHECK-SD-NEXT: sqsub v1.8h, v2.8h, v3.8h264; CHECK-SD-NEXT: str q0, [x2]265; CHECK-SD-NEXT: str d1, [x2, #16]266; CHECK-SD-NEXT: ret267;268; CHECK-GI-LABEL: v12i16:269; CHECK-GI: // %bb.0:270; CHECK-GI-NEXT: ldr q0, [x0]271; CHECK-GI-NEXT: ldr q1, [x1]272; CHECK-GI-NEXT: ldr d2, [x0, #16]273; CHECK-GI-NEXT: ldr d3, [x1, #16]274; CHECK-GI-NEXT: sqsub v0.8h, v0.8h, v1.8h275; CHECK-GI-NEXT: sqsub v1.4h, v2.4h, v3.4h276; CHECK-GI-NEXT: str q0, [x2]277; CHECK-GI-NEXT: str d1, [x2, #16]278; CHECK-GI-NEXT: ret279 %x = load <12 x i16>, ptr %px280 %y = load <12 x i16>, ptr %py281 %z = call <12 x i16> @llvm.ssub.sat.v12i16(<12 x i16> %x, <12 x i16> %y)282 store <12 x i16> %z, ptr %pz283 ret void284}285 286define void @v1i8(ptr %px, ptr %py, ptr %pz) nounwind {287; CHECK-SD-LABEL: v1i8:288; CHECK-SD: // %bb.0:289; CHECK-SD-NEXT: ldr b0, [x0]290; CHECK-SD-NEXT: ldr b1, [x1]291; CHECK-SD-NEXT: sqsub v0.8b, v0.8b, v1.8b292; CHECK-SD-NEXT: str b0, [x2]293; CHECK-SD-NEXT: ret294;295; CHECK-GI-LABEL: v1i8:296; CHECK-GI: // %bb.0:297; CHECK-GI-NEXT: ldrsb w8, [x0]298; CHECK-GI-NEXT: ldrsb w9, [x1]299; CHECK-GI-NEXT: sub w8, w8, w9300; CHECK-GI-NEXT: sxtb w9, w8301; CHECK-GI-NEXT: sbfx w10, w8, #7, #1302; CHECK-GI-NEXT: sub w10, w10, #128303; CHECK-GI-NEXT: cmp w8, w9304; CHECK-GI-NEXT: csel w8, w10, w8, ne305; CHECK-GI-NEXT: strb w8, [x2]306; CHECK-GI-NEXT: ret307 %x = load <1 x i8>, ptr %px308 %y = load <1 x i8>, ptr %py309 %z = call <1 x i8> @llvm.ssub.sat.v1i8(<1 x i8> %x, <1 x i8> %y)310 store <1 x i8> %z, ptr %pz311 ret void312}313 314define void @v1i16(ptr %px, ptr %py, ptr %pz) nounwind {315; CHECK-SD-LABEL: v1i16:316; CHECK-SD: // %bb.0:317; CHECK-SD-NEXT: ldr h0, [x0]318; CHECK-SD-NEXT: ldr h1, [x1]319; CHECK-SD-NEXT: sqsub v0.4h, v0.4h, v1.4h320; CHECK-SD-NEXT: str h0, [x2]321; CHECK-SD-NEXT: ret322;323; CHECK-GI-LABEL: v1i16:324; CHECK-GI: // %bb.0:325; CHECK-GI-NEXT: ldrsh w8, [x0]326; CHECK-GI-NEXT: ldrsh w9, [x1]327; CHECK-GI-NEXT: sub w8, w8, w9328; CHECK-GI-NEXT: sxth w9, w8329; CHECK-GI-NEXT: sbfx w10, w8, #15, #1330; CHECK-GI-NEXT: sub w10, w10, #8, lsl #12 // =32768331; CHECK-GI-NEXT: cmp w8, w9332; CHECK-GI-NEXT: csel w8, w10, w8, ne333; CHECK-GI-NEXT: strh w8, [x2]334; CHECK-GI-NEXT: ret335 %x = load <1 x i16>, ptr %px336 %y = load <1 x i16>, ptr %py337 %z = call <1 x i16> @llvm.ssub.sat.v1i16(<1 x i16> %x, <1 x i16> %y)338 store <1 x i16> %z, ptr %pz339 ret void340}341 342define <16 x i4> @v16i4(<16 x i4> %x, <16 x i4> %y) nounwind {343; CHECK-LABEL: v16i4:344; CHECK: // %bb.0:345; CHECK-NEXT: shl v1.16b, v1.16b, #4346; CHECK-NEXT: shl v0.16b, v0.16b, #4347; CHECK-NEXT: sqsub v0.16b, v0.16b, v1.16b348; CHECK-NEXT: sshr v0.16b, v0.16b, #4349; CHECK-NEXT: ret350 %z = call <16 x i4> @llvm.ssub.sat.v16i4(<16 x i4> %x, <16 x i4> %y)351 ret <16 x i4> %z352}353 354define <16 x i1> @v16i1(<16 x i1> %x, <16 x i1> %y) nounwind {355; CHECK-LABEL: v16i1:356; CHECK: // %bb.0:357; CHECK-NEXT: movi v2.16b, #1358; CHECK-NEXT: eor v1.16b, v1.16b, v2.16b359; CHECK-NEXT: and v0.16b, v0.16b, v1.16b360; CHECK-NEXT: ret361 %z = call <16 x i1> @llvm.ssub.sat.v16i1(<16 x i1> %x, <16 x i1> %y)362 ret <16 x i1> %z363}364 365define void @v1i32(ptr %px, ptr %py, ptr %pz) nounwind {366; CHECK-SD-LABEL: v1i32:367; CHECK-SD: // %bb.0:368; CHECK-SD-NEXT: ldr s0, [x0]369; CHECK-SD-NEXT: ldr s1, [x1]370; CHECK-SD-NEXT: sqsub v0.2s, v0.2s, v1.2s371; CHECK-SD-NEXT: str s0, [x2]372; CHECK-SD-NEXT: ret373;374; CHECK-GI-LABEL: v1i32:375; CHECK-GI: // %bb.0:376; CHECK-GI-NEXT: ldr w8, [x0]377; CHECK-GI-NEXT: ldr w9, [x1]378; CHECK-GI-NEXT: subs w8, w8, w9379; CHECK-GI-NEXT: mov w9, #-2147483648 // =0x80000000380; CHECK-GI-NEXT: cset w10, vs381; CHECK-GI-NEXT: add w9, w9, w8, asr #31382; CHECK-GI-NEXT: tst w10, #0x1383; CHECK-GI-NEXT: csel w8, w9, w8, ne384; CHECK-GI-NEXT: str w8, [x2]385; CHECK-GI-NEXT: ret386 %x = load <1 x i32>, ptr %px387 %y = load <1 x i32>, ptr %py388 %z = call <1 x i32> @llvm.ssub.sat.v1i32(<1 x i32> %x, <1 x i32> %y)389 store <1 x i32> %z, ptr %pz390 ret void391}392 393define <2 x i32> @v2i32(<2 x i32> %x, <2 x i32> %y) nounwind {394; CHECK-LABEL: v2i32:395; CHECK: // %bb.0:396; CHECK-NEXT: sqsub v0.2s, v0.2s, v1.2s397; CHECK-NEXT: ret398 %z = call <2 x i32> @llvm.ssub.sat.v2i32(<2 x i32> %x, <2 x i32> %y)399 ret <2 x i32> %z400}401 402define <4 x i32> @v4i32(<4 x i32> %x, <4 x i32> %y) nounwind {403; CHECK-LABEL: v4i32:404; CHECK: // %bb.0:405; CHECK-NEXT: sqsub v0.4s, v0.4s, v1.4s406; CHECK-NEXT: ret407 %z = call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> %x, <4 x i32> %y)408 ret <4 x i32> %z409}410 411define <8 x i32> @v8i32(<8 x i32> %x, <8 x i32> %y) nounwind {412; CHECK-SD-LABEL: v8i32:413; CHECK-SD: // %bb.0:414; CHECK-SD-NEXT: sqsub v1.4s, v1.4s, v3.4s415; CHECK-SD-NEXT: sqsub v0.4s, v0.4s, v2.4s416; CHECK-SD-NEXT: ret417;418; CHECK-GI-LABEL: v8i32:419; CHECK-GI: // %bb.0:420; CHECK-GI-NEXT: sqsub v0.4s, v0.4s, v2.4s421; CHECK-GI-NEXT: sqsub v1.4s, v1.4s, v3.4s422; CHECK-GI-NEXT: ret423 %z = call <8 x i32> @llvm.ssub.sat.v8i32(<8 x i32> %x, <8 x i32> %y)424 ret <8 x i32> %z425}426 427define <16 x i32> @v16i32(<16 x i32> %x, <16 x i32> %y) nounwind {428; CHECK-SD-LABEL: v16i32:429; CHECK-SD: // %bb.0:430; CHECK-SD-NEXT: sqsub v2.4s, v2.4s, v6.4s431; CHECK-SD-NEXT: sqsub v0.4s, v0.4s, v4.4s432; CHECK-SD-NEXT: sqsub v1.4s, v1.4s, v5.4s433; CHECK-SD-NEXT: sqsub v3.4s, v3.4s, v7.4s434; CHECK-SD-NEXT: ret435;436; CHECK-GI-LABEL: v16i32:437; CHECK-GI: // %bb.0:438; CHECK-GI-NEXT: sqsub v0.4s, v0.4s, v4.4s439; CHECK-GI-NEXT: sqsub v1.4s, v1.4s, v5.4s440; CHECK-GI-NEXT: sqsub v2.4s, v2.4s, v6.4s441; CHECK-GI-NEXT: sqsub v3.4s, v3.4s, v7.4s442; CHECK-GI-NEXT: ret443 %z = call <16 x i32> @llvm.ssub.sat.v16i32(<16 x i32> %x, <16 x i32> %y)444 ret <16 x i32> %z445}446 447define void @v1i64(ptr %px, ptr %py, ptr %pz) nounwind {448; CHECK-SD-LABEL: v1i64:449; CHECK-SD: // %bb.0:450; CHECK-SD-NEXT: ldr d0, [x0]451; CHECK-SD-NEXT: ldr d1, [x1]452; CHECK-SD-NEXT: sqsub d0, d0, d1453; CHECK-SD-NEXT: str d0, [x2]454; CHECK-SD-NEXT: ret455;456; CHECK-GI-LABEL: v1i64:457; CHECK-GI: // %bb.0:458; CHECK-GI-NEXT: ldr x8, [x0]459; CHECK-GI-NEXT: ldr x9, [x1]460; CHECK-GI-NEXT: subs x8, x8, x9461; CHECK-GI-NEXT: mov x9, #-9223372036854775808 // =0x8000000000000000462; CHECK-GI-NEXT: cset w10, vs463; CHECK-GI-NEXT: add x9, x9, x8, asr #63464; CHECK-GI-NEXT: tst w10, #0x1465; CHECK-GI-NEXT: csel x8, x9, x8, ne466; CHECK-GI-NEXT: str x8, [x2]467; CHECK-GI-NEXT: ret468 %x = load <1 x i64>, ptr %px469 %y = load <1 x i64>, ptr %py470 %z = call <1 x i64> @llvm.ssub.sat.v1i64(<1 x i64> %x, <1 x i64> %y)471 store <1 x i64> %z, ptr %pz472 ret void473}474 475define <2 x i64> @v2i64(<2 x i64> %x, <2 x i64> %y) nounwind {476; CHECK-LABEL: v2i64:477; CHECK: // %bb.0:478; CHECK-NEXT: sqsub v0.2d, v0.2d, v1.2d479; CHECK-NEXT: ret480 %z = call <2 x i64> @llvm.ssub.sat.v2i64(<2 x i64> %x, <2 x i64> %y)481 ret <2 x i64> %z482}483 484define <4 x i64> @v4i64(<4 x i64> %x, <4 x i64> %y) nounwind {485; CHECK-SD-LABEL: v4i64:486; CHECK-SD: // %bb.0:487; CHECK-SD-NEXT: sqsub v1.2d, v1.2d, v3.2d488; CHECK-SD-NEXT: sqsub v0.2d, v0.2d, v2.2d489; CHECK-SD-NEXT: ret490;491; CHECK-GI-LABEL: v4i64:492; CHECK-GI: // %bb.0:493; CHECK-GI-NEXT: sqsub v0.2d, v0.2d, v2.2d494; CHECK-GI-NEXT: sqsub v1.2d, v1.2d, v3.2d495; CHECK-GI-NEXT: ret496 %z = call <4 x i64> @llvm.ssub.sat.v4i64(<4 x i64> %x, <4 x i64> %y)497 ret <4 x i64> %z498}499 500define <8 x i64> @v8i64(<8 x i64> %x, <8 x i64> %y) nounwind {501; CHECK-SD-LABEL: v8i64:502; CHECK-SD: // %bb.0:503; CHECK-SD-NEXT: sqsub v2.2d, v2.2d, v6.2d504; CHECK-SD-NEXT: sqsub v0.2d, v0.2d, v4.2d505; CHECK-SD-NEXT: sqsub v1.2d, v1.2d, v5.2d506; CHECK-SD-NEXT: sqsub v3.2d, v3.2d, v7.2d507; CHECK-SD-NEXT: ret508;509; CHECK-GI-LABEL: v8i64:510; CHECK-GI: // %bb.0:511; CHECK-GI-NEXT: sqsub v0.2d, v0.2d, v4.2d512; CHECK-GI-NEXT: sqsub v1.2d, v1.2d, v5.2d513; CHECK-GI-NEXT: sqsub v2.2d, v2.2d, v6.2d514; CHECK-GI-NEXT: sqsub v3.2d, v3.2d, v7.2d515; CHECK-GI-NEXT: ret516 %z = call <8 x i64> @llvm.ssub.sat.v8i64(<8 x i64> %x, <8 x i64> %y)517 ret <8 x i64> %z518}519 520define <2 x i128> @v2i128(<2 x i128> %x, <2 x i128> %y) nounwind {521; CHECK-SD-LABEL: v2i128:522; CHECK-SD: // %bb.0:523; CHECK-SD-NEXT: subs x8, x0, x4524; CHECK-SD-NEXT: sbcs x9, x1, x5525; CHECK-SD-NEXT: asr x10, x9, #63526; CHECK-SD-NEXT: eor x11, x10, #0x8000000000000000527; CHECK-SD-NEXT: csel x0, x10, x8, vs528; CHECK-SD-NEXT: csel x1, x11, x9, vs529; CHECK-SD-NEXT: subs x8, x2, x6530; CHECK-SD-NEXT: sbcs x9, x3, x7531; CHECK-SD-NEXT: asr x10, x9, #63532; CHECK-SD-NEXT: eor x11, x10, #0x8000000000000000533; CHECK-SD-NEXT: csel x2, x10, x8, vs534; CHECK-SD-NEXT: csel x3, x11, x9, vs535; CHECK-SD-NEXT: ret536;537; CHECK-GI-LABEL: v2i128:538; CHECK-GI: // %bb.0:539; CHECK-GI-NEXT: subs x9, x0, x4540; CHECK-GI-NEXT: mov w8, wzr541; CHECK-GI-NEXT: mov x13, #-9223372036854775808 // =0x8000000000000000542; CHECK-GI-NEXT: sbcs x10, x1, x5543; CHECK-GI-NEXT: asr x11, x10, #63544; CHECK-GI-NEXT: cset w12, vs545; CHECK-GI-NEXT: cmp w8, #1546; CHECK-GI-NEXT: adc x14, x11, x13547; CHECK-GI-NEXT: tst w12, #0x1548; CHECK-GI-NEXT: csel x0, x11, x9, ne549; CHECK-GI-NEXT: csel x1, x14, x10, ne550; CHECK-GI-NEXT: subs x9, x2, x6551; CHECK-GI-NEXT: sbcs x10, x3, x7552; CHECK-GI-NEXT: asr x11, x10, #63553; CHECK-GI-NEXT: cset w12, vs554; CHECK-GI-NEXT: cmp w8, #1555; CHECK-GI-NEXT: adc x8, x11, x13556; CHECK-GI-NEXT: tst w12, #0x1557; CHECK-GI-NEXT: csel x2, x11, x9, ne558; CHECK-GI-NEXT: csel x3, x8, x10, ne559; CHECK-GI-NEXT: ret560 %z = call <2 x i128> @llvm.ssub.sat.v2i128(<2 x i128> %x, <2 x i128> %y)561 ret <2 x i128> %z562}563